1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7 #include <linux/gpio/driver.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 /* EIC registers definition */ 16 #define SPRD_PMIC_EIC_DATA 0x0 17 #define SPRD_PMIC_EIC_DMSK 0x4 18 #define SPRD_PMIC_EIC_IEV 0x14 19 #define SPRD_PMIC_EIC_IE 0x18 20 #define SPRD_PMIC_EIC_RIS 0x1c 21 #define SPRD_PMIC_EIC_MIS 0x20 22 #define SPRD_PMIC_EIC_IC 0x24 23 #define SPRD_PMIC_EIC_TRIG 0x28 24 #define SPRD_PMIC_EIC_CTRL0 0x40 25 26 /* 27 * The PMIC EIC controller only has one bank, and each bank now can contain 28 * 16 EICs. 29 */ 30 #define SPRD_PMIC_EIC_PER_BANK_NR 16 31 #define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR 32 #define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0) 33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1)) 34 #define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0) 35 36 /* 37 * These registers are modified under the irq bus lock and cached to avoid 38 * unnecessary writes in bus_sync_unlock. 39 */ 40 enum { 41 REG_IEV, 42 REG_IE, 43 REG_TRIG, 44 CACHE_NR_REGS 45 }; 46 47 /** 48 * struct sprd_pmic_eic - PMIC EIC controller 49 * @chip: the gpio_chip structure. 50 * @map: the regmap from the parent device. 51 * @offset: the EIC controller's offset address of the PMIC. 52 * @reg: the array to cache the EIC registers. 53 * @buslock: for bus lock/sync and unlock. 54 * @irq: the interrupt number of the PMIC EIC conteroller. 55 */ 56 struct sprd_pmic_eic { 57 struct gpio_chip chip; 58 struct regmap *map; 59 u32 offset; 60 u8 reg[CACHE_NR_REGS]; 61 struct mutex buslock; 62 int irq; 63 }; 64 65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, 66 u16 reg, unsigned int val) 67 { 68 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 69 u32 shift = SPRD_PMIC_EIC_BIT(offset); 70 71 regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg, 72 BIT(shift), val << shift); 73 } 74 75 static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset, 76 u16 reg) 77 { 78 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 79 u32 value; 80 int ret; 81 82 ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); 83 if (ret) 84 return ret; 85 86 return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset))); 87 } 88 89 static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset) 90 { 91 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1); 92 return 0; 93 } 94 95 static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset) 96 { 97 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0); 98 } 99 100 static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset) 101 { 102 return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA); 103 } 104 105 static int sprd_pmic_eic_direction_input(struct gpio_chip *chip, 106 unsigned int offset) 107 { 108 /* EICs are always input, nothing need to do here. */ 109 return 0; 110 } 111 112 static void sprd_pmic_eic_set(struct gpio_chip *chip, unsigned int offset, 113 int value) 114 { 115 /* EICs are always input, nothing need to do here. */ 116 } 117 118 static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip, 119 unsigned int offset, 120 unsigned int debounce) 121 { 122 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 123 u32 reg, value; 124 int ret; 125 126 reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4; 127 ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); 128 if (ret) 129 return ret; 130 131 value &= ~SPRD_PMIC_EIC_DBNC_MASK; 132 value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK; 133 return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value); 134 } 135 136 static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset, 137 unsigned long config) 138 { 139 unsigned long param = pinconf_to_config_param(config); 140 u32 arg = pinconf_to_config_argument(config); 141 142 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 143 return sprd_pmic_eic_set_debounce(chip, offset, arg); 144 145 return -ENOTSUPP; 146 } 147 148 static void sprd_pmic_eic_irq_mask(struct irq_data *data) 149 { 150 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 151 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 152 u32 offset = irqd_to_hwirq(data); 153 154 pmic_eic->reg[REG_IE] = 0; 155 pmic_eic->reg[REG_TRIG] = 0; 156 157 gpiochip_disable_irq(chip, offset); 158 } 159 160 static void sprd_pmic_eic_irq_unmask(struct irq_data *data) 161 { 162 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 163 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 164 u32 offset = irqd_to_hwirq(data); 165 166 gpiochip_enable_irq(chip, offset); 167 168 pmic_eic->reg[REG_IE] = 1; 169 pmic_eic->reg[REG_TRIG] = 1; 170 } 171 172 static int sprd_pmic_eic_irq_set_type(struct irq_data *data, 173 unsigned int flow_type) 174 { 175 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 176 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 177 178 switch (flow_type) { 179 case IRQ_TYPE_LEVEL_HIGH: 180 pmic_eic->reg[REG_IEV] = 1; 181 break; 182 case IRQ_TYPE_LEVEL_LOW: 183 pmic_eic->reg[REG_IEV] = 0; 184 break; 185 case IRQ_TYPE_EDGE_RISING: 186 case IRQ_TYPE_EDGE_FALLING: 187 case IRQ_TYPE_EDGE_BOTH: 188 /* 189 * Will set the trigger level according to current EIC level 190 * in irq_bus_sync_unlock() interface, so here nothing to do. 191 */ 192 break; 193 default: 194 return -ENOTSUPP; 195 } 196 197 return 0; 198 } 199 200 static void sprd_pmic_eic_bus_lock(struct irq_data *data) 201 { 202 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 203 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 204 205 mutex_lock(&pmic_eic->buslock); 206 } 207 208 static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data) 209 { 210 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 211 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 212 u32 trigger = irqd_get_trigger_type(data); 213 u32 offset = irqd_to_hwirq(data); 214 int state; 215 216 /* Set irq type */ 217 if (trigger & IRQ_TYPE_EDGE_BOTH) { 218 state = sprd_pmic_eic_get(chip, offset); 219 if (state) 220 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); 221 else 222 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); 223 } else { 224 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 225 pmic_eic->reg[REG_IEV]); 226 } 227 228 /* Set irq unmask */ 229 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 230 pmic_eic->reg[REG_IE]); 231 /* Generate trigger start pulse for debounce EIC */ 232 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 233 pmic_eic->reg[REG_TRIG]); 234 235 mutex_unlock(&pmic_eic->buslock); 236 } 237 238 static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip, 239 unsigned int irq, unsigned int offset) 240 { 241 u32 trigger = irq_get_trigger_type(irq); 242 int state, post_state; 243 244 if (!(trigger & IRQ_TYPE_EDGE_BOTH)) 245 return; 246 247 state = sprd_pmic_eic_get(chip, offset); 248 retry: 249 if (state) 250 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); 251 else 252 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); 253 254 post_state = sprd_pmic_eic_get(chip, offset); 255 if (state != post_state) { 256 dev_warn(chip->parent, "PMIC EIC level was changed.\n"); 257 state = post_state; 258 goto retry; 259 } 260 261 /* Set irq unmask */ 262 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1); 263 /* Generate trigger start pulse for debounce EIC */ 264 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1); 265 } 266 267 static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data) 268 { 269 struct sprd_pmic_eic *pmic_eic = data; 270 struct gpio_chip *chip = &pmic_eic->chip; 271 unsigned long status; 272 u32 n, girq, val; 273 int ret; 274 275 ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS, 276 &val); 277 if (ret) 278 return IRQ_RETVAL(ret); 279 280 status = val & SPRD_PMIC_EIC_DATA_MASK; 281 282 for_each_set_bit(n, &status, chip->ngpio) { 283 /* Clear the interrupt */ 284 sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1); 285 286 girq = irq_find_mapping(chip->irq.domain, n); 287 handle_nested_irq(girq); 288 289 /* 290 * The PMIC EIC can only support level trigger, so we can 291 * toggle the level trigger to emulate the edge trigger. 292 */ 293 sprd_pmic_eic_toggle_trigger(chip, girq, n); 294 } 295 296 return IRQ_HANDLED; 297 } 298 299 static const struct irq_chip pmic_eic_irq_chip = { 300 .name = "sprd-pmic-eic", 301 .irq_mask = sprd_pmic_eic_irq_mask, 302 .irq_unmask = sprd_pmic_eic_irq_unmask, 303 .irq_set_type = sprd_pmic_eic_irq_set_type, 304 .irq_bus_lock = sprd_pmic_eic_bus_lock, 305 .irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock, 306 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 307 GPIOCHIP_IRQ_RESOURCE_HELPERS, 308 }; 309 310 static int sprd_pmic_eic_probe(struct platform_device *pdev) 311 { 312 struct gpio_irq_chip *irq; 313 struct sprd_pmic_eic *pmic_eic; 314 int ret; 315 316 pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL); 317 if (!pmic_eic) 318 return -ENOMEM; 319 320 mutex_init(&pmic_eic->buslock); 321 322 pmic_eic->irq = platform_get_irq(pdev, 0); 323 if (pmic_eic->irq < 0) 324 return pmic_eic->irq; 325 326 pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL); 327 if (!pmic_eic->map) 328 return -ENODEV; 329 330 ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset); 331 if (ret) { 332 dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n"); 333 return ret; 334 } 335 336 ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL, 337 sprd_pmic_eic_irq_handler, 338 IRQF_ONESHOT | IRQF_NO_SUSPEND, 339 dev_name(&pdev->dev), pmic_eic); 340 if (ret) { 341 dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n"); 342 return ret; 343 } 344 345 pmic_eic->chip.label = dev_name(&pdev->dev); 346 pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR; 347 pmic_eic->chip.base = -1; 348 pmic_eic->chip.parent = &pdev->dev; 349 pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input; 350 pmic_eic->chip.request = sprd_pmic_eic_request; 351 pmic_eic->chip.free = sprd_pmic_eic_free; 352 pmic_eic->chip.set_config = sprd_pmic_eic_set_config; 353 pmic_eic->chip.set = sprd_pmic_eic_set; 354 pmic_eic->chip.get = sprd_pmic_eic_get; 355 356 irq = &pmic_eic->chip.irq; 357 gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip); 358 irq->threaded = true; 359 360 ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic); 361 if (ret < 0) { 362 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 363 return ret; 364 } 365 366 return 0; 367 } 368 369 static const struct of_device_id sprd_pmic_eic_of_match[] = { 370 { .compatible = "sprd,sc2731-eic", }, 371 { /* end of list */ } 372 }; 373 MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match); 374 375 static struct platform_driver sprd_pmic_eic_driver = { 376 .probe = sprd_pmic_eic_probe, 377 .driver = { 378 .name = "sprd-pmic-eic", 379 .of_match_table = sprd_pmic_eic_of_match, 380 }, 381 }; 382 383 module_platform_driver(sprd_pmic_eic_driver); 384 385 MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver"); 386 MODULE_LICENSE("GPL v2"); 387