1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2018 Spreadtrum Communications Inc. 4 * Copyright (C) 2018 Linaro Ltd. 5 */ 6 7 #include <linux/gpio/driver.h> 8 #include <linux/interrupt.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 /* EIC registers definition */ 16 #define SPRD_PMIC_EIC_DATA 0x0 17 #define SPRD_PMIC_EIC_DMSK 0x4 18 #define SPRD_PMIC_EIC_IEV 0x14 19 #define SPRD_PMIC_EIC_IE 0x18 20 #define SPRD_PMIC_EIC_RIS 0x1c 21 #define SPRD_PMIC_EIC_MIS 0x20 22 #define SPRD_PMIC_EIC_IC 0x24 23 #define SPRD_PMIC_EIC_TRIG 0x28 24 #define SPRD_PMIC_EIC_CTRL0 0x40 25 26 /* 27 * The PMIC EIC controller only has one bank, and each bank now can contain 28 * 16 EICs. 29 */ 30 #define SPRD_PMIC_EIC_PER_BANK_NR 16 31 #define SPRD_PMIC_EIC_NR SPRD_PMIC_EIC_PER_BANK_NR 32 #define SPRD_PMIC_EIC_DATA_MASK GENMASK(15, 0) 33 #define SPRD_PMIC_EIC_BIT(x) ((x) & (SPRD_PMIC_EIC_PER_BANK_NR - 1)) 34 #define SPRD_PMIC_EIC_DBNC_MASK GENMASK(11, 0) 35 36 /* 37 * These registers are modified under the irq bus lock and cached to avoid 38 * unnecessary writes in bus_sync_unlock. 39 */ 40 enum { 41 REG_IEV, 42 REG_IE, 43 REG_TRIG, 44 CACHE_NR_REGS 45 }; 46 47 /** 48 * struct sprd_pmic_eic - PMIC EIC controller 49 * @chip: the gpio_chip structure. 50 * @map: the regmap from the parent device. 51 * @offset: the EIC controller's offset address of the PMIC. 52 * @reg: the array to cache the EIC registers. 53 * @buslock: for bus lock/sync and unlock. 54 * @irq: the interrupt number of the PMIC EIC conteroller. 55 */ 56 struct sprd_pmic_eic { 57 struct gpio_chip chip; 58 struct regmap *map; 59 u32 offset; 60 u8 reg[CACHE_NR_REGS]; 61 struct mutex buslock; 62 int irq; 63 }; 64 65 static void sprd_pmic_eic_update(struct gpio_chip *chip, unsigned int offset, 66 u16 reg, unsigned int val) 67 { 68 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 69 u32 shift = SPRD_PMIC_EIC_BIT(offset); 70 71 regmap_update_bits(pmic_eic->map, pmic_eic->offset + reg, 72 BIT(shift), val << shift); 73 } 74 75 static int sprd_pmic_eic_read(struct gpio_chip *chip, unsigned int offset, 76 u16 reg) 77 { 78 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 79 u32 value; 80 int ret; 81 82 ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); 83 if (ret) 84 return ret; 85 86 return !!(value & BIT(SPRD_PMIC_EIC_BIT(offset))); 87 } 88 89 static int sprd_pmic_eic_request(struct gpio_chip *chip, unsigned int offset) 90 { 91 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 1); 92 return 0; 93 } 94 95 static void sprd_pmic_eic_free(struct gpio_chip *chip, unsigned int offset) 96 { 97 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_DMSK, 0); 98 } 99 100 static int sprd_pmic_eic_get(struct gpio_chip *chip, unsigned int offset) 101 { 102 return sprd_pmic_eic_read(chip, offset, SPRD_PMIC_EIC_DATA); 103 } 104 105 static int sprd_pmic_eic_direction_input(struct gpio_chip *chip, 106 unsigned int offset) 107 { 108 /* EICs are always input, nothing need to do here. */ 109 return 0; 110 } 111 112 static int sprd_pmic_eic_set_debounce(struct gpio_chip *chip, 113 unsigned int offset, 114 unsigned int debounce) 115 { 116 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 117 u32 reg, value; 118 int ret; 119 120 reg = SPRD_PMIC_EIC_CTRL0 + SPRD_PMIC_EIC_BIT(offset) * 0x4; 121 ret = regmap_read(pmic_eic->map, pmic_eic->offset + reg, &value); 122 if (ret) 123 return ret; 124 125 value &= ~SPRD_PMIC_EIC_DBNC_MASK; 126 value |= (debounce / 1000) & SPRD_PMIC_EIC_DBNC_MASK; 127 return regmap_write(pmic_eic->map, pmic_eic->offset + reg, value); 128 } 129 130 static int sprd_pmic_eic_set_config(struct gpio_chip *chip, unsigned int offset, 131 unsigned long config) 132 { 133 unsigned long param = pinconf_to_config_param(config); 134 u32 arg = pinconf_to_config_argument(config); 135 136 if (param == PIN_CONFIG_INPUT_DEBOUNCE) 137 return sprd_pmic_eic_set_debounce(chip, offset, arg); 138 139 return -ENOTSUPP; 140 } 141 142 static void sprd_pmic_eic_irq_mask(struct irq_data *data) 143 { 144 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 145 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 146 u32 offset = irqd_to_hwirq(data); 147 148 pmic_eic->reg[REG_IE] &= ~BIT(offset); 149 pmic_eic->reg[REG_TRIG] &= ~BIT(offset); 150 151 gpiochip_disable_irq(chip, offset); 152 } 153 154 static void sprd_pmic_eic_irq_unmask(struct irq_data *data) 155 { 156 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 157 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 158 u32 offset = irqd_to_hwirq(data); 159 160 gpiochip_enable_irq(chip, offset); 161 162 pmic_eic->reg[REG_IE] |= BIT(offset); 163 pmic_eic->reg[REG_TRIG] |= BIT(offset); 164 } 165 166 static int sprd_pmic_eic_irq_set_type(struct irq_data *data, 167 unsigned int flow_type) 168 { 169 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 170 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 171 u32 offset = irqd_to_hwirq(data); 172 173 switch (flow_type) { 174 case IRQ_TYPE_LEVEL_HIGH: 175 pmic_eic->reg[REG_IEV] |= BIT(offset); 176 break; 177 case IRQ_TYPE_LEVEL_LOW: 178 pmic_eic->reg[REG_IEV] &= ~BIT(offset); 179 break; 180 case IRQ_TYPE_EDGE_RISING: 181 case IRQ_TYPE_EDGE_FALLING: 182 case IRQ_TYPE_EDGE_BOTH: 183 /* 184 * Will set the trigger level according to current EIC level 185 * in irq_bus_sync_unlock() interface, so here nothing to do. 186 */ 187 break; 188 default: 189 return -ENOTSUPP; 190 } 191 192 return 0; 193 } 194 195 static void sprd_pmic_eic_bus_lock(struct irq_data *data) 196 { 197 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 198 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 199 200 mutex_lock(&pmic_eic->buslock); 201 } 202 203 static void sprd_pmic_eic_bus_sync_unlock(struct irq_data *data) 204 { 205 struct gpio_chip *chip = irq_data_get_irq_chip_data(data); 206 struct sprd_pmic_eic *pmic_eic = gpiochip_get_data(chip); 207 u32 trigger = irqd_get_trigger_type(data); 208 u32 offset = irqd_to_hwirq(data); 209 int state; 210 211 /* Set irq type */ 212 if (trigger & IRQ_TYPE_EDGE_BOTH) { 213 state = sprd_pmic_eic_get(chip, offset); 214 if (state) 215 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); 216 else 217 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); 218 } else { 219 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 220 !!(pmic_eic->reg[REG_IEV] & BIT(offset))); 221 } 222 223 /* Set irq unmask */ 224 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 225 !!(pmic_eic->reg[REG_IE] & BIT(offset))); 226 /* Generate trigger start pulse for debounce EIC */ 227 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 228 !!(pmic_eic->reg[REG_TRIG] & BIT(offset))); 229 230 mutex_unlock(&pmic_eic->buslock); 231 } 232 233 static void sprd_pmic_eic_toggle_trigger(struct gpio_chip *chip, 234 unsigned int irq, unsigned int offset) 235 { 236 u32 trigger = irq_get_trigger_type(irq); 237 int state, post_state; 238 239 if (!(trigger & IRQ_TYPE_EDGE_BOTH)) 240 return; 241 242 state = sprd_pmic_eic_get(chip, offset); 243 retry: 244 if (state) 245 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 0); 246 else 247 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IEV, 1); 248 249 post_state = sprd_pmic_eic_get(chip, offset); 250 if (state != post_state) { 251 dev_warn(chip->parent, "PMIC EIC level was changed.\n"); 252 state = post_state; 253 goto retry; 254 } 255 256 /* Set irq unmask */ 257 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_IE, 1); 258 /* Generate trigger start pulse for debounce EIC */ 259 sprd_pmic_eic_update(chip, offset, SPRD_PMIC_EIC_TRIG, 1); 260 } 261 262 static irqreturn_t sprd_pmic_eic_irq_handler(int irq, void *data) 263 { 264 struct sprd_pmic_eic *pmic_eic = data; 265 struct gpio_chip *chip = &pmic_eic->chip; 266 unsigned long status; 267 u32 n, girq, val; 268 int ret; 269 270 ret = regmap_read(pmic_eic->map, pmic_eic->offset + SPRD_PMIC_EIC_MIS, 271 &val); 272 if (ret) 273 return IRQ_RETVAL(ret); 274 275 status = val & SPRD_PMIC_EIC_DATA_MASK; 276 277 for_each_set_bit(n, &status, chip->ngpio) { 278 /* Clear the interrupt */ 279 sprd_pmic_eic_update(chip, n, SPRD_PMIC_EIC_IC, 1); 280 281 girq = irq_find_mapping(chip->irq.domain, n); 282 handle_nested_irq(girq); 283 284 /* 285 * The PMIC EIC can only support level trigger, so we can 286 * toggle the level trigger to emulate the edge trigger. 287 */ 288 sprd_pmic_eic_toggle_trigger(chip, girq, n); 289 } 290 291 return IRQ_HANDLED; 292 } 293 294 static const struct irq_chip pmic_eic_irq_chip = { 295 .name = "sprd-pmic-eic", 296 .irq_mask = sprd_pmic_eic_irq_mask, 297 .irq_unmask = sprd_pmic_eic_irq_unmask, 298 .irq_set_type = sprd_pmic_eic_irq_set_type, 299 .irq_bus_lock = sprd_pmic_eic_bus_lock, 300 .irq_bus_sync_unlock = sprd_pmic_eic_bus_sync_unlock, 301 .flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_IMMUTABLE, 302 GPIOCHIP_IRQ_RESOURCE_HELPERS, 303 }; 304 305 static int sprd_pmic_eic_probe(struct platform_device *pdev) 306 { 307 struct gpio_irq_chip *irq; 308 struct sprd_pmic_eic *pmic_eic; 309 int ret; 310 311 pmic_eic = devm_kzalloc(&pdev->dev, sizeof(*pmic_eic), GFP_KERNEL); 312 if (!pmic_eic) 313 return -ENOMEM; 314 315 mutex_init(&pmic_eic->buslock); 316 317 pmic_eic->irq = platform_get_irq(pdev, 0); 318 if (pmic_eic->irq < 0) 319 return pmic_eic->irq; 320 321 pmic_eic->map = dev_get_regmap(pdev->dev.parent, NULL); 322 if (!pmic_eic->map) 323 return -ENODEV; 324 325 ret = of_property_read_u32(pdev->dev.of_node, "reg", &pmic_eic->offset); 326 if (ret) { 327 dev_err(&pdev->dev, "Failed to get PMIC EIC base address.\n"); 328 return ret; 329 } 330 331 ret = devm_request_threaded_irq(&pdev->dev, pmic_eic->irq, NULL, 332 sprd_pmic_eic_irq_handler, 333 IRQF_ONESHOT | IRQF_NO_SUSPEND, 334 dev_name(&pdev->dev), pmic_eic); 335 if (ret) { 336 dev_err(&pdev->dev, "Failed to request PMIC EIC IRQ.\n"); 337 return ret; 338 } 339 340 pmic_eic->chip.label = dev_name(&pdev->dev); 341 pmic_eic->chip.ngpio = SPRD_PMIC_EIC_NR; 342 pmic_eic->chip.base = -1; 343 pmic_eic->chip.parent = &pdev->dev; 344 pmic_eic->chip.direction_input = sprd_pmic_eic_direction_input; 345 pmic_eic->chip.request = sprd_pmic_eic_request; 346 pmic_eic->chip.free = sprd_pmic_eic_free; 347 pmic_eic->chip.set_config = sprd_pmic_eic_set_config; 348 pmic_eic->chip.get = sprd_pmic_eic_get; 349 pmic_eic->chip.can_sleep = true; 350 351 irq = &pmic_eic->chip.irq; 352 gpio_irq_chip_set_chip(irq, &pmic_eic_irq_chip); 353 irq->threaded = true; 354 355 ret = devm_gpiochip_add_data(&pdev->dev, &pmic_eic->chip, pmic_eic); 356 if (ret < 0) { 357 dev_err(&pdev->dev, "Could not register gpiochip %d.\n", ret); 358 return ret; 359 } 360 361 return 0; 362 } 363 364 static const struct of_device_id sprd_pmic_eic_of_match[] = { 365 { .compatible = "sprd,sc2731-eic", }, 366 { /* end of list */ } 367 }; 368 MODULE_DEVICE_TABLE(of, sprd_pmic_eic_of_match); 369 370 static struct platform_driver sprd_pmic_eic_driver = { 371 .probe = sprd_pmic_eic_probe, 372 .driver = { 373 .name = "sprd-pmic-eic", 374 .of_match_table = sprd_pmic_eic_of_match, 375 }, 376 }; 377 378 module_platform_driver(sprd_pmic_eic_driver); 379 380 MODULE_DESCRIPTION("Spreadtrum PMIC EIC driver"); 381 MODULE_LICENSE("GPL v2"); 382