1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, 2009 Provigent Ltd. 4 * 5 * Author: Baruch Siach <baruch@tkos.co.il> 6 * 7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 8 * 9 * Data sheet: ARM DDI 0190B, September 2000 10 */ 11 #include <linux/amba/bus.h> 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/errno.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/module.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 29 #define GPIODIR 0x400 30 #define GPIOIS 0x404 31 #define GPIOIBE 0x408 32 #define GPIOIEV 0x40C 33 #define GPIOIE 0x410 34 #define GPIORIS 0x414 35 #define GPIOMIS 0x418 36 #define GPIOIC 0x41C 37 38 #define PL061_GPIO_NR 8 39 40 struct pl061_context_save_regs { 41 u8 gpio_data; 42 u8 gpio_dir; 43 u8 gpio_is; 44 u8 gpio_ibe; 45 u8 gpio_iev; 46 u8 gpio_ie; 47 }; 48 49 struct pl061 { 50 raw_spinlock_t lock; 51 52 void __iomem *base; 53 struct gpio_chip gc; 54 int parent_irq; 55 56 struct pl061_context_save_regs csave_regs; 57 }; 58 59 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 60 { 61 struct pl061 *pl061 = gpiochip_get_data(gc); 62 63 if (readb(pl061->base + GPIODIR) & BIT(offset)) 64 return GPIO_LINE_DIRECTION_OUT; 65 66 return GPIO_LINE_DIRECTION_IN; 67 } 68 69 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 70 { 71 struct pl061 *pl061 = gpiochip_get_data(gc); 72 unsigned long flags; 73 unsigned char gpiodir; 74 75 raw_spin_lock_irqsave(&pl061->lock, flags); 76 gpiodir = readb(pl061->base + GPIODIR); 77 gpiodir &= ~(BIT(offset)); 78 writeb(gpiodir, pl061->base + GPIODIR); 79 raw_spin_unlock_irqrestore(&pl061->lock, flags); 80 81 return 0; 82 } 83 84 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 85 int value) 86 { 87 struct pl061 *pl061 = gpiochip_get_data(gc); 88 unsigned long flags; 89 unsigned char gpiodir; 90 91 raw_spin_lock_irqsave(&pl061->lock, flags); 92 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 93 gpiodir = readb(pl061->base + GPIODIR); 94 gpiodir |= BIT(offset); 95 writeb(gpiodir, pl061->base + GPIODIR); 96 97 /* 98 * gpio value is set again, because pl061 doesn't allow to set value of 99 * a gpio pin before configuring it in OUT mode. 100 */ 101 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 102 raw_spin_unlock_irqrestore(&pl061->lock, flags); 103 104 return 0; 105 } 106 107 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 108 { 109 struct pl061 *pl061 = gpiochip_get_data(gc); 110 111 return !!readb(pl061->base + (BIT(offset + 2))); 112 } 113 114 static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value) 115 { 116 struct pl061 *pl061 = gpiochip_get_data(gc); 117 118 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 119 120 return 0; 121 } 122 123 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 124 { 125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 126 struct pl061 *pl061 = gpiochip_get_data(gc); 127 int offset = irqd_to_hwirq(d); 128 unsigned long flags; 129 u8 gpiois, gpioibe, gpioiev; 130 u8 bit = BIT(offset); 131 132 if (offset < 0 || offset >= PL061_GPIO_NR) 133 return -EINVAL; 134 135 if ((trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) && 136 (trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))) 137 { 138 dev_err(gc->parent, 139 "trying to configure line %d for both level and edge " 140 "detection, choose one!\n", 141 offset); 142 return -EINVAL; 143 } 144 145 146 raw_spin_lock_irqsave(&pl061->lock, flags); 147 148 gpioiev = readb(pl061->base + GPIOIEV); 149 gpiois = readb(pl061->base + GPIOIS); 150 gpioibe = readb(pl061->base + GPIOIBE); 151 152 if (trigger & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { 153 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 154 155 /* Disable edge detection */ 156 gpioibe &= ~bit; 157 /* Enable level detection */ 158 gpiois |= bit; 159 /* Select polarity */ 160 if (polarity) 161 gpioiev |= bit; 162 else 163 gpioiev &= ~bit; 164 irq_set_handler_locked(d, handle_level_irq); 165 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 166 offset, 167 polarity ? "HIGH" : "LOW"); 168 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 169 /* Disable level detection */ 170 gpiois &= ~bit; 171 /* Select both edges, setting this makes GPIOEV be ignored */ 172 gpioibe |= bit; 173 irq_set_handler_locked(d, handle_edge_irq); 174 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 175 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 176 (trigger & IRQ_TYPE_EDGE_FALLING)) { 177 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 178 179 /* Disable level detection */ 180 gpiois &= ~bit; 181 /* Clear detection on both edges */ 182 gpioibe &= ~bit; 183 /* Select edge */ 184 if (rising) 185 gpioiev |= bit; 186 else 187 gpioiev &= ~bit; 188 irq_set_handler_locked(d, handle_edge_irq); 189 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 190 offset, 191 rising ? "RISING" : "FALLING"); 192 } else { 193 /* No trigger: disable everything */ 194 gpiois &= ~bit; 195 gpioibe &= ~bit; 196 gpioiev &= ~bit; 197 irq_set_handler_locked(d, handle_bad_irq); 198 dev_warn(gc->parent, "no trigger selected for line %d\n", 199 offset); 200 } 201 202 writeb(gpiois, pl061->base + GPIOIS); 203 writeb(gpioibe, pl061->base + GPIOIBE); 204 writeb(gpioiev, pl061->base + GPIOIEV); 205 206 raw_spin_unlock_irqrestore(&pl061->lock, flags); 207 208 return 0; 209 } 210 211 static void pl061_irq_handler(struct irq_desc *desc) 212 { 213 unsigned long pending; 214 int offset; 215 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 216 struct pl061 *pl061 = gpiochip_get_data(gc); 217 struct irq_chip *irqchip = irq_desc_get_chip(desc); 218 219 chained_irq_enter(irqchip, desc); 220 221 pending = readb(pl061->base + GPIOMIS); 222 if (pending) { 223 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 224 generic_handle_domain_irq(gc->irq.domain, 225 offset); 226 } 227 228 chained_irq_exit(irqchip, desc); 229 } 230 231 static void pl061_irq_mask(struct irq_data *d) 232 { 233 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 234 struct pl061 *pl061 = gpiochip_get_data(gc); 235 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 236 u8 gpioie; 237 238 raw_spin_lock(&pl061->lock); 239 gpioie = readb(pl061->base + GPIOIE) & ~mask; 240 writeb(gpioie, pl061->base + GPIOIE); 241 raw_spin_unlock(&pl061->lock); 242 243 gpiochip_disable_irq(gc, d->hwirq); 244 } 245 246 static void pl061_irq_unmask(struct irq_data *d) 247 { 248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 249 struct pl061 *pl061 = gpiochip_get_data(gc); 250 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 251 u8 gpioie; 252 253 gpiochip_enable_irq(gc, d->hwirq); 254 255 raw_spin_lock(&pl061->lock); 256 gpioie = readb(pl061->base + GPIOIE) | mask; 257 writeb(gpioie, pl061->base + GPIOIE); 258 raw_spin_unlock(&pl061->lock); 259 } 260 261 /** 262 * pl061_irq_ack() - ACK an edge IRQ 263 * @d: IRQ data for this IRQ 264 * 265 * This gets called from the edge IRQ handler to ACK the edge IRQ 266 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 267 * not needed: these go away when the level signal goes away. 268 */ 269 static void pl061_irq_ack(struct irq_data *d) 270 { 271 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 272 struct pl061 *pl061 = gpiochip_get_data(gc); 273 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 274 275 raw_spin_lock(&pl061->lock); 276 writeb(mask, pl061->base + GPIOIC); 277 raw_spin_unlock(&pl061->lock); 278 } 279 280 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 281 { 282 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 283 struct pl061 *pl061 = gpiochip_get_data(gc); 284 285 return irq_set_irq_wake(pl061->parent_irq, state); 286 } 287 288 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p) 289 { 290 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 291 292 seq_puts(p, dev_name(gc->parent)); 293 } 294 295 static const struct irq_chip pl061_irq_chip = { 296 .irq_ack = pl061_irq_ack, 297 .irq_mask = pl061_irq_mask, 298 .irq_unmask = pl061_irq_unmask, 299 .irq_set_type = pl061_irq_type, 300 .irq_set_wake = pl061_irq_set_wake, 301 .irq_print_chip = pl061_irq_print_chip, 302 .flags = IRQCHIP_IMMUTABLE, 303 GPIOCHIP_IRQ_RESOURCE_HELPERS, 304 }; 305 306 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 307 { 308 struct device *dev = &adev->dev; 309 struct pl061 *pl061; 310 struct gpio_irq_chip *girq; 311 int ret, irq; 312 313 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 314 if (pl061 == NULL) 315 return -ENOMEM; 316 317 pl061->base = devm_ioremap_resource(dev, &adev->res); 318 if (IS_ERR(pl061->base)) 319 return PTR_ERR(pl061->base); 320 321 raw_spin_lock_init(&pl061->lock); 322 pl061->gc.request = gpiochip_generic_request; 323 pl061->gc.free = gpiochip_generic_free; 324 pl061->gc.base = -1; 325 pl061->gc.get_direction = pl061_get_direction; 326 pl061->gc.direction_input = pl061_direction_input; 327 pl061->gc.direction_output = pl061_direction_output; 328 pl061->gc.get = pl061_get_value; 329 pl061->gc.set = pl061_set_value; 330 pl061->gc.ngpio = PL061_GPIO_NR; 331 pl061->gc.label = dev_name(dev); 332 pl061->gc.parent = dev; 333 pl061->gc.owner = THIS_MODULE; 334 335 /* 336 * irq_chip support 337 */ 338 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 339 irq = adev->irq[0]; 340 if (!irq) 341 dev_warn(&adev->dev, "IRQ support disabled\n"); 342 pl061->parent_irq = irq; 343 344 girq = &pl061->gc.irq; 345 gpio_irq_chip_set_chip(girq, &pl061_irq_chip); 346 girq->parent_handler = pl061_irq_handler; 347 girq->num_parents = 1; 348 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 349 GFP_KERNEL); 350 if (!girq->parents) 351 return -ENOMEM; 352 girq->parents[0] = irq; 353 girq->default_type = IRQ_TYPE_NONE; 354 girq->handler = handle_bad_irq; 355 356 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); 357 if (ret) 358 return ret; 359 360 amba_set_drvdata(adev, pl061); 361 dev_info(dev, "PL061 GPIO chip registered\n"); 362 363 return 0; 364 } 365 366 static int pl061_suspend(struct device *dev) 367 { 368 struct pl061 *pl061 = dev_get_drvdata(dev); 369 int offset; 370 371 pl061->csave_regs.gpio_data = 0; 372 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 373 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 374 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 375 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 376 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 377 378 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 379 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 380 pl061->csave_regs.gpio_data |= 381 pl061_get_value(&pl061->gc, offset) << offset; 382 } 383 384 return 0; 385 } 386 387 static int pl061_resume(struct device *dev) 388 { 389 struct pl061 *pl061 = dev_get_drvdata(dev); 390 int offset; 391 392 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 393 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 394 pl061_direction_output(&pl061->gc, offset, 395 pl061->csave_regs.gpio_data & 396 (BIT(offset))); 397 else 398 pl061_direction_input(&pl061->gc, offset); 399 } 400 401 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 402 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 403 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 404 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 405 406 return 0; 407 } 408 409 static DEFINE_SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume); 410 411 static const struct amba_id pl061_ids[] = { 412 { 413 .id = 0x00041061, 414 .mask = 0x000fffff, 415 }, 416 { 0, 0 }, 417 }; 418 MODULE_DEVICE_TABLE(amba, pl061_ids); 419 420 static struct amba_driver pl061_gpio_driver = { 421 .drv = { 422 .name = "pl061_gpio", 423 .pm = pm_sleep_ptr(&pl061_dev_pm_ops), 424 }, 425 .id_table = pl061_ids, 426 .probe = pl061_probe, 427 }; 428 module_amba_driver(pl061_gpio_driver); 429 430 MODULE_DESCRIPTION("Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)"); 431 MODULE_LICENSE("GPL v2"); 432