1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2008, 2009 Provigent Ltd. 4 * 5 * Author: Baruch Siach <baruch@tkos.co.il> 6 * 7 * Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061) 8 * 9 * Data sheet: ARM DDI 0190B, September 2000 10 */ 11 #include <linux/amba/bus.h> 12 #include <linux/bitops.h> 13 #include <linux/device.h> 14 #include <linux/errno.h> 15 #include <linux/gpio/driver.h> 16 #include <linux/init.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/irqchip/chained_irq.h> 22 #include <linux/module.h> 23 #include <linux/pinctrl/consumer.h> 24 #include <linux/pm.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 #include <linux/spinlock.h> 28 29 #define GPIODIR 0x400 30 #define GPIOIS 0x404 31 #define GPIOIBE 0x408 32 #define GPIOIEV 0x40C 33 #define GPIOIE 0x410 34 #define GPIORIS 0x414 35 #define GPIOMIS 0x418 36 #define GPIOIC 0x41C 37 38 #define PL061_GPIO_NR 8 39 40 struct pl061_context_save_regs { 41 u8 gpio_data; 42 u8 gpio_dir; 43 u8 gpio_is; 44 u8 gpio_ibe; 45 u8 gpio_iev; 46 u8 gpio_ie; 47 }; 48 49 struct pl061 { 50 raw_spinlock_t lock; 51 52 void __iomem *base; 53 struct gpio_chip gc; 54 int parent_irq; 55 56 struct pl061_context_save_regs csave_regs; 57 }; 58 59 static int pl061_get_direction(struct gpio_chip *gc, unsigned offset) 60 { 61 struct pl061 *pl061 = gpiochip_get_data(gc); 62 63 if (readb(pl061->base + GPIODIR) & BIT(offset)) 64 return GPIO_LINE_DIRECTION_OUT; 65 66 return GPIO_LINE_DIRECTION_IN; 67 } 68 69 static int pl061_direction_input(struct gpio_chip *gc, unsigned offset) 70 { 71 struct pl061 *pl061 = gpiochip_get_data(gc); 72 unsigned long flags; 73 unsigned char gpiodir; 74 75 raw_spin_lock_irqsave(&pl061->lock, flags); 76 gpiodir = readb(pl061->base + GPIODIR); 77 gpiodir &= ~(BIT(offset)); 78 writeb(gpiodir, pl061->base + GPIODIR); 79 raw_spin_unlock_irqrestore(&pl061->lock, flags); 80 81 return 0; 82 } 83 84 static int pl061_direction_output(struct gpio_chip *gc, unsigned offset, 85 int value) 86 { 87 struct pl061 *pl061 = gpiochip_get_data(gc); 88 unsigned long flags; 89 unsigned char gpiodir; 90 91 raw_spin_lock_irqsave(&pl061->lock, flags); 92 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 93 gpiodir = readb(pl061->base + GPIODIR); 94 gpiodir |= BIT(offset); 95 writeb(gpiodir, pl061->base + GPIODIR); 96 97 /* 98 * gpio value is set again, because pl061 doesn't allow to set value of 99 * a gpio pin before configuring it in OUT mode. 100 */ 101 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 102 raw_spin_unlock_irqrestore(&pl061->lock, flags); 103 104 return 0; 105 } 106 107 static int pl061_get_value(struct gpio_chip *gc, unsigned offset) 108 { 109 struct pl061 *pl061 = gpiochip_get_data(gc); 110 111 return !!readb(pl061->base + (BIT(offset + 2))); 112 } 113 114 static int pl061_set_value(struct gpio_chip *gc, unsigned int offset, int value) 115 { 116 struct pl061 *pl061 = gpiochip_get_data(gc); 117 118 writeb(!!value << offset, pl061->base + (BIT(offset + 2))); 119 120 return 0; 121 } 122 123 static int pl061_irq_type(struct irq_data *d, unsigned trigger) 124 { 125 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 126 struct pl061 *pl061 = gpiochip_get_data(gc); 127 int offset = irqd_to_hwirq(d); 128 unsigned long flags; 129 u8 gpiois, gpioibe, gpioiev; 130 u8 bit = BIT(offset); 131 132 if (offset < 0 || offset >= PL061_GPIO_NR) 133 return -EINVAL; 134 135 if ((trigger & IRQ_TYPE_LEVEL_MASK) && (trigger & IRQ_TYPE_EDGE_BOTH)) 136 { 137 dev_err(gc->parent, 138 "trying to configure line %d for both level and edge " 139 "detection, choose one!\n", 140 offset); 141 return -EINVAL; 142 } 143 144 145 raw_spin_lock_irqsave(&pl061->lock, flags); 146 147 gpioiev = readb(pl061->base + GPIOIEV); 148 gpiois = readb(pl061->base + GPIOIS); 149 gpioibe = readb(pl061->base + GPIOIBE); 150 151 if (trigger & IRQ_TYPE_LEVEL_MASK) { 152 bool polarity = trigger & IRQ_TYPE_LEVEL_HIGH; 153 154 /* Disable edge detection */ 155 gpioibe &= ~bit; 156 /* Enable level detection */ 157 gpiois |= bit; 158 /* Select polarity */ 159 if (polarity) 160 gpioiev |= bit; 161 else 162 gpioiev &= ~bit; 163 irq_set_handler_locked(d, handle_level_irq); 164 dev_dbg(gc->parent, "line %d: IRQ on %s level\n", 165 offset, 166 polarity ? "HIGH" : "LOW"); 167 } else if ((trigger & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { 168 /* Disable level detection */ 169 gpiois &= ~bit; 170 /* Select both edges, setting this makes GPIOEV be ignored */ 171 gpioibe |= bit; 172 irq_set_handler_locked(d, handle_edge_irq); 173 dev_dbg(gc->parent, "line %d: IRQ on both edges\n", offset); 174 } else if ((trigger & IRQ_TYPE_EDGE_RISING) || 175 (trigger & IRQ_TYPE_EDGE_FALLING)) { 176 bool rising = trigger & IRQ_TYPE_EDGE_RISING; 177 178 /* Disable level detection */ 179 gpiois &= ~bit; 180 /* Clear detection on both edges */ 181 gpioibe &= ~bit; 182 /* Select edge */ 183 if (rising) 184 gpioiev |= bit; 185 else 186 gpioiev &= ~bit; 187 irq_set_handler_locked(d, handle_edge_irq); 188 dev_dbg(gc->parent, "line %d: IRQ on %s edge\n", 189 offset, 190 rising ? "RISING" : "FALLING"); 191 } else { 192 /* No trigger: disable everything */ 193 gpiois &= ~bit; 194 gpioibe &= ~bit; 195 gpioiev &= ~bit; 196 irq_set_handler_locked(d, handle_bad_irq); 197 dev_warn(gc->parent, "no trigger selected for line %d\n", 198 offset); 199 } 200 201 writeb(gpiois, pl061->base + GPIOIS); 202 writeb(gpioibe, pl061->base + GPIOIBE); 203 writeb(gpioiev, pl061->base + GPIOIEV); 204 205 raw_spin_unlock_irqrestore(&pl061->lock, flags); 206 207 return 0; 208 } 209 210 static void pl061_irq_handler(struct irq_desc *desc) 211 { 212 unsigned long pending; 213 int offset; 214 struct gpio_chip *gc = irq_desc_get_handler_data(desc); 215 struct pl061 *pl061 = gpiochip_get_data(gc); 216 struct irq_chip *irqchip = irq_desc_get_chip(desc); 217 218 chained_irq_enter(irqchip, desc); 219 220 pending = readb(pl061->base + GPIOMIS); 221 if (pending) { 222 for_each_set_bit(offset, &pending, PL061_GPIO_NR) 223 generic_handle_domain_irq(gc->irq.domain, 224 offset); 225 } 226 227 chained_irq_exit(irqchip, desc); 228 } 229 230 static void pl061_irq_mask(struct irq_data *d) 231 { 232 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 233 struct pl061 *pl061 = gpiochip_get_data(gc); 234 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 235 u8 gpioie; 236 237 raw_spin_lock(&pl061->lock); 238 gpioie = readb(pl061->base + GPIOIE) & ~mask; 239 writeb(gpioie, pl061->base + GPIOIE); 240 raw_spin_unlock(&pl061->lock); 241 242 gpiochip_disable_irq(gc, d->hwirq); 243 } 244 245 static void pl061_irq_unmask(struct irq_data *d) 246 { 247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 248 struct pl061 *pl061 = gpiochip_get_data(gc); 249 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 250 u8 gpioie; 251 252 gpiochip_enable_irq(gc, d->hwirq); 253 254 raw_spin_lock(&pl061->lock); 255 gpioie = readb(pl061->base + GPIOIE) | mask; 256 writeb(gpioie, pl061->base + GPIOIE); 257 raw_spin_unlock(&pl061->lock); 258 } 259 260 /** 261 * pl061_irq_ack() - ACK an edge IRQ 262 * @d: IRQ data for this IRQ 263 * 264 * This gets called from the edge IRQ handler to ACK the edge IRQ 265 * in the GPIOIC (interrupt-clear) register. For level IRQs this is 266 * not needed: these go away when the level signal goes away. 267 */ 268 static void pl061_irq_ack(struct irq_data *d) 269 { 270 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 271 struct pl061 *pl061 = gpiochip_get_data(gc); 272 u8 mask = BIT(irqd_to_hwirq(d) % PL061_GPIO_NR); 273 274 raw_spin_lock(&pl061->lock); 275 writeb(mask, pl061->base + GPIOIC); 276 raw_spin_unlock(&pl061->lock); 277 } 278 279 static int pl061_irq_set_wake(struct irq_data *d, unsigned int state) 280 { 281 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 282 struct pl061 *pl061 = gpiochip_get_data(gc); 283 284 return irq_set_irq_wake(pl061->parent_irq, state); 285 } 286 287 static void pl061_irq_print_chip(struct irq_data *data, struct seq_file *p) 288 { 289 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 290 291 seq_puts(p, dev_name(gc->parent)); 292 } 293 294 static const struct irq_chip pl061_irq_chip = { 295 .irq_ack = pl061_irq_ack, 296 .irq_mask = pl061_irq_mask, 297 .irq_unmask = pl061_irq_unmask, 298 .irq_set_type = pl061_irq_type, 299 .irq_set_wake = pl061_irq_set_wake, 300 .irq_print_chip = pl061_irq_print_chip, 301 .flags = IRQCHIP_IMMUTABLE, 302 GPIOCHIP_IRQ_RESOURCE_HELPERS, 303 }; 304 305 static int pl061_probe(struct amba_device *adev, const struct amba_id *id) 306 { 307 struct device *dev = &adev->dev; 308 struct pl061 *pl061; 309 struct gpio_irq_chip *girq; 310 int ret, irq; 311 312 pl061 = devm_kzalloc(dev, sizeof(*pl061), GFP_KERNEL); 313 if (pl061 == NULL) 314 return -ENOMEM; 315 316 pl061->base = devm_ioremap_resource(dev, &adev->res); 317 if (IS_ERR(pl061->base)) 318 return PTR_ERR(pl061->base); 319 320 raw_spin_lock_init(&pl061->lock); 321 pl061->gc.request = gpiochip_generic_request; 322 pl061->gc.free = gpiochip_generic_free; 323 pl061->gc.base = -1; 324 pl061->gc.get_direction = pl061_get_direction; 325 pl061->gc.direction_input = pl061_direction_input; 326 pl061->gc.direction_output = pl061_direction_output; 327 pl061->gc.get = pl061_get_value; 328 pl061->gc.set = pl061_set_value; 329 pl061->gc.ngpio = PL061_GPIO_NR; 330 pl061->gc.label = dev_name(dev); 331 pl061->gc.parent = dev; 332 pl061->gc.owner = THIS_MODULE; 333 334 /* 335 * irq_chip support 336 */ 337 writeb(0, pl061->base + GPIOIE); /* disable irqs */ 338 irq = adev->irq[0]; 339 if (!irq) 340 dev_warn(&adev->dev, "IRQ support disabled\n"); 341 pl061->parent_irq = irq; 342 343 girq = &pl061->gc.irq; 344 gpio_irq_chip_set_chip(girq, &pl061_irq_chip); 345 girq->parent_handler = pl061_irq_handler; 346 girq->num_parents = 1; 347 girq->parents = devm_kcalloc(dev, 1, sizeof(*girq->parents), 348 GFP_KERNEL); 349 if (!girq->parents) 350 return -ENOMEM; 351 girq->parents[0] = irq; 352 girq->default_type = IRQ_TYPE_NONE; 353 girq->handler = handle_bad_irq; 354 355 ret = devm_gpiochip_add_data(dev, &pl061->gc, pl061); 356 if (ret) 357 return ret; 358 359 amba_set_drvdata(adev, pl061); 360 dev_info(dev, "PL061 GPIO chip registered\n"); 361 362 return 0; 363 } 364 365 static int pl061_suspend(struct device *dev) 366 { 367 struct pl061 *pl061 = dev_get_drvdata(dev); 368 int offset; 369 370 pl061->csave_regs.gpio_data = 0; 371 pl061->csave_regs.gpio_dir = readb(pl061->base + GPIODIR); 372 pl061->csave_regs.gpio_is = readb(pl061->base + GPIOIS); 373 pl061->csave_regs.gpio_ibe = readb(pl061->base + GPIOIBE); 374 pl061->csave_regs.gpio_iev = readb(pl061->base + GPIOIEV); 375 pl061->csave_regs.gpio_ie = readb(pl061->base + GPIOIE); 376 377 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 378 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 379 pl061->csave_regs.gpio_data |= 380 pl061_get_value(&pl061->gc, offset) << offset; 381 } 382 383 return 0; 384 } 385 386 static int pl061_resume(struct device *dev) 387 { 388 struct pl061 *pl061 = dev_get_drvdata(dev); 389 int offset; 390 391 for (offset = 0; offset < PL061_GPIO_NR; offset++) { 392 if (pl061->csave_regs.gpio_dir & (BIT(offset))) 393 pl061_direction_output(&pl061->gc, offset, 394 pl061->csave_regs.gpio_data & 395 (BIT(offset))); 396 else 397 pl061_direction_input(&pl061->gc, offset); 398 } 399 400 writeb(pl061->csave_regs.gpio_is, pl061->base + GPIOIS); 401 writeb(pl061->csave_regs.gpio_ibe, pl061->base + GPIOIBE); 402 writeb(pl061->csave_regs.gpio_iev, pl061->base + GPIOIEV); 403 writeb(pl061->csave_regs.gpio_ie, pl061->base + GPIOIE); 404 405 return 0; 406 } 407 408 static DEFINE_SIMPLE_DEV_PM_OPS(pl061_dev_pm_ops, pl061_suspend, pl061_resume); 409 410 static const struct amba_id pl061_ids[] = { 411 { 412 .id = 0x00041061, 413 .mask = 0x000fffff, 414 }, 415 { 0, 0 }, 416 }; 417 MODULE_DEVICE_TABLE(amba, pl061_ids); 418 419 static struct amba_driver pl061_gpio_driver = { 420 .drv = { 421 .name = "pl061_gpio", 422 .pm = pm_sleep_ptr(&pl061_dev_pm_ops), 423 }, 424 .id_table = pl061_ids, 425 .probe = pl061_probe, 426 }; 427 module_amba_driver(pl061_gpio_driver); 428 429 MODULE_DESCRIPTION("Driver for the ARM PrimeCell(tm) General Purpose Input/Output (PL061)"); 430 MODULE_LICENSE("GPL v2"); 431