1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2011 LAPIS Semiconductor Co., Ltd. 4 */ 5 #include <linux/bits.h> 6 #include <linux/gpio/driver.h> 7 #include <linux/interrupt.h> 8 #include <linux/irq.h> 9 #include <linux/kernel.h> 10 #include <linux/module.h> 11 #include <linux/pci.h> 12 #include <linux/slab.h> 13 14 #define PCH_EDGE_FALLING 0 15 #define PCH_EDGE_RISING 1 16 #define PCH_LEVEL_L 2 17 #define PCH_LEVEL_H 3 18 #define PCH_EDGE_BOTH 4 19 #define PCH_IM_MASK GENMASK(2, 0) 20 21 #define PCH_IRQ_BASE 24 22 23 struct pch_regs { 24 u32 ien; 25 u32 istatus; 26 u32 idisp; 27 u32 iclr; 28 u32 imask; 29 u32 imaskclr; 30 u32 po; 31 u32 pi; 32 u32 pm; 33 u32 im0; 34 u32 im1; 35 u32 reserved[3]; 36 u32 gpio_use_sel; 37 u32 reset; 38 }; 39 40 #define PCI_DEVICE_ID_INTEL_EG20T_PCH 0x8803 41 #define PCI_DEVICE_ID_ROHM_ML7223m_IOH 0x8014 42 #define PCI_DEVICE_ID_ROHM_ML7223n_IOH 0x8043 43 #define PCI_DEVICE_ID_ROHM_EG20T_PCH 0x8803 44 45 enum pch_type_t { 46 INTEL_EG20T_PCH, 47 OKISEMI_ML7223m_IOH, /* LAPIS Semiconductor ML7223 IOH PCIe Bus-m */ 48 OKISEMI_ML7223n_IOH /* LAPIS Semiconductor ML7223 IOH PCIe Bus-n */ 49 }; 50 51 /* Specifies number of GPIO PINS */ 52 static int gpio_pins[] = { 53 [INTEL_EG20T_PCH] = 12, 54 [OKISEMI_ML7223m_IOH] = 8, 55 [OKISEMI_ML7223n_IOH] = 8, 56 }; 57 58 /** 59 * struct pch_gpio_reg_data - The register store data. 60 * @ien_reg: To store contents of IEN register. 61 * @imask_reg: To store contents of IMASK register. 62 * @po_reg: To store contents of PO register. 63 * @pm_reg: To store contents of PM register. 64 * @im0_reg: To store contents of IM0 register. 65 * @im1_reg: To store contents of IM1 register. 66 * @gpio_use_sel_reg : To store contents of GPIO_USE_SEL register. 67 * (Only ML7223 Bus-n) 68 */ 69 struct pch_gpio_reg_data { 70 u32 ien_reg; 71 u32 imask_reg; 72 u32 po_reg; 73 u32 pm_reg; 74 u32 im0_reg; 75 u32 im1_reg; 76 u32 gpio_use_sel_reg; 77 }; 78 79 /** 80 * struct pch_gpio - GPIO private data structure. 81 * @base: PCI base address of Memory mapped I/O register. 82 * @reg: Memory mapped PCH GPIO register list. 83 * @dev: Pointer to device structure. 84 * @gpio: Data for GPIO infrastructure. 85 * @pch_gpio_reg: Memory mapped Register data is saved here 86 * when suspend. 87 * @irq_base: Save base of IRQ number for interrupt 88 * @ioh: IOH ID 89 * @spinlock: Used for register access protection 90 */ 91 struct pch_gpio { 92 void __iomem *base; 93 struct pch_regs __iomem *reg; 94 struct device *dev; 95 struct gpio_chip gpio; 96 struct pch_gpio_reg_data pch_gpio_reg; 97 int irq_base; 98 enum pch_type_t ioh; 99 spinlock_t spinlock; 100 }; 101 102 static int pch_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) 103 { 104 u32 reg_val; 105 struct pch_gpio *chip = gpiochip_get_data(gpio); 106 unsigned long flags; 107 108 spin_lock_irqsave(&chip->spinlock, flags); 109 reg_val = ioread32(&chip->reg->po); 110 if (val) 111 reg_val |= BIT(nr); 112 else 113 reg_val &= ~BIT(nr); 114 115 iowrite32(reg_val, &chip->reg->po); 116 spin_unlock_irqrestore(&chip->spinlock, flags); 117 118 return 0; 119 } 120 121 static int pch_gpio_get(struct gpio_chip *gpio, unsigned int nr) 122 { 123 struct pch_gpio *chip = gpiochip_get_data(gpio); 124 125 return !!(ioread32(&chip->reg->pi) & BIT(nr)); 126 } 127 128 static int pch_gpio_direction_output(struct gpio_chip *gpio, unsigned int nr, 129 int val) 130 { 131 struct pch_gpio *chip = gpiochip_get_data(gpio); 132 u32 pm; 133 u32 reg_val; 134 unsigned long flags; 135 136 spin_lock_irqsave(&chip->spinlock, flags); 137 138 reg_val = ioread32(&chip->reg->po); 139 if (val) 140 reg_val |= BIT(nr); 141 else 142 reg_val &= ~BIT(nr); 143 iowrite32(reg_val, &chip->reg->po); 144 145 pm = ioread32(&chip->reg->pm); 146 pm &= BIT(gpio_pins[chip->ioh]) - 1; 147 pm |= BIT(nr); 148 iowrite32(pm, &chip->reg->pm); 149 150 spin_unlock_irqrestore(&chip->spinlock, flags); 151 152 return 0; 153 } 154 155 static int pch_gpio_direction_input(struct gpio_chip *gpio, unsigned int nr) 156 { 157 struct pch_gpio *chip = gpiochip_get_data(gpio); 158 u32 pm; 159 unsigned long flags; 160 161 spin_lock_irqsave(&chip->spinlock, flags); 162 pm = ioread32(&chip->reg->pm); 163 pm &= BIT(gpio_pins[chip->ioh]) - 1; 164 pm &= ~BIT(nr); 165 iowrite32(pm, &chip->reg->pm); 166 spin_unlock_irqrestore(&chip->spinlock, flags); 167 168 return 0; 169 } 170 171 /* 172 * Save register configuration and disable interrupts. 173 */ 174 static void __maybe_unused pch_gpio_save_reg_conf(struct pch_gpio *chip) 175 { 176 chip->pch_gpio_reg.ien_reg = ioread32(&chip->reg->ien); 177 chip->pch_gpio_reg.imask_reg = ioread32(&chip->reg->imask); 178 chip->pch_gpio_reg.po_reg = ioread32(&chip->reg->po); 179 chip->pch_gpio_reg.pm_reg = ioread32(&chip->reg->pm); 180 chip->pch_gpio_reg.im0_reg = ioread32(&chip->reg->im0); 181 if (chip->ioh == INTEL_EG20T_PCH) 182 chip->pch_gpio_reg.im1_reg = ioread32(&chip->reg->im1); 183 if (chip->ioh == OKISEMI_ML7223n_IOH) 184 chip->pch_gpio_reg.gpio_use_sel_reg = ioread32(&chip->reg->gpio_use_sel); 185 } 186 187 /* 188 * This function restores the register configuration of the GPIO device. 189 */ 190 static void __maybe_unused pch_gpio_restore_reg_conf(struct pch_gpio *chip) 191 { 192 iowrite32(chip->pch_gpio_reg.ien_reg, &chip->reg->ien); 193 iowrite32(chip->pch_gpio_reg.imask_reg, &chip->reg->imask); 194 /* to store contents of PO register */ 195 iowrite32(chip->pch_gpio_reg.po_reg, &chip->reg->po); 196 /* to store contents of PM register */ 197 iowrite32(chip->pch_gpio_reg.pm_reg, &chip->reg->pm); 198 iowrite32(chip->pch_gpio_reg.im0_reg, &chip->reg->im0); 199 if (chip->ioh == INTEL_EG20T_PCH) 200 iowrite32(chip->pch_gpio_reg.im1_reg, &chip->reg->im1); 201 if (chip->ioh == OKISEMI_ML7223n_IOH) 202 iowrite32(chip->pch_gpio_reg.gpio_use_sel_reg, &chip->reg->gpio_use_sel); 203 } 204 205 static int pch_gpio_to_irq(struct gpio_chip *gpio, unsigned int offset) 206 { 207 struct pch_gpio *chip = gpiochip_get_data(gpio); 208 209 return chip->irq_base + offset; 210 } 211 212 static void pch_gpio_setup(struct pch_gpio *chip) 213 { 214 struct gpio_chip *gpio = &chip->gpio; 215 216 gpio->label = dev_name(chip->dev); 217 gpio->parent = chip->dev; 218 gpio->owner = THIS_MODULE; 219 gpio->direction_input = pch_gpio_direction_input; 220 gpio->get = pch_gpio_get; 221 gpio->direction_output = pch_gpio_direction_output; 222 gpio->set = pch_gpio_set; 223 gpio->base = -1; 224 gpio->ngpio = gpio_pins[chip->ioh]; 225 gpio->can_sleep = false; 226 gpio->to_irq = pch_gpio_to_irq; 227 } 228 229 static int pch_irq_type(struct irq_data *d, unsigned int type) 230 { 231 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 232 struct pch_gpio *chip = gc->private; 233 u32 im, im_pos, val; 234 u32 __iomem *im_reg; 235 unsigned long flags; 236 int ch, irq = d->irq; 237 238 ch = irq - chip->irq_base; 239 if (irq < chip->irq_base + 8) { 240 im_reg = &chip->reg->im0; 241 im_pos = ch - 0; 242 } else { 243 im_reg = &chip->reg->im1; 244 im_pos = ch - 8; 245 } 246 dev_dbg(chip->dev, "irq=%d type=%d ch=%d pos=%d\n", irq, type, ch, im_pos); 247 248 switch (type) { 249 case IRQ_TYPE_EDGE_RISING: 250 val = PCH_EDGE_RISING; 251 break; 252 case IRQ_TYPE_EDGE_FALLING: 253 val = PCH_EDGE_FALLING; 254 break; 255 case IRQ_TYPE_EDGE_BOTH: 256 val = PCH_EDGE_BOTH; 257 break; 258 case IRQ_TYPE_LEVEL_HIGH: 259 val = PCH_LEVEL_H; 260 break; 261 case IRQ_TYPE_LEVEL_LOW: 262 val = PCH_LEVEL_L; 263 break; 264 default: 265 return 0; 266 } 267 268 spin_lock_irqsave(&chip->spinlock, flags); 269 270 /* Set interrupt mode */ 271 im = ioread32(im_reg) & ~(PCH_IM_MASK << (im_pos * 4)); 272 iowrite32(im | (val << (im_pos * 4)), im_reg); 273 274 /* And the handler */ 275 if (type & IRQ_TYPE_LEVEL_MASK) 276 irq_set_handler_locked(d, handle_level_irq); 277 else if (type & IRQ_TYPE_EDGE_BOTH) 278 irq_set_handler_locked(d, handle_edge_irq); 279 280 spin_unlock_irqrestore(&chip->spinlock, flags); 281 return 0; 282 } 283 284 static void pch_irq_unmask(struct irq_data *d) 285 { 286 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 287 struct pch_gpio *chip = gc->private; 288 289 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imaskclr); 290 } 291 292 static void pch_irq_mask(struct irq_data *d) 293 { 294 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 295 struct pch_gpio *chip = gc->private; 296 297 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->imask); 298 } 299 300 static void pch_irq_ack(struct irq_data *d) 301 { 302 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 303 struct pch_gpio *chip = gc->private; 304 305 iowrite32(BIT(d->irq - chip->irq_base), &chip->reg->iclr); 306 } 307 308 static irqreturn_t pch_gpio_handler(int irq, void *dev_id) 309 { 310 struct pch_gpio *chip = dev_id; 311 unsigned long reg_val = ioread32(&chip->reg->istatus); 312 int i; 313 314 dev_vdbg(chip->dev, "irq=%d status=0x%lx\n", irq, reg_val); 315 316 reg_val &= BIT(gpio_pins[chip->ioh]) - 1; 317 318 for_each_set_bit(i, ®_val, gpio_pins[chip->ioh]) 319 generic_handle_irq(chip->irq_base + i); 320 321 return IRQ_RETVAL(reg_val); 322 } 323 324 static int pch_gpio_alloc_generic_chip(struct pch_gpio *chip, 325 unsigned int irq_start, 326 unsigned int num) 327 { 328 struct irq_chip_generic *gc; 329 struct irq_chip_type *ct; 330 int rv; 331 332 gc = devm_irq_alloc_generic_chip(chip->dev, "pch_gpio", 1, irq_start, 333 chip->base, handle_simple_irq); 334 if (!gc) 335 return -ENOMEM; 336 337 gc->private = chip; 338 ct = gc->chip_types; 339 340 ct->chip.irq_ack = pch_irq_ack; 341 ct->chip.irq_mask = pch_irq_mask; 342 ct->chip.irq_unmask = pch_irq_unmask; 343 ct->chip.irq_set_type = pch_irq_type; 344 345 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), 346 IRQ_GC_INIT_MASK_CACHE, 347 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 348 349 return rv; 350 } 351 352 static int pch_gpio_probe(struct pci_dev *pdev, 353 const struct pci_device_id *id) 354 { 355 struct device *dev = &pdev->dev; 356 s32 ret; 357 struct pch_gpio *chip; 358 int irq_base; 359 360 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 361 if (chip == NULL) 362 return -ENOMEM; 363 364 chip->dev = dev; 365 ret = pcim_enable_device(pdev); 366 if (ret) 367 return dev_err_probe(dev, ret, "Failed to enable PCI device\n"); 368 369 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME); 370 if (ret) 371 return dev_err_probe(dev, ret, "Failed to request and map PCI regions\n"); 372 373 chip->base = pcim_iomap_table(pdev)[1]; 374 chip->ioh = id->driver_data; 375 chip->reg = chip->base; 376 pci_set_drvdata(pdev, chip); 377 spin_lock_init(&chip->spinlock); 378 pch_gpio_setup(chip); 379 380 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip); 381 if (ret) 382 return dev_err_probe(dev, ret, "Failed to register GPIO\n"); 383 384 irq_base = devm_irq_alloc_descs(dev, -1, 0, 385 gpio_pins[chip->ioh], NUMA_NO_NODE); 386 if (irq_base < 0) { 387 dev_warn(dev, "PCH gpio: Failed to get IRQ base num\n"); 388 chip->irq_base = -1; 389 return 0; 390 } 391 chip->irq_base = irq_base; 392 393 /* Mask all interrupts, but enable them */ 394 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->imask); 395 iowrite32(BIT(gpio_pins[chip->ioh]) - 1, &chip->reg->ien); 396 397 ret = devm_request_irq(dev, pdev->irq, pch_gpio_handler, 398 IRQF_SHARED, KBUILD_MODNAME, chip); 399 if (ret) 400 return dev_err_probe(dev, ret, "Failed to request IRQ\n"); 401 402 return pch_gpio_alloc_generic_chip(chip, irq_base, gpio_pins[chip->ioh]); 403 } 404 405 static int __maybe_unused pch_gpio_suspend(struct device *dev) 406 { 407 struct pch_gpio *chip = dev_get_drvdata(dev); 408 unsigned long flags; 409 410 spin_lock_irqsave(&chip->spinlock, flags); 411 pch_gpio_save_reg_conf(chip); 412 spin_unlock_irqrestore(&chip->spinlock, flags); 413 414 return 0; 415 } 416 417 static int __maybe_unused pch_gpio_resume(struct device *dev) 418 { 419 struct pch_gpio *chip = dev_get_drvdata(dev); 420 unsigned long flags; 421 422 spin_lock_irqsave(&chip->spinlock, flags); 423 iowrite32(0x01, &chip->reg->reset); 424 iowrite32(0x00, &chip->reg->reset); 425 pch_gpio_restore_reg_conf(chip); 426 spin_unlock_irqrestore(&chip->spinlock, flags); 427 428 return 0; 429 } 430 431 static SIMPLE_DEV_PM_OPS(pch_gpio_pm_ops, pch_gpio_suspend, pch_gpio_resume); 432 433 static const struct pci_device_id pch_gpio_pcidev_id[] = { 434 { PCI_DEVICE_DATA(INTEL, EG20T_PCH, INTEL_EG20T_PCH) }, 435 { PCI_DEVICE_DATA(ROHM, ML7223m_IOH, OKISEMI_ML7223m_IOH) }, 436 { PCI_DEVICE_DATA(ROHM, ML7223n_IOH, OKISEMI_ML7223n_IOH) }, 437 { PCI_DEVICE_DATA(ROHM, EG20T_PCH, INTEL_EG20T_PCH) }, 438 { } 439 }; 440 MODULE_DEVICE_TABLE(pci, pch_gpio_pcidev_id); 441 442 static struct pci_driver pch_gpio_driver = { 443 .name = "pch_gpio", 444 .id_table = pch_gpio_pcidev_id, 445 .probe = pch_gpio_probe, 446 .driver = { 447 .pm = &pch_gpio_pm_ops, 448 }, 449 }; 450 451 module_pci_driver(pch_gpio_driver); 452 453 MODULE_DESCRIPTION("PCH GPIO PCI Driver"); 454 MODULE_LICENSE("GPL v2"); 455