1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders 4 * 5 * Copyright (C) 2007 David Brownell 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/property.h> 19 #include <linux/slab.h> 20 #include <linux/spinlock.h> 21 22 static const struct i2c_device_id pcf857x_id[] = { 23 { "pcf8574", 8 }, 24 { "pcf8574a", 8 }, 25 { "pca8574", 8 }, 26 { "pca9670", 8 }, 27 { "pca9672", 8 }, 28 { "pca9674", 8 }, 29 { "pcf8575", 16 }, 30 { "pca8575", 16 }, 31 { "pca9671", 16 }, 32 { "pca9673", 16 }, 33 { "pca9675", 16 }, 34 { "max7328", 8 }, 35 { "max7329", 8 }, 36 { } 37 }; 38 MODULE_DEVICE_TABLE(i2c, pcf857x_id); 39 40 static const struct of_device_id pcf857x_of_table[] = { 41 { .compatible = "nxp,pcf8574", (void *)8 }, 42 { .compatible = "nxp,pcf8574a", (void *)8 }, 43 { .compatible = "nxp,pca8574", (void *)8 }, 44 { .compatible = "nxp,pca9670", (void *)8 }, 45 { .compatible = "nxp,pca9672", (void *)8 }, 46 { .compatible = "nxp,pca9674", (void *)8 }, 47 { .compatible = "nxp,pcf8575", (void *)16 }, 48 { .compatible = "nxp,pca8575", (void *)16 }, 49 { .compatible = "nxp,pca9671", (void *)16 }, 50 { .compatible = "nxp,pca9673", (void *)16 }, 51 { .compatible = "nxp,pca9675", (void *)16 }, 52 { .compatible = "maxim,max7328", (void *)8 }, 53 { .compatible = "maxim,max7329", (void *)8 }, 54 { } 55 }; 56 MODULE_DEVICE_TABLE(of, pcf857x_of_table); 57 58 /* 59 * The pcf857x, pca857x, and pca967x chips only expose one read and one 60 * write register. Writing a "one" bit (to match the reset state) lets 61 * that pin be used as an input; it's not an open-drain model, but acts 62 * a bit like one. This is described as "quasi-bidirectional"; read the 63 * chip documentation for details. 64 * 65 * Many other I2C GPIO expander chips (like the pca953x models) have 66 * more complex register models and more conventional circuitry using 67 * push/pull drivers. They often use the same 0x20..0x27 addresses as 68 * pcf857x parts, making the "legacy" I2C driver model problematic. 69 */ 70 struct pcf857x { 71 struct gpio_chip chip; 72 struct i2c_client *client; 73 struct mutex lock; /* protect 'out' */ 74 unsigned int out; /* software latch */ 75 unsigned int status; /* current status */ 76 unsigned int irq_enabled; /* enabled irqs */ 77 78 int (*write)(struct i2c_client *client, unsigned int data); 79 int (*read)(struct i2c_client *client); 80 }; 81 82 /*-------------------------------------------------------------------------*/ 83 84 /* Talk to 8-bit I/O expander */ 85 86 static int i2c_write_le8(struct i2c_client *client, unsigned int data) 87 { 88 return i2c_smbus_write_byte(client, data); 89 } 90 91 static int i2c_read_le8(struct i2c_client *client) 92 { 93 return i2c_smbus_read_byte(client); 94 } 95 96 /* Talk to 16-bit I/O expander */ 97 98 static int i2c_write_le16(struct i2c_client *client, unsigned int word) 99 { 100 u8 buf[2] = { word & 0xff, word >> 8, }; 101 int status; 102 103 status = i2c_master_send(client, buf, 2); 104 return (status < 0) ? status : 0; 105 } 106 107 static int i2c_read_le16(struct i2c_client *client) 108 { 109 u8 buf[2]; 110 int status; 111 112 status = i2c_master_recv(client, buf, 2); 113 if (status < 0) 114 return status; 115 return (buf[1] << 8) | buf[0]; 116 } 117 118 /*-------------------------------------------------------------------------*/ 119 120 static int pcf857x_input(struct gpio_chip *chip, unsigned int offset) 121 { 122 struct pcf857x *gpio = gpiochip_get_data(chip); 123 int status; 124 125 mutex_lock(&gpio->lock); 126 gpio->out |= (1 << offset); 127 status = gpio->write(gpio->client, gpio->out); 128 mutex_unlock(&gpio->lock); 129 130 return status; 131 } 132 133 static int pcf857x_get(struct gpio_chip *chip, unsigned int offset) 134 { 135 struct pcf857x *gpio = gpiochip_get_data(chip); 136 int value; 137 138 value = gpio->read(gpio->client); 139 return (value < 0) ? value : !!(value & (1 << offset)); 140 } 141 142 static int pcf857x_get_multiple(struct gpio_chip *chip, unsigned long *mask, 143 unsigned long *bits) 144 { 145 struct pcf857x *gpio = gpiochip_get_data(chip); 146 int value = gpio->read(gpio->client); 147 148 if (value < 0) 149 return value; 150 151 *bits &= ~*mask; 152 *bits |= value & *mask; 153 154 return 0; 155 } 156 157 static int pcf857x_output(struct gpio_chip *chip, unsigned int offset, int value) 158 { 159 struct pcf857x *gpio = gpiochip_get_data(chip); 160 unsigned int bit = 1 << offset; 161 int status; 162 163 mutex_lock(&gpio->lock); 164 if (value) 165 gpio->out |= bit; 166 else 167 gpio->out &= ~bit; 168 status = gpio->write(gpio->client, gpio->out); 169 mutex_unlock(&gpio->lock); 170 171 return status; 172 } 173 174 static void pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value) 175 { 176 pcf857x_output(chip, offset, value); 177 } 178 179 static void pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask, 180 unsigned long *bits) 181 { 182 struct pcf857x *gpio = gpiochip_get_data(chip); 183 184 mutex_lock(&gpio->lock); 185 gpio->out &= ~*mask; 186 gpio->out |= *bits & *mask; 187 gpio->write(gpio->client, gpio->out); 188 mutex_unlock(&gpio->lock); 189 } 190 191 /*-------------------------------------------------------------------------*/ 192 193 static irqreturn_t pcf857x_irq(int irq, void *data) 194 { 195 struct pcf857x *gpio = data; 196 unsigned long change, i, status; 197 198 status = gpio->read(gpio->client); 199 200 /* 201 * call the interrupt handler iff gpio is used as 202 * interrupt source, just to avoid bad irqs 203 */ 204 mutex_lock(&gpio->lock); 205 change = (gpio->status ^ status) & gpio->irq_enabled; 206 gpio->status = status; 207 mutex_unlock(&gpio->lock); 208 209 for_each_set_bit(i, &change, gpio->chip.ngpio) 210 handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i)); 211 212 return IRQ_HANDLED; 213 } 214 215 /* 216 * NOP functions 217 */ 218 static void noop(struct irq_data *data) { } 219 220 static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on) 221 { 222 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 223 224 return irq_set_irq_wake(gpio->client->irq, on); 225 } 226 227 static void pcf857x_irq_enable(struct irq_data *data) 228 { 229 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 230 irq_hw_number_t hwirq = irqd_to_hwirq(data); 231 232 gpiochip_enable_irq(&gpio->chip, hwirq); 233 gpio->irq_enabled |= (1 << hwirq); 234 } 235 236 static void pcf857x_irq_disable(struct irq_data *data) 237 { 238 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 239 irq_hw_number_t hwirq = irqd_to_hwirq(data); 240 241 gpio->irq_enabled &= ~(1 << hwirq); 242 gpiochip_disable_irq(&gpio->chip, hwirq); 243 } 244 245 static void pcf857x_irq_bus_lock(struct irq_data *data) 246 { 247 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 248 249 mutex_lock(&gpio->lock); 250 } 251 252 static void pcf857x_irq_bus_sync_unlock(struct irq_data *data) 253 { 254 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 255 256 mutex_unlock(&gpio->lock); 257 } 258 259 static const struct irq_chip pcf857x_irq_chip = { 260 .name = "pcf857x", 261 .irq_enable = pcf857x_irq_enable, 262 .irq_disable = pcf857x_irq_disable, 263 .irq_ack = noop, 264 .irq_mask = noop, 265 .irq_unmask = noop, 266 .irq_set_wake = pcf857x_irq_set_wake, 267 .irq_bus_lock = pcf857x_irq_bus_lock, 268 .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock, 269 .flags = IRQCHIP_IMMUTABLE, 270 GPIOCHIP_IRQ_RESOURCE_HELPERS, 271 }; 272 273 /*-------------------------------------------------------------------------*/ 274 275 static int pcf857x_probe(struct i2c_client *client) 276 { 277 struct gpio_desc *reset_gpio; 278 struct pcf857x *gpio; 279 unsigned int n_latch = 0; 280 int status; 281 282 /* Allocate, initialize, and register this gpio_chip. */ 283 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); 284 if (!gpio) 285 return -ENOMEM; 286 287 mutex_init(&gpio->lock); 288 289 gpio->chip.base = -1; 290 gpio->chip.can_sleep = true; 291 gpio->chip.parent = &client->dev; 292 gpio->chip.owner = THIS_MODULE; 293 gpio->chip.get = pcf857x_get; 294 gpio->chip.get_multiple = pcf857x_get_multiple; 295 gpio->chip.set = pcf857x_set; 296 gpio->chip.set_multiple = pcf857x_set_multiple; 297 gpio->chip.direction_input = pcf857x_input; 298 gpio->chip.direction_output = pcf857x_output; 299 gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client); 300 301 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); 302 if (IS_ERR(reset_gpio)) 303 return dev_err_probe(&client->dev, PTR_ERR(reset_gpio), 304 "failed to get reset GPIO\n"); 305 306 if (reset_gpio) { 307 /* Reset already held with devm_gpiod_get_optional with GPIOD_OUT_HIGH */ 308 fsleep(4); /* tw(rst) > 4us */ 309 gpiod_set_value_cansleep(reset_gpio, 0); 310 fsleep(100); /* trst > 100uS */ 311 312 /* 313 * Performing a reset means "The PCA9670 registers and I2C-bus 314 * state machine will be held in their default state until the 315 * RESET input is once again HIGH". 316 * 317 * This is the same as writing 1 for all pins, which is the same 318 * as n_latch=0, the default value of the variable. 319 */ 320 } else { 321 device_property_read_u32(&client->dev, "lines-initial-states", 322 &n_latch); 323 } 324 325 /* NOTE: the OnSemi jlc1562b is also largely compatible with 326 * these parts, notably for output. It has a low-resolution 327 * DAC instead of pin change IRQs; and its inputs can be the 328 * result of comparators. 329 */ 330 331 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f; 332 * 9670, 9672, 9764, and 9764a use quite a variety. 333 * 334 * NOTE: we don't distinguish here between *4 and *4a parts. 335 */ 336 if (gpio->chip.ngpio == 8) { 337 gpio->write = i2c_write_le8; 338 gpio->read = i2c_read_le8; 339 340 if (!i2c_check_functionality(client->adapter, 341 I2C_FUNC_SMBUS_BYTE)) 342 status = -EIO; 343 344 /* fail if there's no chip present */ 345 else 346 status = i2c_smbus_read_byte(client); 347 348 /* '75/'75c addresses are 0x20..0x27, just like the '74; 349 * the '75c doesn't have a current source pulling high. 350 * 9671, 9673, and 9765 use quite a variety of addresses. 351 * 352 * NOTE: we don't distinguish here between '75 and '75c parts. 353 */ 354 } else if (gpio->chip.ngpio == 16) { 355 gpio->write = i2c_write_le16; 356 gpio->read = i2c_read_le16; 357 358 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 359 status = -EIO; 360 361 /* fail if there's no chip present */ 362 else 363 status = i2c_read_le16(client); 364 365 } else { 366 dev_dbg(&client->dev, "unsupported number of gpios\n"); 367 status = -EINVAL; 368 } 369 370 if (status < 0) 371 goto fail; 372 373 gpio->chip.label = client->name; 374 375 gpio->client = client; 376 i2c_set_clientdata(client, gpio); 377 378 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. 379 * We can't actually know whether a pin is configured (a) as output 380 * and driving the signal low, or (b) as input and reporting a low 381 * value ... without knowing the last value written since the chip 382 * came out of reset (if any). We can't read the latched output. 383 * 384 * In short, the only reliable solution for setting up pin direction 385 * is to do it explicitly. The setup() method can do that, but it 386 * may cause transient glitching since it can't know the last value 387 * written (some pins may need to be driven low). 388 * 389 * Using n_latch avoids that trouble. When left initialized to zero, 390 * our software copy of the "latch" then matches the chip's all-ones 391 * reset state. Otherwise it flags pins to be driven low. 392 */ 393 gpio->out = ~n_latch; 394 gpio->status = gpio->read(gpio->client); 395 396 /* Enable irqchip if we have an interrupt */ 397 if (client->irq) { 398 struct gpio_irq_chip *girq; 399 400 status = devm_request_threaded_irq(&client->dev, client->irq, 401 NULL, pcf857x_irq, IRQF_ONESHOT | 402 IRQF_TRIGGER_FALLING | IRQF_SHARED, 403 dev_name(&client->dev), gpio); 404 if (status) 405 goto fail; 406 407 girq = &gpio->chip.irq; 408 gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip); 409 /* This will let us handle the parent IRQ in the driver */ 410 girq->parent_handler = NULL; 411 girq->num_parents = 0; 412 girq->parents = NULL; 413 girq->default_type = IRQ_TYPE_NONE; 414 girq->handler = handle_level_irq; 415 girq->threaded = true; 416 } 417 418 status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio); 419 if (status < 0) 420 goto fail; 421 422 dev_info(&client->dev, "probed\n"); 423 424 return 0; 425 426 fail: 427 dev_dbg(&client->dev, "probe error %d for '%s'\n", status, 428 client->name); 429 430 return status; 431 } 432 433 static void pcf857x_shutdown(struct i2c_client *client) 434 { 435 struct pcf857x *gpio = i2c_get_clientdata(client); 436 437 /* Drive all the I/O lines high */ 438 gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1); 439 } 440 441 static struct i2c_driver pcf857x_driver = { 442 .driver = { 443 .name = "pcf857x", 444 .of_match_table = pcf857x_of_table, 445 }, 446 .probe = pcf857x_probe, 447 .shutdown = pcf857x_shutdown, 448 .id_table = pcf857x_id, 449 }; 450 451 static int __init pcf857x_init(void) 452 { 453 return i2c_add_driver(&pcf857x_driver); 454 } 455 /* register after i2c postcore initcall and before 456 * subsys initcalls that may rely on these GPIOs 457 */ 458 subsys_initcall(pcf857x_init); 459 460 static void __exit pcf857x_exit(void) 461 { 462 i2c_del_driver(&pcf857x_driver); 463 } 464 module_exit(pcf857x_exit); 465 466 MODULE_DESCRIPTION("Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders"); 467 MODULE_LICENSE("GPL"); 468 MODULE_AUTHOR("David Brownell"); 469