1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders 4 * 5 * Copyright (C) 2007 David Brownell 6 */ 7 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/i2c.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/property.h> 18 #include <linux/slab.h> 19 #include <linux/spinlock.h> 20 21 static const struct i2c_device_id pcf857x_id[] = { 22 { .name = "pcf8574", .driver_data = 8 }, 23 { .name = "pcf8574a", .driver_data = 8 }, 24 { .name = "pca8574", .driver_data = 8 }, 25 { .name = "pca9670", .driver_data = 8 }, 26 { .name = "pca9672", .driver_data = 8 }, 27 { .name = "pca9674", .driver_data = 8 }, 28 { .name = "pcf8575", .driver_data = 16 }, 29 { .name = "pca8575", .driver_data = 16 }, 30 { .name = "pca9671", .driver_data = 16 }, 31 { .name = "pca9673", .driver_data = 16 }, 32 { .name = "pca9675", .driver_data = 16 }, 33 { .name = "max7328", .driver_data = 8 }, 34 { .name = "max7329", .driver_data = 8 }, 35 { } 36 }; 37 MODULE_DEVICE_TABLE(i2c, pcf857x_id); 38 39 static const struct of_device_id pcf857x_of_table[] = { 40 { .compatible = "nxp,pcf8574", (void *)8 }, 41 { .compatible = "nxp,pcf8574a", (void *)8 }, 42 { .compatible = "nxp,pca8574", (void *)8 }, 43 { .compatible = "nxp,pca9670", (void *)8 }, 44 { .compatible = "nxp,pca9672", (void *)8 }, 45 { .compatible = "nxp,pca9674", (void *)8 }, 46 { .compatible = "nxp,pcf8575", (void *)16 }, 47 { .compatible = "nxp,pca8575", (void *)16 }, 48 { .compatible = "nxp,pca9671", (void *)16 }, 49 { .compatible = "nxp,pca9673", (void *)16 }, 50 { .compatible = "nxp,pca9675", (void *)16 }, 51 { .compatible = "maxim,max7328", (void *)8 }, 52 { .compatible = "maxim,max7329", (void *)8 }, 53 { } 54 }; 55 MODULE_DEVICE_TABLE(of, pcf857x_of_table); 56 57 /* 58 * The pcf857x, pca857x, and pca967x chips only expose one read and one 59 * write register. Writing a "one" bit (to match the reset state) lets 60 * that pin be used as an input; it's not an open-drain model, but acts 61 * a bit like one. This is described as "quasi-bidirectional"; read the 62 * chip documentation for details. 63 * 64 * Many other I2C GPIO expander chips (like the pca953x models) have 65 * more complex register models and more conventional circuitry using 66 * push/pull drivers. They often use the same 0x20..0x27 addresses as 67 * pcf857x parts, making the "legacy" I2C driver model problematic. 68 */ 69 struct pcf857x { 70 struct gpio_chip chip; 71 struct i2c_client *client; 72 struct mutex lock; /* protect 'out' */ 73 unsigned int out; /* software latch */ 74 unsigned int status; /* current status */ 75 unsigned int irq_enabled; /* enabled irqs */ 76 77 int (*write)(struct i2c_client *client, unsigned int data); 78 int (*read)(struct i2c_client *client); 79 }; 80 81 /*-------------------------------------------------------------------------*/ 82 83 /* Talk to 8-bit I/O expander */ 84 85 static int i2c_write_le8(struct i2c_client *client, unsigned int data) 86 { 87 return i2c_smbus_write_byte(client, data); 88 } 89 90 static int i2c_read_le8(struct i2c_client *client) 91 { 92 return i2c_smbus_read_byte(client); 93 } 94 95 /* Talk to 16-bit I/O expander */ 96 97 static int i2c_write_le16(struct i2c_client *client, unsigned int word) 98 { 99 u8 buf[2] = { word & 0xff, word >> 8, }; 100 int status; 101 102 status = i2c_master_send(client, buf, 2); 103 return (status < 0) ? status : 0; 104 } 105 106 static int i2c_read_le16(struct i2c_client *client) 107 { 108 u8 buf[2]; 109 int status; 110 111 status = i2c_master_recv(client, buf, 2); 112 if (status < 0) 113 return status; 114 return (buf[1] << 8) | buf[0]; 115 } 116 117 /*-------------------------------------------------------------------------*/ 118 119 static int pcf857x_input(struct gpio_chip *chip, unsigned int offset) 120 { 121 struct pcf857x *gpio = gpiochip_get_data(chip); 122 int status; 123 124 mutex_lock(&gpio->lock); 125 gpio->out |= (1 << offset); 126 status = gpio->write(gpio->client, gpio->out); 127 mutex_unlock(&gpio->lock); 128 129 return status; 130 } 131 132 static int pcf857x_get(struct gpio_chip *chip, unsigned int offset) 133 { 134 struct pcf857x *gpio = gpiochip_get_data(chip); 135 int value; 136 137 value = gpio->read(gpio->client); 138 return (value < 0) ? value : !!(value & (1 << offset)); 139 } 140 141 static int pcf857x_get_multiple(struct gpio_chip *chip, unsigned long *mask, 142 unsigned long *bits) 143 { 144 struct pcf857x *gpio = gpiochip_get_data(chip); 145 int value = gpio->read(gpio->client); 146 147 if (value < 0) 148 return value; 149 150 *bits &= ~*mask; 151 *bits |= value & *mask; 152 153 return 0; 154 } 155 156 static int pcf857x_output(struct gpio_chip *chip, unsigned int offset, int value) 157 { 158 struct pcf857x *gpio = gpiochip_get_data(chip); 159 unsigned int bit = 1 << offset; 160 int status; 161 162 mutex_lock(&gpio->lock); 163 if (value) 164 gpio->out |= bit; 165 else 166 gpio->out &= ~bit; 167 status = gpio->write(gpio->client, gpio->out); 168 mutex_unlock(&gpio->lock); 169 170 return status; 171 } 172 173 static int pcf857x_set(struct gpio_chip *chip, unsigned int offset, int value) 174 { 175 return pcf857x_output(chip, offset, value); 176 } 177 178 static int pcf857x_set_multiple(struct gpio_chip *chip, unsigned long *mask, 179 unsigned long *bits) 180 { 181 struct pcf857x *gpio = gpiochip_get_data(chip); 182 int status; 183 184 mutex_lock(&gpio->lock); 185 gpio->out &= ~*mask; 186 gpio->out |= *bits & *mask; 187 status = gpio->write(gpio->client, gpio->out); 188 mutex_unlock(&gpio->lock); 189 190 return status; 191 } 192 193 /*-------------------------------------------------------------------------*/ 194 195 static irqreturn_t pcf857x_irq(int irq, void *data) 196 { 197 struct pcf857x *gpio = data; 198 unsigned long change, i, status; 199 200 status = gpio->read(gpio->client); 201 202 /* 203 * call the interrupt handler iff gpio is used as 204 * interrupt source, just to avoid bad irqs 205 */ 206 mutex_lock(&gpio->lock); 207 change = (gpio->status ^ status) & gpio->irq_enabled; 208 gpio->status = status; 209 mutex_unlock(&gpio->lock); 210 211 for_each_set_bit(i, &change, gpio->chip.ngpio) 212 handle_nested_irq(irq_find_mapping(gpio->chip.irq.domain, i)); 213 214 return IRQ_HANDLED; 215 } 216 217 /* 218 * NOP functions 219 */ 220 static void noop(struct irq_data *data) { } 221 222 static int pcf857x_irq_set_wake(struct irq_data *data, unsigned int on) 223 { 224 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 225 226 return irq_set_irq_wake(gpio->client->irq, on); 227 } 228 229 static void pcf857x_irq_enable(struct irq_data *data) 230 { 231 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 232 irq_hw_number_t hwirq = irqd_to_hwirq(data); 233 234 gpiochip_enable_irq(&gpio->chip, hwirq); 235 gpio->irq_enabled |= (1 << hwirq); 236 } 237 238 static void pcf857x_irq_disable(struct irq_data *data) 239 { 240 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 241 irq_hw_number_t hwirq = irqd_to_hwirq(data); 242 243 gpio->irq_enabled &= ~(1 << hwirq); 244 gpiochip_disable_irq(&gpio->chip, hwirq); 245 } 246 247 static void pcf857x_irq_bus_lock(struct irq_data *data) 248 { 249 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 250 251 mutex_lock(&gpio->lock); 252 } 253 254 static void pcf857x_irq_bus_sync_unlock(struct irq_data *data) 255 { 256 struct pcf857x *gpio = irq_data_get_irq_chip_data(data); 257 258 mutex_unlock(&gpio->lock); 259 } 260 261 static const struct irq_chip pcf857x_irq_chip = { 262 .name = "pcf857x", 263 .irq_enable = pcf857x_irq_enable, 264 .irq_disable = pcf857x_irq_disable, 265 .irq_ack = noop, 266 .irq_mask = noop, 267 .irq_unmask = noop, 268 .irq_set_wake = pcf857x_irq_set_wake, 269 .irq_bus_lock = pcf857x_irq_bus_lock, 270 .irq_bus_sync_unlock = pcf857x_irq_bus_sync_unlock, 271 .flags = IRQCHIP_IMMUTABLE, 272 GPIOCHIP_IRQ_RESOURCE_HELPERS, 273 }; 274 275 /*-------------------------------------------------------------------------*/ 276 277 static int pcf857x_probe(struct i2c_client *client) 278 { 279 struct gpio_desc *reset_gpio; 280 struct pcf857x *gpio; 281 unsigned int n_latch = 0; 282 int status; 283 284 /* Allocate, initialize, and register this gpio_chip. */ 285 gpio = devm_kzalloc(&client->dev, sizeof(*gpio), GFP_KERNEL); 286 if (!gpio) 287 return -ENOMEM; 288 289 mutex_init(&gpio->lock); 290 291 gpio->chip.base = -1; 292 gpio->chip.can_sleep = true; 293 gpio->chip.parent = &client->dev; 294 gpio->chip.owner = THIS_MODULE; 295 gpio->chip.get = pcf857x_get; 296 gpio->chip.get_multiple = pcf857x_get_multiple; 297 gpio->chip.set = pcf857x_set; 298 gpio->chip.set_multiple = pcf857x_set_multiple; 299 gpio->chip.direction_input = pcf857x_input; 300 gpio->chip.direction_output = pcf857x_output; 301 gpio->chip.ngpio = (uintptr_t)i2c_get_match_data(client); 302 303 reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", GPIOD_OUT_HIGH); 304 if (IS_ERR(reset_gpio)) 305 return dev_err_probe(&client->dev, PTR_ERR(reset_gpio), 306 "failed to get reset GPIO\n"); 307 308 if (reset_gpio) { 309 /* Reset already held with devm_gpiod_get_optional with GPIOD_OUT_HIGH */ 310 fsleep(4); /* tw(rst) > 4us */ 311 gpiod_set_value_cansleep(reset_gpio, 0); 312 fsleep(100); /* trst > 100uS */ 313 314 /* 315 * Performing a reset means "The PCA9670 registers and I2C-bus 316 * state machine will be held in their default state until the 317 * RESET input is once again HIGH". 318 * 319 * This is the same as writing 1 for all pins, which is the same 320 * as n_latch=0, the default value of the variable. 321 */ 322 } else { 323 device_property_read_u32(&client->dev, "lines-initial-states", 324 &n_latch); 325 } 326 327 /* NOTE: the OnSemi jlc1562b is also largely compatible with 328 * these parts, notably for output. It has a low-resolution 329 * DAC instead of pin change IRQs; and its inputs can be the 330 * result of comparators. 331 */ 332 333 /* 8574 addresses are 0x20..0x27; 8574a uses 0x38..0x3f; 334 * 9670, 9672, 9764, and 9764a use quite a variety. 335 * 336 * NOTE: we don't distinguish here between *4 and *4a parts. 337 */ 338 if (gpio->chip.ngpio == 8) { 339 gpio->write = i2c_write_le8; 340 gpio->read = i2c_read_le8; 341 342 if (!i2c_check_functionality(client->adapter, 343 I2C_FUNC_SMBUS_BYTE)) 344 status = -EIO; 345 346 /* fail if there's no chip present */ 347 else 348 status = i2c_smbus_read_byte(client); 349 350 /* '75/'75c addresses are 0x20..0x27, just like the '74; 351 * the '75c doesn't have a current source pulling high. 352 * 9671, 9673, and 9765 use quite a variety of addresses. 353 * 354 * NOTE: we don't distinguish here between '75 and '75c parts. 355 */ 356 } else if (gpio->chip.ngpio == 16) { 357 gpio->write = i2c_write_le16; 358 gpio->read = i2c_read_le16; 359 360 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) 361 status = -EIO; 362 363 /* fail if there's no chip present */ 364 else 365 status = i2c_read_le16(client); 366 367 } else { 368 dev_dbg(&client->dev, "unsupported number of gpios\n"); 369 status = -EINVAL; 370 } 371 372 if (status < 0) 373 goto fail; 374 375 gpio->chip.label = client->name; 376 377 gpio->client = client; 378 i2c_set_clientdata(client, gpio); 379 380 /* NOTE: these chips have strange "quasi-bidirectional" I/O pins. 381 * We can't actually know whether a pin is configured (a) as output 382 * and driving the signal low, or (b) as input and reporting a low 383 * value ... without knowing the last value written since the chip 384 * came out of reset (if any). We can't read the latched output. 385 * 386 * In short, the only reliable solution for setting up pin direction 387 * is to do it explicitly. The setup() method can do that, but it 388 * may cause transient glitching since it can't know the last value 389 * written (some pins may need to be driven low). 390 * 391 * Using n_latch avoids that trouble. When left initialized to zero, 392 * our software copy of the "latch" then matches the chip's all-ones 393 * reset state. Otherwise it flags pins to be driven low. 394 */ 395 gpio->out = ~n_latch; 396 gpio->status = gpio->read(gpio->client); 397 398 /* Enable irqchip if we have an interrupt */ 399 if (client->irq) { 400 struct gpio_irq_chip *girq; 401 402 status = devm_request_threaded_irq(&client->dev, client->irq, 403 NULL, pcf857x_irq, IRQF_ONESHOT | 404 IRQF_TRIGGER_FALLING | IRQF_SHARED, 405 dev_name(&client->dev), gpio); 406 if (status) 407 goto fail; 408 409 girq = &gpio->chip.irq; 410 gpio_irq_chip_set_chip(girq, &pcf857x_irq_chip); 411 /* This will let us handle the parent IRQ in the driver */ 412 girq->parent_handler = NULL; 413 girq->num_parents = 0; 414 girq->parents = NULL; 415 girq->default_type = IRQ_TYPE_NONE; 416 girq->handler = handle_level_irq; 417 girq->threaded = true; 418 } 419 420 status = devm_gpiochip_add_data(&client->dev, &gpio->chip, gpio); 421 if (status < 0) 422 goto fail; 423 424 dev_info(&client->dev, "probed\n"); 425 426 return 0; 427 428 fail: 429 dev_dbg(&client->dev, "probe error %d for '%s'\n", status, 430 client->name); 431 432 return status; 433 } 434 435 static void pcf857x_shutdown(struct i2c_client *client) 436 { 437 struct pcf857x *gpio = i2c_get_clientdata(client); 438 439 /* Drive all the I/O lines high */ 440 gpio->write(gpio->client, BIT(gpio->chip.ngpio) - 1); 441 } 442 443 static struct i2c_driver pcf857x_driver = { 444 .driver = { 445 .name = "pcf857x", 446 .of_match_table = pcf857x_of_table, 447 }, 448 .probe = pcf857x_probe, 449 .shutdown = pcf857x_shutdown, 450 .id_table = pcf857x_id, 451 }; 452 453 static int __init pcf857x_init(void) 454 { 455 return i2c_add_driver(&pcf857x_driver); 456 } 457 /* register after i2c postcore initcall and before 458 * subsys initcalls that may rely on these GPIOs 459 */ 460 subsys_initcall(pcf857x_init); 461 462 static void __exit pcf857x_exit(void) 463 { 464 i2c_del_driver(&pcf857x_driver); 465 } 466 module_exit(pcf857x_exit); 467 468 MODULE_DESCRIPTION("Driver for pcf857x, pca857x, and pca967x I2C GPIO expanders"); 469 MODULE_LICENSE("GPL"); 470 MODULE_AUTHOR("David Brownell"); 471