1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/pm.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 28 #include <linux/gpio/consumer.h> 29 #include <linux/gpio/driver.h> 30 31 #include <linux/pinctrl/pinconf-generic.h> 32 33 #include <linux/platform_data/pca953x.h> 34 35 #define PCA953X_INPUT 0x00 36 #define PCA953X_OUTPUT 0x01 37 #define PCA953X_INVERT 0x02 38 #define PCA953X_DIRECTION 0x03 39 40 #define TCA6418_INPUT 0x14 41 #define TCA6418_OUTPUT 0x17 42 #define TCA6418_DIRECTION 0x23 43 44 #define REG_ADDR_MASK GENMASK(5, 0) 45 #define REG_ADDR_EXT BIT(6) 46 #define REG_ADDR_AI BIT(7) 47 48 #define PCA957X_IN 0x00 49 #define PCA957X_INVRT 0x01 50 #define PCA957X_BKEN 0x02 51 #define PCA957X_PUPD 0x03 52 #define PCA957X_CFG 0x04 53 #define PCA957X_OUT 0x05 54 #define PCA957X_MSK 0x06 55 #define PCA957X_INTS 0x07 56 57 #define PCAL953X_OUT_STRENGTH 0x20 58 #define PCAL953X_IN_LATCH 0x22 59 #define PCAL953X_PULL_EN 0x23 60 #define PCAL953X_PULL_SEL 0x24 61 #define PCAL953X_INT_MASK 0x25 62 #define PCAL953X_INT_STAT 0x26 63 #define PCAL953X_OUT_CONF 0x27 64 65 #define PCAL6524_INT_EDGE 0x28 66 #define PCAL6524_INT_CLR 0x2a 67 #define PCAL6524_IN_STATUS 0x2b 68 #define PCAL6524_OUT_INDCONF 0x2c 69 #define PCAL6524_DEBOUNCE 0x2d 70 71 #define PCA_GPIO_MASK GENMASK(7, 0) 72 73 #define PCAL_GPIO_MASK GENMASK(4, 0) 74 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 75 76 #define PCA_INT BIT(8) 77 #define PCA_PCAL BIT(9) 78 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 79 #define PCA953X_TYPE BIT(12) 80 #define PCA957X_TYPE BIT(13) 81 #define PCAL653X_TYPE BIT(14) 82 #define TCA6418_TYPE BIT(16) 83 #define PCA_TYPE_MASK GENMASK(16, 12) 84 85 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 86 87 static const struct i2c_device_id pca953x_id[] = { 88 { .name = "pca6408", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 89 { .name = "pca6416", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 90 { .name = "pca9505", .driver_data = 40 | PCA953X_TYPE | PCA_INT }, 91 { .name = "pca9506", .driver_data = 40 | PCA953X_TYPE | PCA_INT }, 92 { .name = "pca9534", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 93 { .name = "pca9535", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 94 { .name = "pca9536", .driver_data = 4 | PCA953X_TYPE }, 95 { .name = "pca9537", .driver_data = 4 | PCA953X_TYPE | PCA_INT }, 96 { .name = "pca9538", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 97 { .name = "pca9539", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 98 { .name = "pca9554", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 99 { .name = "pca9555", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 100 { .name = "pca9556", .driver_data = 8 | PCA953X_TYPE }, 101 { .name = "pca9557", .driver_data = 8 | PCA953X_TYPE }, 102 { .name = "pca9574", .driver_data = 8 | PCA957X_TYPE | PCA_INT }, 103 { .name = "pca9575", .driver_data = 16 | PCA957X_TYPE | PCA_INT }, 104 { .name = "pca9698", .driver_data = 40 | PCA953X_TYPE }, 105 106 { .name = "pcal6408", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 107 { .name = "pcal6416", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 108 { .name = "pcal6524", .driver_data = 24 | PCA953X_TYPE | PCA_LATCH_INT }, 109 { .name = "pcal6534", .driver_data = 34 | PCAL653X_TYPE | PCA_LATCH_INT }, 110 { .name = "pcal9535", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 111 { .name = "pcal9554b", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 112 { .name = "pcal9555a", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 113 114 { .name = "max7310", .driver_data = 8 | PCA953X_TYPE }, 115 { .name = "max7312", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 116 { .name = "max7313", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 117 { .name = "max7315", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 118 { .name = "max7318", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 119 { .name = "pca6107", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 120 { .name = "tca6408", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 121 { .name = "tca6416", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 122 { .name = "tca6418", .driver_data = 18 | TCA6418_TYPE | PCA_INT }, 123 { .name = "tca6424", .driver_data = 24 | PCA953X_TYPE | PCA_INT }, 124 { .name = "tca9538", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 125 { .name = "tca9539", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 126 { .name = "tca9554", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 127 { .name = "xra1202", .driver_data = 8 | PCA953X_TYPE }, 128 129 { .name = "tcal6408", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 130 { .name = "tcal6416", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 131 { } 132 }; 133 MODULE_DEVICE_TABLE(i2c, pca953x_id); 134 135 #ifdef CONFIG_GPIO_PCA953X_IRQ 136 137 #include <linux/acpi.h> 138 #include <linux/dmi.h> 139 140 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 141 142 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 143 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 144 { } 145 }; 146 147 static int pca953x_acpi_get_irq(struct device *dev) 148 { 149 int ret; 150 151 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 152 if (ret) 153 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 154 155 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 156 if (ret < 0) 157 return ret; 158 159 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 160 return ret; 161 } 162 163 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 164 { 165 /* 166 * On Intel Galileo Gen 2 board the IRQ pin of one of 167 * the I²C GPIO expanders, which has GpioInt() resource, 168 * is provided as an absolute number instead of being 169 * relative. Since first controller (gpio-sch.c) and 170 * second (gpio-dwapb.c) are at the fixed bases, we may 171 * safely refer to the number in the global space to get 172 * an IRQ out of it. 173 */ 174 .matches = { 175 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 176 }, 177 }, 178 {} 179 }; 180 #endif 181 182 static const struct acpi_device_id pca953x_acpi_ids[] = { 183 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 184 { } 185 }; 186 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 187 188 #define MAX_BANK 5 189 #define BANK_SZ 8 190 #define MAX_LINE (MAX_BANK * BANK_SZ) 191 192 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 193 194 struct pca953x_reg_config { 195 int direction; 196 int output; 197 int input; 198 int invert; 199 }; 200 201 static const struct pca953x_reg_config pca953x_regs = { 202 .direction = PCA953X_DIRECTION, 203 .output = PCA953X_OUTPUT, 204 .input = PCA953X_INPUT, 205 .invert = PCA953X_INVERT, 206 }; 207 208 static const struct pca953x_reg_config pca957x_regs = { 209 .direction = PCA957X_CFG, 210 .output = PCA957X_OUT, 211 .input = PCA957X_IN, 212 .invert = PCA957X_INVRT, 213 }; 214 215 static const struct pca953x_reg_config tca6418_regs = { 216 .direction = TCA6418_DIRECTION, 217 .output = TCA6418_OUTPUT, 218 .input = TCA6418_INPUT, 219 .invert = 0xFF, /* Does not apply */ 220 }; 221 222 struct pca953x_chip { 223 unsigned gpio_start; 224 struct mutex i2c_lock; 225 struct regmap *regmap; 226 227 #ifdef CONFIG_GPIO_PCA953X_IRQ 228 struct mutex irq_lock; 229 DECLARE_BITMAP(irq_mask, MAX_LINE); 230 DECLARE_BITMAP(irq_stat, MAX_LINE); 231 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 232 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 233 DECLARE_BITMAP(irq_trig_level_high, MAX_LINE); 234 DECLARE_BITMAP(irq_trig_level_low, MAX_LINE); 235 #endif 236 atomic_t wakeup_path; 237 238 struct i2c_client *client; 239 struct gpio_chip gpio_chip; 240 unsigned long driver_data; 241 struct regulator *regulator; 242 243 const struct pca953x_reg_config *regs; 244 245 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 246 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 247 u32 checkbank); 248 }; 249 250 static int pca953x_bank_shift(struct pca953x_chip *chip) 251 { 252 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 253 } 254 255 /* 256 * Helper function to get the correct bit mask for a given offset and chip type. 257 * The TCA6418's input, output, and direction banks have a peculiar bit order: 258 * the first byte uses reversed bit order, while the second byte uses standard order. 259 */ 260 static inline u8 pca953x_get_bit_mask(struct pca953x_chip *chip, unsigned int offset) 261 { 262 unsigned int bit_pos_in_bank = offset % BANK_SZ; 263 int msb = BANK_SZ - 1; 264 265 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE && offset <= msb) 266 return BIT(msb - bit_pos_in_bank); 267 268 return BIT(bit_pos_in_bank); 269 } 270 271 #define PCA953x_BANK_INPUT BIT(0) 272 #define PCA953x_BANK_OUTPUT BIT(1) 273 #define PCA953x_BANK_POLARITY BIT(2) 274 #define PCA953x_BANK_CONFIG BIT(3) 275 276 #define PCA957x_BANK_INPUT BIT(0) 277 #define PCA957x_BANK_POLARITY BIT(1) 278 #define PCA957x_BANK_BUSHOLD BIT(2) 279 #define PCA957x_BANK_CONFIG BIT(4) 280 #define PCA957x_BANK_OUTPUT BIT(5) 281 282 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 283 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 284 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 285 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 286 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 287 288 /* 289 * We care about the following registers: 290 * - Standard set, below 0x40, each port can be replicated up to 8 times 291 * - PCA953x standard 292 * Input port 0x00 + 0 * bank_size R 293 * Output port 0x00 + 1 * bank_size RW 294 * Polarity Inversion port 0x00 + 2 * bank_size RW 295 * Configuration port 0x00 + 3 * bank_size RW 296 * - PCA957x with mixed up registers 297 * Input port 0x00 + 0 * bank_size R 298 * Polarity Inversion port 0x00 + 1 * bank_size RW 299 * Bus hold port 0x00 + 2 * bank_size RW 300 * Configuration port 0x00 + 4 * bank_size RW 301 * Output port 0x00 + 5 * bank_size RW 302 * 303 * - Extended set, above 0x40, often chip specific. 304 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 305 * Input latch register 0x40 + 2 * bank_size RW 306 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 307 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 308 * Interrupt mask register 0x40 + 5 * bank_size RW 309 * Interrupt status register 0x40 + 6 * bank_size R 310 * 311 * - Registers with bit 0x80 set, the AI bit (auto increment) 312 * The bit is cleared and the registers fall into one of the 313 * categories above. 314 */ 315 316 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 317 u32 checkbank) 318 { 319 int bank_shift = pca953x_bank_shift(chip); 320 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 321 int offset = reg & (BIT(bank_shift) - 1); 322 323 /* Special PCAL extended register check. */ 324 if (reg & REG_ADDR_EXT) { 325 if (!(chip->driver_data & PCA_PCAL)) 326 return false; 327 bank += 8; 328 } 329 330 /* Register is not in the matching bank. */ 331 if (!(BIT(bank) & checkbank)) 332 return false; 333 334 /* Register is not within allowed range of bank. */ 335 if (offset >= NBANK(chip)) 336 return false; 337 338 return true; 339 } 340 341 /* 342 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 343 * same register layout as the PCAL6524, the spacing of the registers has been 344 * fundamentally altered by compacting them and thus does not obey the same 345 * rules, including being able to use bit shifting to determine bank. These 346 * chips hence need special handling here. 347 */ 348 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 349 u32 checkbank) 350 { 351 int bank_shift; 352 int bank; 353 int offset; 354 355 if (reg >= 0x54) { 356 /* 357 * Handle lack of reserved registers after output port 358 * configuration register to form a bank. 359 */ 360 reg -= 0x54; 361 bank_shift = 16; 362 } else if (reg >= 0x30) { 363 /* 364 * Reserved block between 14h and 2Fh does not align on 365 * expected bank boundaries like other devices. 366 */ 367 reg -= 0x30; 368 bank_shift = 8; 369 } else { 370 bank_shift = 0; 371 } 372 373 bank = bank_shift + reg / NBANK(chip); 374 offset = reg % NBANK(chip); 375 376 /* Register is not in the matching bank. */ 377 if (!(BIT(bank) & checkbank)) 378 return false; 379 380 /* Register is not within allowed range of bank. */ 381 if (offset >= NBANK(chip)) 382 return false; 383 384 return true; 385 } 386 387 /* TCA6418 breaks the PCA953x register order rule */ 388 static bool tca6418_check_register(struct pca953x_chip *chip, unsigned int reg, 389 u32 access_type_mask) 390 { 391 /* Valid Input Registers - BIT(0) for readable access */ 392 if (reg >= TCA6418_INPUT && reg < (TCA6418_INPUT + NBANK(chip))) 393 return (access_type_mask & BIT(0)); 394 395 /* Valid Output Registers - BIT(1) for writeable access */ 396 if (reg >= TCA6418_OUTPUT && reg < (TCA6418_OUTPUT + NBANK(chip))) 397 return (access_type_mask & (BIT(0) | BIT(1))); 398 399 /* Valid Direction Registers - BIT(2) for volatile access */ 400 if (reg >= TCA6418_DIRECTION && reg < (TCA6418_DIRECTION + NBANK(chip))) 401 return (access_type_mask & (BIT(0) | BIT(1))); 402 403 return false; 404 } 405 406 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 407 { 408 struct pca953x_chip *chip = dev_get_drvdata(dev); 409 u32 bank; 410 411 switch (PCA_CHIP_TYPE(chip->driver_data)) { 412 case PCA957X_TYPE: 413 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 414 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 415 PCA957x_BANK_BUSHOLD; 416 break; 417 case TCA6418_TYPE: 418 /* BIT(0) to indicate read access */ 419 return tca6418_check_register(chip, reg, BIT(0)); 420 default: 421 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 422 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 423 break; 424 } 425 426 if (chip->driver_data & PCA_PCAL) { 427 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 428 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 429 PCAL9xxx_BANK_IRQ_STAT; 430 } 431 432 return chip->check_reg(chip, reg, bank); 433 } 434 435 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 436 { 437 struct pca953x_chip *chip = dev_get_drvdata(dev); 438 u32 bank; 439 440 switch (PCA_CHIP_TYPE(chip->driver_data)) { 441 case PCA957X_TYPE: 442 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 443 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 444 break; 445 case TCA6418_TYPE: 446 /* BIT(1) for write access */ 447 return tca6418_check_register(chip, reg, BIT(1)); 448 default: 449 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 450 PCA953x_BANK_CONFIG; 451 break; 452 } 453 454 if (chip->driver_data & PCA_PCAL) 455 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 456 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 457 458 return chip->check_reg(chip, reg, bank); 459 } 460 461 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 462 { 463 struct pca953x_chip *chip = dev_get_drvdata(dev); 464 u32 bank; 465 466 switch (PCA_CHIP_TYPE(chip->driver_data)) { 467 case PCA957X_TYPE: 468 bank = PCA957x_BANK_INPUT; 469 break; 470 case TCA6418_TYPE: 471 /* BIT(2) for volatile access */ 472 return tca6418_check_register(chip, reg, BIT(2)); 473 default: 474 bank = PCA953x_BANK_INPUT; 475 break; 476 } 477 478 if (chip->driver_data & PCA_PCAL) 479 bank |= PCAL9xxx_BANK_IRQ_STAT; 480 481 return chip->check_reg(chip, reg, bank); 482 } 483 484 static const struct regmap_config pca953x_i2c_regmap = { 485 .reg_bits = 8, 486 .val_bits = 8, 487 488 .use_single_read = true, 489 .use_single_write = true, 490 491 .readable_reg = pca953x_readable_register, 492 .writeable_reg = pca953x_writeable_register, 493 .volatile_reg = pca953x_volatile_register, 494 495 .disable_locking = true, 496 .cache_type = REGCACHE_MAPLE, 497 .max_register = 0x7f, 498 }; 499 500 static const struct regmap_config pca953x_ai_i2c_regmap = { 501 .reg_bits = 8, 502 .val_bits = 8, 503 504 .read_flag_mask = REG_ADDR_AI, 505 .write_flag_mask = REG_ADDR_AI, 506 507 .readable_reg = pca953x_readable_register, 508 .writeable_reg = pca953x_writeable_register, 509 .volatile_reg = pca953x_volatile_register, 510 511 .disable_locking = true, 512 .cache_type = REGCACHE_MAPLE, 513 .max_register = 0x7f, 514 }; 515 516 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 517 { 518 int bank_shift = pca953x_bank_shift(chip); 519 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 520 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 521 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 522 523 return regaddr; 524 } 525 526 /* 527 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 528 * fit within the bit shifting scheme used for other devices. 529 */ 530 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 531 { 532 int addr; 533 int pinctrl; 534 535 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 536 537 switch (reg) { 538 case PCAL953X_OUT_STRENGTH: 539 case PCAL953X_IN_LATCH: 540 case PCAL953X_PULL_EN: 541 case PCAL953X_PULL_SEL: 542 case PCAL953X_INT_MASK: 543 case PCAL953X_INT_STAT: 544 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 545 break; 546 case PCAL6524_INT_EDGE: 547 case PCAL6524_INT_CLR: 548 case PCAL6524_IN_STATUS: 549 case PCAL6524_OUT_INDCONF: 550 case PCAL6524_DEBOUNCE: 551 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 552 break; 553 default: 554 pinctrl = 0; 555 break; 556 } 557 558 return pinctrl + addr + (off / BANK_SZ); 559 } 560 561 static u8 tca6418_recalc_addr(struct pca953x_chip *chip, int reg_base, int offset) 562 { 563 /* 564 * reg_base will be TCA6418_INPUT, TCA6418_OUTPUT, or TCA6418_DIRECTION 565 * offset is the global GPIO line offset (0-17) 566 * BANK_SZ is 8 for TCA6418 (8 bits per register bank) 567 */ 568 return reg_base + (offset / BANK_SZ); 569 } 570 571 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 572 { 573 u8 regaddr = chip->recalc_addr(chip, reg, 0); 574 u8 value[MAX_BANK]; 575 int i, ret; 576 577 for (i = 0; i < NBANK(chip); i++) 578 value[i] = bitmap_get_value8(val, i * BANK_SZ); 579 580 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 581 if (ret < 0) { 582 dev_err(&chip->client->dev, "failed writing register: %d\n", ret); 583 return ret; 584 } 585 586 return 0; 587 } 588 589 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 590 { 591 u8 regaddr = chip->recalc_addr(chip, reg, 0); 592 u8 value[MAX_BANK]; 593 int i, ret; 594 595 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 596 if (ret < 0) { 597 dev_err(&chip->client->dev, "failed reading register: %d\n", ret); 598 return ret; 599 } 600 601 for (i = 0; i < NBANK(chip); i++) 602 bitmap_set_value8(val, value[i], i * BANK_SZ); 603 604 return 0; 605 } 606 607 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 608 { 609 struct pca953x_chip *chip = gpiochip_get_data(gc); 610 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 611 u8 bit = pca953x_get_bit_mask(chip, off); 612 613 guard(mutex)(&chip->i2c_lock); 614 615 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 616 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 617 618 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 619 } 620 621 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 622 unsigned off, int val) 623 { 624 struct pca953x_chip *chip = gpiochip_get_data(gc); 625 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 626 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 627 u8 bit = pca953x_get_bit_mask(chip, off); 628 int ret; 629 630 guard(mutex)(&chip->i2c_lock); 631 632 /* set output level */ 633 ret = regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 634 if (ret) 635 return ret; 636 637 /* 638 * then direction 639 * (in/out logic is inverted on TCA6418) 640 */ 641 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 642 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 643 644 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 645 } 646 647 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 648 { 649 struct pca953x_chip *chip = gpiochip_get_data(gc); 650 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 651 u8 bit = pca953x_get_bit_mask(chip, off); 652 u32 reg_val; 653 int ret; 654 655 scoped_guard(mutex, &chip->i2c_lock) 656 ret = regmap_read(chip->regmap, inreg, ®_val); 657 if (ret < 0) 658 return ret; 659 660 return !!(reg_val & bit); 661 } 662 663 static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 664 int val) 665 { 666 struct pca953x_chip *chip = gpiochip_get_data(gc); 667 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 668 u8 bit = pca953x_get_bit_mask(chip, off); 669 670 guard(mutex)(&chip->i2c_lock); 671 672 return regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 673 } 674 675 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 676 { 677 struct pca953x_chip *chip = gpiochip_get_data(gc); 678 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 679 u8 bit = pca953x_get_bit_mask(chip, off); 680 u32 reg_val; 681 int ret; 682 683 scoped_guard(mutex, &chip->i2c_lock) 684 ret = regmap_read(chip->regmap, dirreg, ®_val); 685 if (ret < 0) 686 return ret; 687 688 /* (in/out logic is inverted on TCA6418) */ 689 if (reg_val & bit) { 690 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 691 return GPIO_LINE_DIRECTION_OUT; 692 693 return GPIO_LINE_DIRECTION_IN; 694 } 695 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 696 return GPIO_LINE_DIRECTION_IN; 697 698 return GPIO_LINE_DIRECTION_OUT; 699 } 700 701 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 702 unsigned long *mask, unsigned long *bits) 703 { 704 struct pca953x_chip *chip = gpiochip_get_data(gc); 705 DECLARE_BITMAP(reg_val, MAX_LINE); 706 int ret; 707 708 scoped_guard(mutex, &chip->i2c_lock) 709 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 710 if (ret) 711 return ret; 712 713 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 714 return 0; 715 } 716 717 static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 718 unsigned long *mask, unsigned long *bits) 719 { 720 struct pca953x_chip *chip = gpiochip_get_data(gc); 721 DECLARE_BITMAP(reg_val, MAX_LINE); 722 int ret; 723 724 guard(mutex)(&chip->i2c_lock); 725 726 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 727 if (ret) 728 return ret; 729 730 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 731 732 return pca953x_write_regs(chip, chip->regs->output, reg_val); 733 } 734 735 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 736 unsigned int offset, 737 unsigned long config) 738 { 739 enum pin_config_param param = pinconf_to_config_param(config); 740 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 741 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 742 u8 bit = BIT(offset % BANK_SZ); 743 int ret; 744 745 /* 746 * pull-up/pull-down configuration requires PCAL extended 747 * registers 748 */ 749 if (!(chip->driver_data & PCA_PCAL)) 750 return -ENOTSUPP; 751 752 guard(mutex)(&chip->i2c_lock); 753 754 /* Configure pull-up/pull-down */ 755 if (param == PIN_CONFIG_BIAS_PULL_UP) 756 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, bit); 757 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 758 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, 0); 759 else 760 ret = 0; 761 if (ret) 762 return ret; 763 764 /* Disable/Enable pull-up/pull-down */ 765 if (param == PIN_CONFIG_BIAS_DISABLE) 766 return regmap_update_bits(chip->regmap, pull_en_reg, bit, 0); 767 else 768 return regmap_update_bits(chip->regmap, pull_en_reg, bit, bit); 769 } 770 771 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 772 unsigned long config) 773 { 774 struct pca953x_chip *chip = gpiochip_get_data(gc); 775 776 switch (pinconf_to_config_param(config)) { 777 case PIN_CONFIG_BIAS_PULL_UP: 778 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 779 case PIN_CONFIG_BIAS_PULL_DOWN: 780 case PIN_CONFIG_BIAS_DISABLE: 781 return pca953x_gpio_set_pull_up_down(chip, offset, config); 782 default: 783 return -ENOTSUPP; 784 } 785 } 786 787 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 788 { 789 struct gpio_chip *gc = &chip->gpio_chip; 790 791 gc->direction_input = pca953x_gpio_direction_input; 792 gc->direction_output = pca953x_gpio_direction_output; 793 gc->get = pca953x_gpio_get_value; 794 gc->set = pca953x_gpio_set_value; 795 gc->get_direction = pca953x_gpio_get_direction; 796 gc->get_multiple = pca953x_gpio_get_multiple; 797 gc->set_multiple = pca953x_gpio_set_multiple; 798 gc->set_config = pca953x_gpio_set_config; 799 gc->can_sleep = true; 800 801 gc->base = chip->gpio_start; 802 gc->ngpio = gpios; 803 gc->label = dev_name(&chip->client->dev); 804 gc->parent = &chip->client->dev; 805 gc->owner = THIS_MODULE; 806 } 807 808 #ifdef CONFIG_GPIO_PCA953X_IRQ 809 static void pca953x_irq_mask(struct irq_data *d) 810 { 811 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 812 struct pca953x_chip *chip = gpiochip_get_data(gc); 813 irq_hw_number_t hwirq = irqd_to_hwirq(d); 814 815 clear_bit(hwirq, chip->irq_mask); 816 gpiochip_disable_irq(gc, hwirq); 817 } 818 819 static void pca953x_irq_unmask(struct irq_data *d) 820 { 821 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 822 struct pca953x_chip *chip = gpiochip_get_data(gc); 823 irq_hw_number_t hwirq = irqd_to_hwirq(d); 824 825 gpiochip_enable_irq(gc, hwirq); 826 set_bit(hwirq, chip->irq_mask); 827 } 828 829 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 830 { 831 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 832 struct pca953x_chip *chip = gpiochip_get_data(gc); 833 834 if (on) 835 atomic_inc(&chip->wakeup_path); 836 else 837 atomic_dec(&chip->wakeup_path); 838 839 return irq_set_irq_wake(chip->client->irq, on); 840 } 841 842 static void pca953x_irq_bus_lock(struct irq_data *d) 843 { 844 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 845 struct pca953x_chip *chip = gpiochip_get_data(gc); 846 847 mutex_lock(&chip->irq_lock); 848 } 849 850 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 851 { 852 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 853 struct pca953x_chip *chip = gpiochip_get_data(gc); 854 DECLARE_BITMAP(irq_mask, MAX_LINE); 855 DECLARE_BITMAP(reg_direction, MAX_LINE); 856 int level; 857 858 if (chip->driver_data & PCA_PCAL) { 859 DECLARE_BITMAP(latched_inputs, MAX_LINE); 860 guard(mutex)(&chip->i2c_lock); 861 862 /* Enable latch on edge-triggered interrupt-enabled inputs */ 863 bitmap_or(latched_inputs, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 864 bitmap_and(latched_inputs, latched_inputs, chip->irq_mask, gc->ngpio); 865 pca953x_write_regs(chip, PCAL953X_IN_LATCH, latched_inputs); 866 867 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 868 869 /* Unmask enabled interrupts */ 870 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 871 } 872 873 /* Switch direction to input if needed */ 874 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 875 876 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 877 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_high, gc->ngpio); 878 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_low, gc->ngpio); 879 880 /* Look for any newly setup interrupt */ 881 for_each_andnot_bit(level, irq_mask, reg_direction, gc->ngpio) 882 pca953x_gpio_direction_input(&chip->gpio_chip, level); 883 884 mutex_unlock(&chip->irq_lock); 885 } 886 887 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 888 { 889 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 890 struct pca953x_chip *chip = gpiochip_get_data(gc); 891 struct device *dev = &chip->client->dev; 892 irq_hw_number_t hwirq = irqd_to_hwirq(d); 893 894 if (!(type & IRQ_TYPE_SENSE_MASK)) { 895 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 896 return -EINVAL; 897 } 898 899 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 900 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 901 assign_bit(hwirq, chip->irq_trig_level_low, type & IRQ_TYPE_LEVEL_LOW); 902 assign_bit(hwirq, chip->irq_trig_level_high, type & IRQ_TYPE_LEVEL_HIGH); 903 904 return 0; 905 } 906 907 static void pca953x_irq_shutdown(struct irq_data *d) 908 { 909 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 910 struct pca953x_chip *chip = gpiochip_get_data(gc); 911 irq_hw_number_t hwirq = irqd_to_hwirq(d); 912 913 clear_bit(hwirq, chip->irq_trig_raise); 914 clear_bit(hwirq, chip->irq_trig_fall); 915 clear_bit(hwirq, chip->irq_trig_level_low); 916 clear_bit(hwirq, chip->irq_trig_level_high); 917 918 pca953x_irq_mask(d); 919 } 920 921 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 922 { 923 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 924 925 seq_puts(p, dev_name(gc->parent)); 926 } 927 928 static const struct irq_chip pca953x_irq_chip = { 929 .irq_mask = pca953x_irq_mask, 930 .irq_unmask = pca953x_irq_unmask, 931 .irq_set_wake = pca953x_irq_set_wake, 932 .irq_bus_lock = pca953x_irq_bus_lock, 933 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 934 .irq_set_type = pca953x_irq_set_type, 935 .irq_shutdown = pca953x_irq_shutdown, 936 .irq_print_chip = pca953x_irq_print_chip, 937 .flags = IRQCHIP_IMMUTABLE, 938 GPIOCHIP_IRQ_RESOURCE_HELPERS, 939 }; 940 941 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 942 { 943 struct gpio_chip *gc = &chip->gpio_chip; 944 DECLARE_BITMAP(reg_direction, MAX_LINE); 945 DECLARE_BITMAP(old_stat, MAX_LINE); 946 DECLARE_BITMAP(cur_stat, MAX_LINE); 947 DECLARE_BITMAP(new_stat, MAX_LINE); 948 DECLARE_BITMAP(int_stat, MAX_LINE); 949 DECLARE_BITMAP(trigger, MAX_LINE); 950 DECLARE_BITMAP(edges, MAX_LINE); 951 int ret; 952 953 if (chip->driver_data & PCA_PCAL) { 954 /* Read INT_STAT before it is cleared by the input-port read. */ 955 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, int_stat); 956 if (ret) 957 return false; 958 } 959 960 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 961 if (ret) 962 return false; 963 964 if (chip->driver_data & PCA_PCAL) { 965 /* Detect short pulses via INT_STAT. */ 966 bitmap_and(trigger, int_stat, chip->irq_mask, gc->ngpio); 967 968 /* Apply filter for rising/falling edge selection. */ 969 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 970 cur_stat, gc->ngpio); 971 972 bitmap_and(int_stat, new_stat, trigger, gc->ngpio); 973 } else { 974 bitmap_zero(int_stat, gc->ngpio); 975 } 976 977 /* Remove output pins from the equation */ 978 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 979 980 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 981 982 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 983 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 984 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 985 986 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 987 988 if (bitmap_empty(chip->irq_trig_level_high, gc->ngpio) && 989 bitmap_empty(chip->irq_trig_level_low, gc->ngpio)) { 990 if (bitmap_empty(trigger, gc->ngpio) && 991 bitmap_empty(int_stat, gc->ngpio)) 992 return false; 993 } 994 995 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 996 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 997 bitmap_or(edges, old_stat, cur_stat, gc->ngpio); 998 bitmap_and(pending, edges, trigger, gc->ngpio); 999 bitmap_or(pending, pending, int_stat, gc->ngpio); 1000 1001 bitmap_and(cur_stat, new_stat, chip->irq_trig_level_high, gc->ngpio); 1002 bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio); 1003 bitmap_or(pending, pending, cur_stat, gc->ngpio); 1004 1005 bitmap_andnot(cur_stat, reg_direction, new_stat, gc->ngpio); 1006 bitmap_and(old_stat, cur_stat, chip->irq_trig_level_low, gc->ngpio); 1007 bitmap_and(old_stat, old_stat, chip->irq_mask, gc->ngpio); 1008 bitmap_or(pending, pending, old_stat, gc->ngpio); 1009 1010 return !bitmap_empty(pending, gc->ngpio); 1011 } 1012 1013 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 1014 { 1015 struct pca953x_chip *chip = devid; 1016 struct gpio_chip *gc = &chip->gpio_chip; 1017 DECLARE_BITMAP(pending, MAX_LINE); 1018 int level; 1019 bool ret; 1020 1021 bitmap_zero(pending, MAX_LINE); 1022 1023 scoped_guard(mutex, &chip->i2c_lock) 1024 ret = pca953x_irq_pending(chip, pending); 1025 if (ret) { 1026 ret = 0; 1027 1028 for_each_set_bit(level, pending, gc->ngpio) { 1029 int nested_irq = irq_find_mapping(gc->irq.domain, level); 1030 1031 if (unlikely(nested_irq <= 0)) { 1032 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1033 continue; 1034 } 1035 1036 handle_nested_irq(nested_irq); 1037 ret = 1; 1038 } 1039 } 1040 1041 return IRQ_RETVAL(ret); 1042 } 1043 1044 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1045 { 1046 struct i2c_client *client = chip->client; 1047 struct device *dev = &client->dev; 1048 DECLARE_BITMAP(reg_direction, MAX_LINE); 1049 DECLARE_BITMAP(irq_stat, MAX_LINE); 1050 struct gpio_chip *gc = &chip->gpio_chip; 1051 struct gpio_irq_chip *girq; 1052 int ret; 1053 1054 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 1055 ret = pca953x_acpi_get_irq(dev); 1056 if (ret > 0) 1057 client->irq = ret; 1058 } 1059 1060 if (!client->irq) 1061 return 0; 1062 1063 if (irq_base == -1) 1064 return 0; 1065 1066 if (!(chip->driver_data & PCA_INT)) 1067 return 0; 1068 1069 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 1070 if (ret) 1071 return ret; 1072 1073 /* 1074 * There is no way to know which GPIO line generated the 1075 * interrupt. We have to rely on the previous read for 1076 * this purpose. 1077 */ 1078 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 1079 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 1080 mutex_init(&chip->irq_lock); 1081 1082 girq = &chip->gpio_chip.irq; 1083 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 1084 /* This will let us handle the parent IRQ in the driver */ 1085 girq->parent_handler = NULL; 1086 girq->num_parents = 0; 1087 girq->parents = NULL; 1088 girq->default_type = IRQ_TYPE_NONE; 1089 girq->handler = handle_simple_irq; 1090 girq->threaded = true; 1091 girq->first = irq_base; /* FIXME: get rid of this */ 1092 1093 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 1094 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 1095 chip); 1096 if (ret) 1097 return dev_err_probe(dev, ret, "failed to request irq\n"); 1098 1099 return 0; 1100 } 1101 1102 #else /* CONFIG_GPIO_PCA953X_IRQ */ 1103 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1104 { 1105 struct i2c_client *client = chip->client; 1106 struct device *dev = &client->dev; 1107 1108 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 1109 dev_warn(dev, "interrupt support not compiled in\n"); 1110 1111 return 0; 1112 } 1113 #endif 1114 1115 static int device_pca95xx_init(struct pca953x_chip *chip) 1116 { 1117 DECLARE_BITMAP(val, MAX_LINE); 1118 u8 regaddr; 1119 int ret; 1120 1121 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1122 ret = regcache_sync_region(chip->regmap, regaddr, 1123 regaddr + NBANK(chip) - 1); 1124 if (ret) 1125 return ret; 1126 1127 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1128 ret = regcache_sync_region(chip->regmap, regaddr, 1129 regaddr + NBANK(chip) - 1); 1130 if (ret) 1131 return ret; 1132 1133 /* clear polarity inversion */ 1134 bitmap_zero(val, MAX_LINE); 1135 1136 return pca953x_write_regs(chip, chip->regs->invert, val); 1137 } 1138 1139 static int device_pca957x_init(struct pca953x_chip *chip) 1140 { 1141 DECLARE_BITMAP(val, MAX_LINE); 1142 unsigned int i; 1143 int ret; 1144 1145 ret = device_pca95xx_init(chip); 1146 if (ret) 1147 return ret; 1148 1149 /* To enable register 6, 7 to control pull up and pull down */ 1150 for (i = 0; i < NBANK(chip); i++) 1151 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1152 1153 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1154 } 1155 1156 static void pca953x_disable_regulator(void *reg) 1157 { 1158 regulator_disable(reg); 1159 } 1160 1161 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1162 { 1163 struct device *dev = &chip->client->dev; 1164 struct regulator *reg = chip->regulator; 1165 int ret; 1166 1167 reg = devm_regulator_get(dev, "vcc"); 1168 if (IS_ERR(reg)) 1169 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1170 1171 ret = regulator_enable(reg); 1172 if (ret) 1173 return dev_err_probe(dev, ret, "reg en err\n"); 1174 1175 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1176 if (ret) 1177 return ret; 1178 1179 chip->regulator = reg; 1180 return 0; 1181 } 1182 1183 static int pca953x_probe(struct i2c_client *client) 1184 { 1185 struct device *dev = &client->dev; 1186 struct pca953x_platform_data *pdata; 1187 struct pca953x_chip *chip; 1188 int irq_base; 1189 int ret; 1190 const struct regmap_config *regmap_config; 1191 1192 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1193 if (chip == NULL) 1194 return -ENOMEM; 1195 1196 pdata = dev_get_platdata(dev); 1197 if (pdata) { 1198 irq_base = pdata->irq_base; 1199 chip->gpio_start = pdata->gpio_base; 1200 } else { 1201 struct gpio_desc *reset_gpio; 1202 1203 chip->gpio_start = -1; 1204 irq_base = 0; 1205 1206 /* 1207 * See if we need to de-assert a reset pin. 1208 * 1209 * There is no known ACPI-enabled platforms that are 1210 * using "reset" GPIO. Otherwise any of those platform 1211 * must use _DSD method with corresponding property. 1212 */ 1213 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1214 if (IS_ERR(reset_gpio)) 1215 return dev_err_probe(dev, PTR_ERR(reset_gpio), 1216 "Failed to get reset gpio\n"); 1217 } 1218 1219 chip->client = client; 1220 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1221 if (!chip->driver_data) 1222 return -ENODEV; 1223 1224 ret = pca953x_get_and_enable_regulator(chip); 1225 if (ret) 1226 return ret; 1227 1228 i2c_set_clientdata(client, chip); 1229 1230 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1231 1232 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1233 dev_info(dev, "using auto increment\n"); 1234 regmap_config = &pca953x_ai_i2c_regmap; 1235 } else { 1236 dev_info(dev, "using no auto increment\n"); 1237 regmap_config = &pca953x_i2c_regmap; 1238 } 1239 1240 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1241 case PCAL653X_TYPE: 1242 chip->recalc_addr = pcal6534_recalc_addr; 1243 chip->check_reg = pcal6534_check_register; 1244 break; 1245 case TCA6418_TYPE: 1246 chip->recalc_addr = tca6418_recalc_addr; 1247 /* 1248 * We don't assign chip->check_reg = tca6418_check_register directly here. 1249 * Instead, the wrappers handle the dispatch based on PCA_CHIP_TYPE. 1250 */ 1251 break; 1252 default: 1253 chip->recalc_addr = pca953x_recalc_addr; 1254 chip->check_reg = pca953x_check_register; 1255 break; 1256 } 1257 1258 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1259 if (IS_ERR(chip->regmap)) 1260 return PTR_ERR(chip->regmap); 1261 1262 regcache_mark_dirty(chip->regmap); 1263 1264 mutex_init(&chip->i2c_lock); 1265 /* 1266 * In case we have an i2c-mux controlled by a GPIO provided by an 1267 * expander using the same driver higher on the device tree, read the 1268 * i2c adapter nesting depth and use the retrieved value as lockdep 1269 * subclass for chip->i2c_lock. 1270 * 1271 * REVISIT: This solution is not complete. It protects us from lockdep 1272 * false positives when the expander controlling the i2c-mux is on 1273 * a different level on the device tree, but not when it's on the same 1274 * level on a different branch (in which case the subclass number 1275 * would be the same). 1276 * 1277 * TODO: Once a correct solution is developed, a similar fix should be 1278 * applied to all other i2c-controlled GPIO expanders (and potentially 1279 * regmap-i2c). 1280 */ 1281 lockdep_set_subclass(&chip->i2c_lock, 1282 i2c_adapter_depth(client->adapter)); 1283 1284 /* 1285 * initialize cached registers from their original values. 1286 * we can't share this chip with another i2c master. 1287 */ 1288 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1289 case PCA957X_TYPE: 1290 chip->regs = &pca957x_regs; 1291 ret = device_pca957x_init(chip); 1292 break; 1293 case TCA6418_TYPE: 1294 chip->regs = &tca6418_regs; 1295 break; 1296 default: 1297 chip->regs = &pca953x_regs; 1298 ret = device_pca95xx_init(chip); 1299 break; 1300 } 1301 if (ret) 1302 return ret; 1303 1304 ret = pca953x_irq_setup(chip, irq_base); 1305 if (ret) 1306 return ret; 1307 1308 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1309 } 1310 1311 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1312 { 1313 struct device *dev = &chip->client->dev; 1314 int ret; 1315 u8 regaddr; 1316 1317 /* 1318 * The ordering between direction and output is important, 1319 * sync these registers first and only then sync the rest. 1320 */ 1321 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1322 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1323 if (ret) { 1324 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1325 return ret; 1326 } 1327 1328 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1329 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1330 if (ret) { 1331 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1332 return ret; 1333 } 1334 1335 #ifdef CONFIG_GPIO_PCA953X_IRQ 1336 if (chip->driver_data & PCA_PCAL) { 1337 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1338 ret = regcache_sync_region(chip->regmap, regaddr, 1339 regaddr + NBANK(chip) - 1); 1340 if (ret) { 1341 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1342 ret); 1343 return ret; 1344 } 1345 1346 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1347 ret = regcache_sync_region(chip->regmap, regaddr, 1348 regaddr + NBANK(chip) - 1); 1349 if (ret) { 1350 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1351 ret); 1352 return ret; 1353 } 1354 } 1355 #endif 1356 1357 return 0; 1358 } 1359 1360 static int pca953x_restore_context(struct pca953x_chip *chip) 1361 { 1362 int ret; 1363 1364 guard(mutex)(&chip->i2c_lock); 1365 1366 if (chip->client->irq > 0) 1367 enable_irq(chip->client->irq); 1368 regcache_cache_only(chip->regmap, false); 1369 regcache_mark_dirty(chip->regmap); 1370 ret = pca953x_regcache_sync(chip); 1371 if (ret) 1372 return ret; 1373 1374 return regcache_sync(chip->regmap); 1375 } 1376 1377 static void pca953x_save_context(struct pca953x_chip *chip) 1378 { 1379 guard(mutex)(&chip->i2c_lock); 1380 1381 /* Disable IRQ to prevent early triggering while regmap "cache only" is on */ 1382 if (chip->client->irq > 0) 1383 disable_irq(chip->client->irq); 1384 regcache_cache_only(chip->regmap, true); 1385 } 1386 1387 static int pca953x_suspend(struct device *dev) 1388 { 1389 struct pca953x_chip *chip = dev_get_drvdata(dev); 1390 1391 pca953x_save_context(chip); 1392 1393 if (atomic_read(&chip->wakeup_path)) 1394 device_set_wakeup_path(dev); 1395 else 1396 regulator_disable(chip->regulator); 1397 1398 return 0; 1399 } 1400 1401 static int pca953x_resume(struct device *dev) 1402 { 1403 struct pca953x_chip *chip = dev_get_drvdata(dev); 1404 int ret; 1405 1406 if (!atomic_read(&chip->wakeup_path)) { 1407 ret = regulator_enable(chip->regulator); 1408 if (ret) { 1409 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1410 return ret; 1411 } 1412 } 1413 1414 ret = pca953x_restore_context(chip); 1415 if (ret) 1416 dev_err(dev, "Failed to restore register map: %d\n", ret); 1417 1418 return ret; 1419 } 1420 1421 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1422 1423 /* convenience to stop overlong match-table lines */ 1424 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1425 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1426 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1427 1428 static const struct of_device_id pca953x_dt_ids[] = { 1429 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1430 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1431 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1432 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1433 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1434 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1435 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1436 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1437 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1438 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1439 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1440 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1441 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1442 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1443 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1444 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1445 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1446 1447 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1448 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1449 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1450 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1451 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1452 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1453 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1454 1455 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1456 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1457 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1458 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1459 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1460 1461 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1462 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1463 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1464 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1465 { .compatible = "ti,tca6418", .data = (void *)(18 | TCA6418_TYPE | PCA_INT), }, 1466 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1467 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1468 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1469 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1470 1471 { .compatible = "ti,tcal6408", .data = OF_953X( 8, PCA_LATCH_INT), }, 1472 { .compatible = "ti,tcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1473 1474 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1475 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1476 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1477 1478 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1479 { } 1480 }; 1481 1482 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1483 1484 static struct i2c_driver pca953x_driver = { 1485 .driver = { 1486 .name = "pca953x", 1487 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1488 .of_match_table = pca953x_dt_ids, 1489 .acpi_match_table = pca953x_acpi_ids, 1490 }, 1491 .probe = pca953x_probe, 1492 .id_table = pca953x_id, 1493 }; 1494 1495 static int __init pca953x_init(void) 1496 { 1497 return i2c_add_driver(&pca953x_driver); 1498 } 1499 1500 /* 1501 * register after i2c postcore initcall and before 1502 * subsys initcalls that may rely on these GPIOs 1503 */ 1504 subsys_initcall(pca953x_init); 1505 1506 static void __exit pca953x_exit(void) 1507 { 1508 i2c_del_driver(&pca953x_driver); 1509 } 1510 module_exit(pca953x_exit); 1511 1512 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1513 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1514 MODULE_LICENSE("GPL"); 1515