1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/seq_file.h> 27 #include <linux/slab.h> 28 29 #include <linux/gpio/consumer.h> 30 #include <linux/gpio/driver.h> 31 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 #include <linux/platform_data/pca953x.h> 35 36 #define PCA953X_INPUT 0x00 37 #define PCA953X_OUTPUT 0x01 38 #define PCA953X_INVERT 0x02 39 #define PCA953X_DIRECTION 0x03 40 41 #define REG_ADDR_MASK GENMASK(5, 0) 42 #define REG_ADDR_EXT BIT(6) 43 #define REG_ADDR_AI BIT(7) 44 45 #define PCA957X_IN 0x00 46 #define PCA957X_INVRT 0x01 47 #define PCA957X_BKEN 0x02 48 #define PCA957X_PUPD 0x03 49 #define PCA957X_CFG 0x04 50 #define PCA957X_OUT 0x05 51 #define PCA957X_MSK 0x06 52 #define PCA957X_INTS 0x07 53 54 #define PCAL953X_OUT_STRENGTH 0x20 55 #define PCAL953X_IN_LATCH 0x22 56 #define PCAL953X_PULL_EN 0x23 57 #define PCAL953X_PULL_SEL 0x24 58 #define PCAL953X_INT_MASK 0x25 59 #define PCAL953X_INT_STAT 0x26 60 #define PCAL953X_OUT_CONF 0x27 61 62 #define PCAL6524_INT_EDGE 0x28 63 #define PCAL6524_INT_CLR 0x2a 64 #define PCAL6524_IN_STATUS 0x2b 65 #define PCAL6524_OUT_INDCONF 0x2c 66 #define PCAL6524_DEBOUNCE 0x2d 67 68 #define PCA_GPIO_MASK GENMASK(7, 0) 69 70 #define PCAL_GPIO_MASK GENMASK(4, 0) 71 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 72 73 #define PCA_INT BIT(8) 74 #define PCA_PCAL BIT(9) 75 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 76 #define PCA953X_TYPE BIT(12) 77 #define PCA957X_TYPE BIT(13) 78 #define PCAL653X_TYPE BIT(14) 79 #define PCA_TYPE_MASK GENMASK(15, 12) 80 81 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 82 83 static const struct i2c_device_id pca953x_id[] = { 84 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 87 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 88 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 89 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 90 { "pca9536", 4 | PCA953X_TYPE, }, 91 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 92 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 93 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 94 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 95 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 96 { "pca9556", 8 | PCA953X_TYPE, }, 97 { "pca9557", 8 | PCA953X_TYPE, }, 98 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 99 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 100 { "pca9698", 40 | PCA953X_TYPE, }, 101 102 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 103 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 104 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 105 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 106 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 107 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 108 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 109 110 { "max7310", 8 | PCA953X_TYPE, }, 111 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 112 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 113 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 114 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 115 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 116 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 117 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 118 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 119 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, }, 120 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 121 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 122 { "xra1202", 8 | PCA953X_TYPE }, 123 { } 124 }; 125 MODULE_DEVICE_TABLE(i2c, pca953x_id); 126 127 #ifdef CONFIG_GPIO_PCA953X_IRQ 128 129 #include <linux/acpi.h> 130 #include <linux/dmi.h> 131 132 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 133 134 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 136 { } 137 }; 138 139 static int pca953x_acpi_get_irq(struct device *dev) 140 { 141 int ret; 142 143 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 144 if (ret) 145 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 146 147 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 148 if (ret < 0) 149 return ret; 150 151 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 152 return ret; 153 } 154 155 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 156 { 157 /* 158 * On Intel Galileo Gen 2 board the IRQ pin of one of 159 * the I²C GPIO expanders, which has GpioInt() resource, 160 * is provided as an absolute number instead of being 161 * relative. Since first controller (gpio-sch.c) and 162 * second (gpio-dwapb.c) are at the fixed bases, we may 163 * safely refer to the number in the global space to get 164 * an IRQ out of it. 165 */ 166 .matches = { 167 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 168 }, 169 }, 170 {} 171 }; 172 #endif 173 174 static const struct acpi_device_id pca953x_acpi_ids[] = { 175 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 176 { } 177 }; 178 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 179 180 #define MAX_BANK 5 181 #define BANK_SZ 8 182 #define MAX_LINE (MAX_BANK * BANK_SZ) 183 184 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 185 186 struct pca953x_reg_config { 187 int direction; 188 int output; 189 int input; 190 int invert; 191 }; 192 193 static const struct pca953x_reg_config pca953x_regs = { 194 .direction = PCA953X_DIRECTION, 195 .output = PCA953X_OUTPUT, 196 .input = PCA953X_INPUT, 197 .invert = PCA953X_INVERT, 198 }; 199 200 static const struct pca953x_reg_config pca957x_regs = { 201 .direction = PCA957X_CFG, 202 .output = PCA957X_OUT, 203 .input = PCA957X_IN, 204 .invert = PCA957X_INVRT, 205 }; 206 207 struct pca953x_chip { 208 unsigned gpio_start; 209 struct mutex i2c_lock; 210 struct regmap *regmap; 211 212 #ifdef CONFIG_GPIO_PCA953X_IRQ 213 struct mutex irq_lock; 214 DECLARE_BITMAP(irq_mask, MAX_LINE); 215 DECLARE_BITMAP(irq_stat, MAX_LINE); 216 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 217 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 218 #endif 219 atomic_t wakeup_path; 220 221 struct i2c_client *client; 222 struct gpio_chip gpio_chip; 223 unsigned long driver_data; 224 struct regulator *regulator; 225 226 const struct pca953x_reg_config *regs; 227 228 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 229 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 230 u32 checkbank); 231 }; 232 233 static int pca953x_bank_shift(struct pca953x_chip *chip) 234 { 235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 236 } 237 238 #define PCA953x_BANK_INPUT BIT(0) 239 #define PCA953x_BANK_OUTPUT BIT(1) 240 #define PCA953x_BANK_POLARITY BIT(2) 241 #define PCA953x_BANK_CONFIG BIT(3) 242 243 #define PCA957x_BANK_INPUT BIT(0) 244 #define PCA957x_BANK_POLARITY BIT(1) 245 #define PCA957x_BANK_BUSHOLD BIT(2) 246 #define PCA957x_BANK_CONFIG BIT(4) 247 #define PCA957x_BANK_OUTPUT BIT(5) 248 249 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 250 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 251 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 252 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 253 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 254 255 /* 256 * We care about the following registers: 257 * - Standard set, below 0x40, each port can be replicated up to 8 times 258 * - PCA953x standard 259 * Input port 0x00 + 0 * bank_size R 260 * Output port 0x00 + 1 * bank_size RW 261 * Polarity Inversion port 0x00 + 2 * bank_size RW 262 * Configuration port 0x00 + 3 * bank_size RW 263 * - PCA957x with mixed up registers 264 * Input port 0x00 + 0 * bank_size R 265 * Polarity Inversion port 0x00 + 1 * bank_size RW 266 * Bus hold port 0x00 + 2 * bank_size RW 267 * Configuration port 0x00 + 4 * bank_size RW 268 * Output port 0x00 + 5 * bank_size RW 269 * 270 * - Extended set, above 0x40, often chip specific. 271 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 272 * Input latch register 0x40 + 2 * bank_size RW 273 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 274 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 275 * Interrupt mask register 0x40 + 5 * bank_size RW 276 * Interrupt status register 0x40 + 6 * bank_size R 277 * 278 * - Registers with bit 0x80 set, the AI bit 279 * The bit is cleared and the registers fall into one of the 280 * categories above. 281 */ 282 283 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 284 u32 checkbank) 285 { 286 int bank_shift = pca953x_bank_shift(chip); 287 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 288 int offset = reg & (BIT(bank_shift) - 1); 289 290 /* Special PCAL extended register check. */ 291 if (reg & REG_ADDR_EXT) { 292 if (!(chip->driver_data & PCA_PCAL)) 293 return false; 294 bank += 8; 295 } 296 297 /* Register is not in the matching bank. */ 298 if (!(BIT(bank) & checkbank)) 299 return false; 300 301 /* Register is not within allowed range of bank. */ 302 if (offset >= NBANK(chip)) 303 return false; 304 305 return true; 306 } 307 308 /* 309 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 310 * same register layout as the PCAL6524, the spacing of the registers has been 311 * fundamentally altered by compacting them and thus does not obey the same 312 * rules, including being able to use bit shifting to determine bank. These 313 * chips hence need special handling here. 314 */ 315 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 316 u32 checkbank) 317 { 318 int bank_shift; 319 int bank; 320 int offset; 321 322 if (reg >= 0x54) { 323 /* 324 * Handle lack of reserved registers after output port 325 * configuration register to form a bank. 326 */ 327 reg -= 0x54; 328 bank_shift = 16; 329 } else if (reg >= 0x30) { 330 /* 331 * Reserved block between 14h and 2Fh does not align on 332 * expected bank boundaries like other devices. 333 */ 334 reg -= 0x30; 335 bank_shift = 8; 336 } else { 337 bank_shift = 0; 338 } 339 340 bank = bank_shift + reg / NBANK(chip); 341 offset = reg % NBANK(chip); 342 343 /* Register is not in the matching bank. */ 344 if (!(BIT(bank) & checkbank)) 345 return false; 346 347 /* Register is not within allowed range of bank. */ 348 if (offset >= NBANK(chip)) 349 return false; 350 351 return true; 352 } 353 354 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 355 { 356 struct pca953x_chip *chip = dev_get_drvdata(dev); 357 u32 bank; 358 359 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 360 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 361 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 362 PCA957x_BANK_BUSHOLD; 363 } else { 364 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 365 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 366 } 367 368 if (chip->driver_data & PCA_PCAL) { 369 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 370 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 371 PCAL9xxx_BANK_IRQ_STAT; 372 } 373 374 return chip->check_reg(chip, reg, bank); 375 } 376 377 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 378 { 379 struct pca953x_chip *chip = dev_get_drvdata(dev); 380 u32 bank; 381 382 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 383 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 384 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 385 } else { 386 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 387 PCA953x_BANK_CONFIG; 388 } 389 390 if (chip->driver_data & PCA_PCAL) 391 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 392 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 393 394 return chip->check_reg(chip, reg, bank); 395 } 396 397 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 398 { 399 struct pca953x_chip *chip = dev_get_drvdata(dev); 400 u32 bank; 401 402 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 403 bank = PCA957x_BANK_INPUT; 404 else 405 bank = PCA953x_BANK_INPUT; 406 407 if (chip->driver_data & PCA_PCAL) 408 bank |= PCAL9xxx_BANK_IRQ_STAT; 409 410 return chip->check_reg(chip, reg, bank); 411 } 412 413 static const struct regmap_config pca953x_i2c_regmap = { 414 .reg_bits = 8, 415 .val_bits = 8, 416 417 .use_single_read = true, 418 .use_single_write = true, 419 420 .readable_reg = pca953x_readable_register, 421 .writeable_reg = pca953x_writeable_register, 422 .volatile_reg = pca953x_volatile_register, 423 424 .disable_locking = true, 425 .cache_type = REGCACHE_MAPLE, 426 .max_register = 0x7f, 427 }; 428 429 static const struct regmap_config pca953x_ai_i2c_regmap = { 430 .reg_bits = 8, 431 .val_bits = 8, 432 433 .read_flag_mask = REG_ADDR_AI, 434 .write_flag_mask = REG_ADDR_AI, 435 436 .readable_reg = pca953x_readable_register, 437 .writeable_reg = pca953x_writeable_register, 438 .volatile_reg = pca953x_volatile_register, 439 440 .disable_locking = true, 441 .cache_type = REGCACHE_MAPLE, 442 .max_register = 0x7f, 443 }; 444 445 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 446 { 447 int bank_shift = pca953x_bank_shift(chip); 448 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 449 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 450 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 451 452 return regaddr; 453 } 454 455 /* 456 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 457 * fit within the bit shifting scheme used for other devices. 458 */ 459 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 460 { 461 int addr; 462 int pinctrl; 463 464 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 465 466 switch (reg) { 467 case PCAL953X_OUT_STRENGTH: 468 case PCAL953X_IN_LATCH: 469 case PCAL953X_PULL_EN: 470 case PCAL953X_PULL_SEL: 471 case PCAL953X_INT_MASK: 472 case PCAL953X_INT_STAT: 473 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 474 break; 475 case PCAL6524_INT_EDGE: 476 case PCAL6524_INT_CLR: 477 case PCAL6524_IN_STATUS: 478 case PCAL6524_OUT_INDCONF: 479 case PCAL6524_DEBOUNCE: 480 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 481 break; 482 default: 483 pinctrl = 0; 484 break; 485 } 486 487 return pinctrl + addr + (off / BANK_SZ); 488 } 489 490 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 491 { 492 u8 regaddr = chip->recalc_addr(chip, reg, 0); 493 u8 value[MAX_BANK]; 494 int i, ret; 495 496 for (i = 0; i < NBANK(chip); i++) 497 value[i] = bitmap_get_value8(val, i * BANK_SZ); 498 499 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 500 if (ret < 0) { 501 dev_err(&chip->client->dev, "failed writing register: %d\n", ret); 502 return ret; 503 } 504 505 return 0; 506 } 507 508 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 509 { 510 u8 regaddr = chip->recalc_addr(chip, reg, 0); 511 u8 value[MAX_BANK]; 512 int i, ret; 513 514 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 515 if (ret < 0) { 516 dev_err(&chip->client->dev, "failed reading register: %d\n", ret); 517 return ret; 518 } 519 520 for (i = 0; i < NBANK(chip); i++) 521 bitmap_set_value8(val, value[i], i * BANK_SZ); 522 523 return 0; 524 } 525 526 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 527 { 528 struct pca953x_chip *chip = gpiochip_get_data(gc); 529 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 530 u8 bit = BIT(off % BANK_SZ); 531 532 guard(mutex)(&chip->i2c_lock); 533 534 return regmap_write_bits(chip->regmap, dirreg, bit, bit); 535 } 536 537 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 538 unsigned off, int val) 539 { 540 struct pca953x_chip *chip = gpiochip_get_data(gc); 541 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 542 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 543 u8 bit = BIT(off % BANK_SZ); 544 int ret; 545 546 guard(mutex)(&chip->i2c_lock); 547 548 /* set output level */ 549 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 550 if (ret) 551 return ret; 552 553 /* then direction */ 554 return regmap_write_bits(chip->regmap, dirreg, bit, 0); 555 } 556 557 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 558 { 559 struct pca953x_chip *chip = gpiochip_get_data(gc); 560 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 561 u8 bit = BIT(off % BANK_SZ); 562 u32 reg_val; 563 int ret; 564 565 scoped_guard(mutex, &chip->i2c_lock) 566 ret = regmap_read(chip->regmap, inreg, ®_val); 567 if (ret < 0) 568 return ret; 569 570 return !!(reg_val & bit); 571 } 572 573 static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 574 int val) 575 { 576 struct pca953x_chip *chip = gpiochip_get_data(gc); 577 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 578 u8 bit = BIT(off % BANK_SZ); 579 580 guard(mutex)(&chip->i2c_lock); 581 582 return regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 583 } 584 585 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 586 { 587 struct pca953x_chip *chip = gpiochip_get_data(gc); 588 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 589 u8 bit = BIT(off % BANK_SZ); 590 u32 reg_val; 591 int ret; 592 593 scoped_guard(mutex, &chip->i2c_lock) 594 ret = regmap_read(chip->regmap, dirreg, ®_val); 595 if (ret < 0) 596 return ret; 597 598 if (reg_val & bit) 599 return GPIO_LINE_DIRECTION_IN; 600 601 return GPIO_LINE_DIRECTION_OUT; 602 } 603 604 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 605 unsigned long *mask, unsigned long *bits) 606 { 607 struct pca953x_chip *chip = gpiochip_get_data(gc); 608 DECLARE_BITMAP(reg_val, MAX_LINE); 609 int ret; 610 611 scoped_guard(mutex, &chip->i2c_lock) 612 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 613 if (ret) 614 return ret; 615 616 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 617 return 0; 618 } 619 620 static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 621 unsigned long *mask, unsigned long *bits) 622 { 623 struct pca953x_chip *chip = gpiochip_get_data(gc); 624 DECLARE_BITMAP(reg_val, MAX_LINE); 625 int ret; 626 627 guard(mutex)(&chip->i2c_lock); 628 629 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 630 if (ret) 631 return ret; 632 633 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 634 635 return pca953x_write_regs(chip, chip->regs->output, reg_val); 636 } 637 638 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 639 unsigned int offset, 640 unsigned long config) 641 { 642 enum pin_config_param param = pinconf_to_config_param(config); 643 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 644 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 645 u8 bit = BIT(offset % BANK_SZ); 646 int ret; 647 648 /* 649 * pull-up/pull-down configuration requires PCAL extended 650 * registers 651 */ 652 if (!(chip->driver_data & PCA_PCAL)) 653 return -ENOTSUPP; 654 655 guard(mutex)(&chip->i2c_lock); 656 657 /* Configure pull-up/pull-down */ 658 if (param == PIN_CONFIG_BIAS_PULL_UP) 659 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 660 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 661 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 662 else 663 ret = 0; 664 if (ret) 665 return ret; 666 667 /* Disable/Enable pull-up/pull-down */ 668 if (param == PIN_CONFIG_BIAS_DISABLE) 669 return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 670 else 671 return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 672 } 673 674 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 675 unsigned long config) 676 { 677 struct pca953x_chip *chip = gpiochip_get_data(gc); 678 679 switch (pinconf_to_config_param(config)) { 680 case PIN_CONFIG_BIAS_PULL_UP: 681 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 682 case PIN_CONFIG_BIAS_PULL_DOWN: 683 case PIN_CONFIG_BIAS_DISABLE: 684 return pca953x_gpio_set_pull_up_down(chip, offset, config); 685 default: 686 return -ENOTSUPP; 687 } 688 } 689 690 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 691 { 692 struct gpio_chip *gc = &chip->gpio_chip; 693 694 gc->direction_input = pca953x_gpio_direction_input; 695 gc->direction_output = pca953x_gpio_direction_output; 696 gc->get = pca953x_gpio_get_value; 697 gc->set_rv = pca953x_gpio_set_value; 698 gc->get_direction = pca953x_gpio_get_direction; 699 gc->get_multiple = pca953x_gpio_get_multiple; 700 gc->set_multiple_rv = pca953x_gpio_set_multiple; 701 gc->set_config = pca953x_gpio_set_config; 702 gc->can_sleep = true; 703 704 gc->base = chip->gpio_start; 705 gc->ngpio = gpios; 706 gc->label = dev_name(&chip->client->dev); 707 gc->parent = &chip->client->dev; 708 gc->owner = THIS_MODULE; 709 } 710 711 #ifdef CONFIG_GPIO_PCA953X_IRQ 712 static void pca953x_irq_mask(struct irq_data *d) 713 { 714 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 715 struct pca953x_chip *chip = gpiochip_get_data(gc); 716 irq_hw_number_t hwirq = irqd_to_hwirq(d); 717 718 clear_bit(hwirq, chip->irq_mask); 719 gpiochip_disable_irq(gc, hwirq); 720 } 721 722 static void pca953x_irq_unmask(struct irq_data *d) 723 { 724 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 725 struct pca953x_chip *chip = gpiochip_get_data(gc); 726 irq_hw_number_t hwirq = irqd_to_hwirq(d); 727 728 gpiochip_enable_irq(gc, hwirq); 729 set_bit(hwirq, chip->irq_mask); 730 } 731 732 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 733 { 734 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 735 struct pca953x_chip *chip = gpiochip_get_data(gc); 736 737 if (on) 738 atomic_inc(&chip->wakeup_path); 739 else 740 atomic_dec(&chip->wakeup_path); 741 742 return irq_set_irq_wake(chip->client->irq, on); 743 } 744 745 static void pca953x_irq_bus_lock(struct irq_data *d) 746 { 747 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 748 struct pca953x_chip *chip = gpiochip_get_data(gc); 749 750 mutex_lock(&chip->irq_lock); 751 } 752 753 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 754 { 755 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 756 struct pca953x_chip *chip = gpiochip_get_data(gc); 757 DECLARE_BITMAP(irq_mask, MAX_LINE); 758 DECLARE_BITMAP(reg_direction, MAX_LINE); 759 int level; 760 761 if (chip->driver_data & PCA_PCAL) { 762 guard(mutex)(&chip->i2c_lock); 763 764 /* Enable latch on interrupt-enabled inputs */ 765 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 766 767 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 768 769 /* Unmask enabled interrupts */ 770 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 771 } 772 773 /* Switch direction to input if needed */ 774 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 775 776 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 777 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 778 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 779 780 /* Look for any newly setup interrupt */ 781 for_each_set_bit(level, irq_mask, gc->ngpio) 782 pca953x_gpio_direction_input(&chip->gpio_chip, level); 783 784 mutex_unlock(&chip->irq_lock); 785 } 786 787 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 788 { 789 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 790 struct pca953x_chip *chip = gpiochip_get_data(gc); 791 struct device *dev = &chip->client->dev; 792 irq_hw_number_t hwirq = irqd_to_hwirq(d); 793 794 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 795 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 796 return -EINVAL; 797 } 798 799 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 800 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 801 802 return 0; 803 } 804 805 static void pca953x_irq_shutdown(struct irq_data *d) 806 { 807 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 808 struct pca953x_chip *chip = gpiochip_get_data(gc); 809 irq_hw_number_t hwirq = irqd_to_hwirq(d); 810 811 clear_bit(hwirq, chip->irq_trig_raise); 812 clear_bit(hwirq, chip->irq_trig_fall); 813 } 814 815 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 816 { 817 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 818 819 seq_puts(p, dev_name(gc->parent)); 820 } 821 822 static const struct irq_chip pca953x_irq_chip = { 823 .irq_mask = pca953x_irq_mask, 824 .irq_unmask = pca953x_irq_unmask, 825 .irq_set_wake = pca953x_irq_set_wake, 826 .irq_bus_lock = pca953x_irq_bus_lock, 827 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 828 .irq_set_type = pca953x_irq_set_type, 829 .irq_shutdown = pca953x_irq_shutdown, 830 .irq_print_chip = pca953x_irq_print_chip, 831 .flags = IRQCHIP_IMMUTABLE, 832 GPIOCHIP_IRQ_RESOURCE_HELPERS, 833 }; 834 835 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 836 { 837 struct gpio_chip *gc = &chip->gpio_chip; 838 DECLARE_BITMAP(reg_direction, MAX_LINE); 839 DECLARE_BITMAP(old_stat, MAX_LINE); 840 DECLARE_BITMAP(cur_stat, MAX_LINE); 841 DECLARE_BITMAP(new_stat, MAX_LINE); 842 DECLARE_BITMAP(trigger, MAX_LINE); 843 int ret; 844 845 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 846 if (ret) 847 return false; 848 849 /* Remove output pins from the equation */ 850 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 851 852 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 853 854 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 855 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 856 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 857 858 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 859 860 if (bitmap_empty(trigger, gc->ngpio)) 861 return false; 862 863 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 864 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 865 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 866 bitmap_and(pending, new_stat, trigger, gc->ngpio); 867 868 return !bitmap_empty(pending, gc->ngpio); 869 } 870 871 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 872 { 873 struct pca953x_chip *chip = devid; 874 struct gpio_chip *gc = &chip->gpio_chip; 875 DECLARE_BITMAP(pending, MAX_LINE); 876 int level; 877 bool ret; 878 879 bitmap_zero(pending, MAX_LINE); 880 881 scoped_guard(mutex, &chip->i2c_lock) 882 ret = pca953x_irq_pending(chip, pending); 883 if (ret) { 884 ret = 0; 885 886 for_each_set_bit(level, pending, gc->ngpio) { 887 int nested_irq = irq_find_mapping(gc->irq.domain, level); 888 889 if (unlikely(nested_irq <= 0)) { 890 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 891 continue; 892 } 893 894 handle_nested_irq(nested_irq); 895 ret = 1; 896 } 897 } 898 899 return IRQ_RETVAL(ret); 900 } 901 902 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 903 { 904 struct i2c_client *client = chip->client; 905 struct device *dev = &client->dev; 906 DECLARE_BITMAP(reg_direction, MAX_LINE); 907 DECLARE_BITMAP(irq_stat, MAX_LINE); 908 struct gpio_chip *gc = &chip->gpio_chip; 909 struct gpio_irq_chip *girq; 910 int ret; 911 912 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 913 ret = pca953x_acpi_get_irq(dev); 914 if (ret > 0) 915 client->irq = ret; 916 } 917 918 if (!client->irq) 919 return 0; 920 921 if (irq_base == -1) 922 return 0; 923 924 if (!(chip->driver_data & PCA_INT)) 925 return 0; 926 927 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 928 if (ret) 929 return ret; 930 931 /* 932 * There is no way to know which GPIO line generated the 933 * interrupt. We have to rely on the previous read for 934 * this purpose. 935 */ 936 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 937 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 938 mutex_init(&chip->irq_lock); 939 940 girq = &chip->gpio_chip.irq; 941 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 942 /* This will let us handle the parent IRQ in the driver */ 943 girq->parent_handler = NULL; 944 girq->num_parents = 0; 945 girq->parents = NULL; 946 girq->default_type = IRQ_TYPE_NONE; 947 girq->handler = handle_simple_irq; 948 girq->threaded = true; 949 girq->first = irq_base; /* FIXME: get rid of this */ 950 951 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 952 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 953 chip); 954 if (ret) 955 return dev_err_probe(dev, client->irq, "failed to request irq\n"); 956 957 return 0; 958 } 959 960 #else /* CONFIG_GPIO_PCA953X_IRQ */ 961 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 962 { 963 struct i2c_client *client = chip->client; 964 struct device *dev = &client->dev; 965 966 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 967 dev_warn(dev, "interrupt support not compiled in\n"); 968 969 return 0; 970 } 971 #endif 972 973 static int device_pca95xx_init(struct pca953x_chip *chip) 974 { 975 DECLARE_BITMAP(val, MAX_LINE); 976 u8 regaddr; 977 int ret; 978 979 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 980 ret = regcache_sync_region(chip->regmap, regaddr, 981 regaddr + NBANK(chip) - 1); 982 if (ret) 983 return ret; 984 985 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 986 ret = regcache_sync_region(chip->regmap, regaddr, 987 regaddr + NBANK(chip) - 1); 988 if (ret) 989 return ret; 990 991 /* clear polarity inversion */ 992 bitmap_zero(val, MAX_LINE); 993 994 return pca953x_write_regs(chip, chip->regs->invert, val); 995 } 996 997 static int device_pca957x_init(struct pca953x_chip *chip) 998 { 999 DECLARE_BITMAP(val, MAX_LINE); 1000 unsigned int i; 1001 int ret; 1002 1003 ret = device_pca95xx_init(chip); 1004 if (ret) 1005 return ret; 1006 1007 /* To enable register 6, 7 to control pull up and pull down */ 1008 for (i = 0; i < NBANK(chip); i++) 1009 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1010 1011 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1012 } 1013 1014 static void pca953x_disable_regulator(void *reg) 1015 { 1016 regulator_disable(reg); 1017 } 1018 1019 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1020 { 1021 struct device *dev = &chip->client->dev; 1022 struct regulator *reg = chip->regulator; 1023 int ret; 1024 1025 reg = devm_regulator_get(dev, "vcc"); 1026 if (IS_ERR(reg)) 1027 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1028 1029 ret = regulator_enable(reg); 1030 if (ret) 1031 return dev_err_probe(dev, ret, "reg en err\n"); 1032 1033 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1034 if (ret) 1035 return ret; 1036 1037 chip->regulator = reg; 1038 return 0; 1039 } 1040 1041 static int pca953x_probe(struct i2c_client *client) 1042 { 1043 struct device *dev = &client->dev; 1044 struct pca953x_platform_data *pdata; 1045 struct pca953x_chip *chip; 1046 int irq_base; 1047 int ret; 1048 const struct regmap_config *regmap_config; 1049 1050 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1051 if (chip == NULL) 1052 return -ENOMEM; 1053 1054 pdata = dev_get_platdata(dev); 1055 if (pdata) { 1056 irq_base = pdata->irq_base; 1057 chip->gpio_start = pdata->gpio_base; 1058 } else { 1059 struct gpio_desc *reset_gpio; 1060 1061 chip->gpio_start = -1; 1062 irq_base = 0; 1063 1064 /* 1065 * See if we need to de-assert a reset pin. 1066 * 1067 * There is no known ACPI-enabled platforms that are 1068 * using "reset" GPIO. Otherwise any of those platform 1069 * must use _DSD method with corresponding property. 1070 */ 1071 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1072 if (IS_ERR(reset_gpio)) 1073 return dev_err_probe(dev, PTR_ERR(reset_gpio), 1074 "Failed to get reset gpio\n"); 1075 } 1076 1077 chip->client = client; 1078 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1079 if (!chip->driver_data) 1080 return -ENODEV; 1081 1082 ret = pca953x_get_and_enable_regulator(chip); 1083 if (ret) 1084 return ret; 1085 1086 i2c_set_clientdata(client, chip); 1087 1088 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1089 1090 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1091 dev_info(dev, "using AI\n"); 1092 regmap_config = &pca953x_ai_i2c_regmap; 1093 } else { 1094 dev_info(dev, "using no AI\n"); 1095 regmap_config = &pca953x_i2c_regmap; 1096 } 1097 1098 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { 1099 chip->recalc_addr = pcal6534_recalc_addr; 1100 chip->check_reg = pcal6534_check_register; 1101 } else { 1102 chip->recalc_addr = pca953x_recalc_addr; 1103 chip->check_reg = pca953x_check_register; 1104 } 1105 1106 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1107 if (IS_ERR(chip->regmap)) 1108 return PTR_ERR(chip->regmap); 1109 1110 regcache_mark_dirty(chip->regmap); 1111 1112 mutex_init(&chip->i2c_lock); 1113 /* 1114 * In case we have an i2c-mux controlled by a GPIO provided by an 1115 * expander using the same driver higher on the device tree, read the 1116 * i2c adapter nesting depth and use the retrieved value as lockdep 1117 * subclass for chip->i2c_lock. 1118 * 1119 * REVISIT: This solution is not complete. It protects us from lockdep 1120 * false positives when the expander controlling the i2c-mux is on 1121 * a different level on the device tree, but not when it's on the same 1122 * level on a different branch (in which case the subclass number 1123 * would be the same). 1124 * 1125 * TODO: Once a correct solution is developed, a similar fix should be 1126 * applied to all other i2c-controlled GPIO expanders (and potentially 1127 * regmap-i2c). 1128 */ 1129 lockdep_set_subclass(&chip->i2c_lock, 1130 i2c_adapter_depth(client->adapter)); 1131 1132 /* initialize cached registers from their original values. 1133 * we can't share this chip with another i2c master. 1134 */ 1135 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1136 chip->regs = &pca957x_regs; 1137 ret = device_pca957x_init(chip); 1138 } else { 1139 chip->regs = &pca953x_regs; 1140 ret = device_pca95xx_init(chip); 1141 } 1142 if (ret) 1143 return ret; 1144 1145 ret = pca953x_irq_setup(chip, irq_base); 1146 if (ret) 1147 return ret; 1148 1149 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1150 } 1151 1152 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1153 { 1154 struct device *dev = &chip->client->dev; 1155 int ret; 1156 u8 regaddr; 1157 1158 /* 1159 * The ordering between direction and output is important, 1160 * sync these registers first and only then sync the rest. 1161 */ 1162 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1163 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1164 if (ret) { 1165 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1166 return ret; 1167 } 1168 1169 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1170 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1171 if (ret) { 1172 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1173 return ret; 1174 } 1175 1176 #ifdef CONFIG_GPIO_PCA953X_IRQ 1177 if (chip->driver_data & PCA_PCAL) { 1178 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1179 ret = regcache_sync_region(chip->regmap, regaddr, 1180 regaddr + NBANK(chip) - 1); 1181 if (ret) { 1182 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1183 ret); 1184 return ret; 1185 } 1186 1187 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1188 ret = regcache_sync_region(chip->regmap, regaddr, 1189 regaddr + NBANK(chip) - 1); 1190 if (ret) { 1191 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1192 ret); 1193 return ret; 1194 } 1195 } 1196 #endif 1197 1198 return 0; 1199 } 1200 1201 static int pca953x_restore_context(struct pca953x_chip *chip) 1202 { 1203 int ret; 1204 1205 guard(mutex)(&chip->i2c_lock); 1206 1207 regcache_cache_only(chip->regmap, false); 1208 regcache_mark_dirty(chip->regmap); 1209 ret = pca953x_regcache_sync(chip); 1210 if (ret) 1211 return ret; 1212 1213 return regcache_sync(chip->regmap); 1214 } 1215 1216 static void pca953x_save_context(struct pca953x_chip *chip) 1217 { 1218 guard(mutex)(&chip->i2c_lock); 1219 regcache_cache_only(chip->regmap, true); 1220 } 1221 1222 static int pca953x_suspend(struct device *dev) 1223 { 1224 struct pca953x_chip *chip = dev_get_drvdata(dev); 1225 1226 pca953x_save_context(chip); 1227 1228 if (atomic_read(&chip->wakeup_path)) 1229 device_set_wakeup_path(dev); 1230 else 1231 regulator_disable(chip->regulator); 1232 1233 return 0; 1234 } 1235 1236 static int pca953x_resume(struct device *dev) 1237 { 1238 struct pca953x_chip *chip = dev_get_drvdata(dev); 1239 int ret; 1240 1241 if (!atomic_read(&chip->wakeup_path)) { 1242 ret = regulator_enable(chip->regulator); 1243 if (ret) { 1244 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1245 return 0; 1246 } 1247 } 1248 1249 ret = pca953x_restore_context(chip); 1250 if (ret) 1251 dev_err(dev, "Failed to restore register map: %d\n", ret); 1252 1253 return ret; 1254 } 1255 1256 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1257 1258 /* convenience to stop overlong match-table lines */ 1259 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1260 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1261 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1262 1263 static const struct of_device_id pca953x_dt_ids[] = { 1264 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1265 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1266 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1267 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1268 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1269 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1270 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1271 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1272 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1273 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1274 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1275 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1276 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1277 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1278 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1279 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1280 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1281 1282 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1283 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1284 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1285 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1286 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1287 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1288 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1289 1290 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1291 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1292 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1293 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1294 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1295 1296 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1297 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1298 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1299 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1300 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1301 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1302 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1303 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1304 1305 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1306 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1307 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1308 1309 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1310 { } 1311 }; 1312 1313 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1314 1315 static struct i2c_driver pca953x_driver = { 1316 .driver = { 1317 .name = "pca953x", 1318 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1319 .of_match_table = pca953x_dt_ids, 1320 .acpi_match_table = pca953x_acpi_ids, 1321 }, 1322 .probe = pca953x_probe, 1323 .id_table = pca953x_id, 1324 }; 1325 1326 static int __init pca953x_init(void) 1327 { 1328 return i2c_add_driver(&pca953x_driver); 1329 } 1330 /* register after i2c postcore initcall and before 1331 * subsys initcalls that may rely on these GPIOs 1332 */ 1333 subsys_initcall(pca953x_init); 1334 1335 static void __exit pca953x_exit(void) 1336 { 1337 i2c_del_driver(&pca953x_driver); 1338 } 1339 module_exit(pca953x_exit); 1340 1341 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1342 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1343 MODULE_LICENSE("GPL"); 1344