1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/seq_file.h> 27 #include <linux/slab.h> 28 29 #include <linux/gpio/consumer.h> 30 #include <linux/gpio/driver.h> 31 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 #include <linux/platform_data/pca953x.h> 35 36 #define PCA953X_INPUT 0x00 37 #define PCA953X_OUTPUT 0x01 38 #define PCA953X_INVERT 0x02 39 #define PCA953X_DIRECTION 0x03 40 41 #define REG_ADDR_MASK GENMASK(5, 0) 42 #define REG_ADDR_EXT BIT(6) 43 #define REG_ADDR_AI BIT(7) 44 45 #define PCA957X_IN 0x00 46 #define PCA957X_INVRT 0x01 47 #define PCA957X_BKEN 0x02 48 #define PCA957X_PUPD 0x03 49 #define PCA957X_CFG 0x04 50 #define PCA957X_OUT 0x05 51 #define PCA957X_MSK 0x06 52 #define PCA957X_INTS 0x07 53 54 #define PCAL953X_OUT_STRENGTH 0x20 55 #define PCAL953X_IN_LATCH 0x22 56 #define PCAL953X_PULL_EN 0x23 57 #define PCAL953X_PULL_SEL 0x24 58 #define PCAL953X_INT_MASK 0x25 59 #define PCAL953X_INT_STAT 0x26 60 #define PCAL953X_OUT_CONF 0x27 61 62 #define PCAL6524_INT_EDGE 0x28 63 #define PCAL6524_INT_CLR 0x2a 64 #define PCAL6524_IN_STATUS 0x2b 65 #define PCAL6524_OUT_INDCONF 0x2c 66 #define PCAL6524_DEBOUNCE 0x2d 67 68 #define PCA_GPIO_MASK GENMASK(7, 0) 69 70 #define PCAL_GPIO_MASK GENMASK(4, 0) 71 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 72 73 #define PCA_INT BIT(8) 74 #define PCA_PCAL BIT(9) 75 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 76 #define PCA953X_TYPE BIT(12) 77 #define PCA957X_TYPE BIT(13) 78 #define PCAL653X_TYPE BIT(14) 79 #define PCA_TYPE_MASK GENMASK(15, 12) 80 81 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 82 83 static const struct i2c_device_id pca953x_id[] = { 84 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 85 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 86 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 87 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 88 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 89 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 90 { "pca9536", 4 | PCA953X_TYPE, }, 91 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 92 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 93 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 94 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 95 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 96 { "pca9556", 8 | PCA953X_TYPE, }, 97 { "pca9557", 8 | PCA953X_TYPE, }, 98 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 99 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 100 { "pca9698", 40 | PCA953X_TYPE, }, 101 102 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 103 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 104 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 105 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 106 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 107 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 108 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 109 110 { "max7310", 8 | PCA953X_TYPE, }, 111 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 112 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 113 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 114 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 115 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 116 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 117 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 118 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 119 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, }, 120 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 121 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 122 { "xra1202", 8 | PCA953X_TYPE }, 123 { } 124 }; 125 MODULE_DEVICE_TABLE(i2c, pca953x_id); 126 127 #ifdef CONFIG_GPIO_PCA953X_IRQ 128 129 #include <linux/acpi.h> 130 #include <linux/dmi.h> 131 132 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 133 134 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 135 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 136 { } 137 }; 138 139 static int pca953x_acpi_get_irq(struct device *dev) 140 { 141 int ret; 142 143 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 144 if (ret) 145 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 146 147 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 148 if (ret < 0) 149 return ret; 150 151 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 152 return ret; 153 } 154 155 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 156 { 157 /* 158 * On Intel Galileo Gen 2 board the IRQ pin of one of 159 * the I²C GPIO expanders, which has GpioInt() resource, 160 * is provided as an absolute number instead of being 161 * relative. Since first controller (gpio-sch.c) and 162 * second (gpio-dwapb.c) are at the fixed bases, we may 163 * safely refer to the number in the global space to get 164 * an IRQ out of it. 165 */ 166 .matches = { 167 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 168 }, 169 }, 170 {} 171 }; 172 #endif 173 174 static const struct acpi_device_id pca953x_acpi_ids[] = { 175 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 176 { } 177 }; 178 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 179 180 #define MAX_BANK 5 181 #define BANK_SZ 8 182 #define MAX_LINE (MAX_BANK * BANK_SZ) 183 184 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 185 186 struct pca953x_reg_config { 187 int direction; 188 int output; 189 int input; 190 int invert; 191 }; 192 193 static const struct pca953x_reg_config pca953x_regs = { 194 .direction = PCA953X_DIRECTION, 195 .output = PCA953X_OUTPUT, 196 .input = PCA953X_INPUT, 197 .invert = PCA953X_INVERT, 198 }; 199 200 static const struct pca953x_reg_config pca957x_regs = { 201 .direction = PCA957X_CFG, 202 .output = PCA957X_OUT, 203 .input = PCA957X_IN, 204 .invert = PCA957X_INVRT, 205 }; 206 207 struct pca953x_chip { 208 unsigned gpio_start; 209 struct mutex i2c_lock; 210 struct regmap *regmap; 211 212 #ifdef CONFIG_GPIO_PCA953X_IRQ 213 struct mutex irq_lock; 214 DECLARE_BITMAP(irq_mask, MAX_LINE); 215 DECLARE_BITMAP(irq_stat, MAX_LINE); 216 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 217 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 218 #endif 219 atomic_t wakeup_path; 220 221 struct i2c_client *client; 222 struct gpio_chip gpio_chip; 223 unsigned long driver_data; 224 struct regulator *regulator; 225 226 const struct pca953x_reg_config *regs; 227 228 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 229 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 230 u32 checkbank); 231 }; 232 233 static int pca953x_bank_shift(struct pca953x_chip *chip) 234 { 235 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 236 } 237 238 #define PCA953x_BANK_INPUT BIT(0) 239 #define PCA953x_BANK_OUTPUT BIT(1) 240 #define PCA953x_BANK_POLARITY BIT(2) 241 #define PCA953x_BANK_CONFIG BIT(3) 242 243 #define PCA957x_BANK_INPUT BIT(0) 244 #define PCA957x_BANK_POLARITY BIT(1) 245 #define PCA957x_BANK_BUSHOLD BIT(2) 246 #define PCA957x_BANK_CONFIG BIT(4) 247 #define PCA957x_BANK_OUTPUT BIT(5) 248 249 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 250 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 251 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 252 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 253 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 254 255 /* 256 * We care about the following registers: 257 * - Standard set, below 0x40, each port can be replicated up to 8 times 258 * - PCA953x standard 259 * Input port 0x00 + 0 * bank_size R 260 * Output port 0x00 + 1 * bank_size RW 261 * Polarity Inversion port 0x00 + 2 * bank_size RW 262 * Configuration port 0x00 + 3 * bank_size RW 263 * - PCA957x with mixed up registers 264 * Input port 0x00 + 0 * bank_size R 265 * Polarity Inversion port 0x00 + 1 * bank_size RW 266 * Bus hold port 0x00 + 2 * bank_size RW 267 * Configuration port 0x00 + 4 * bank_size RW 268 * Output port 0x00 + 5 * bank_size RW 269 * 270 * - Extended set, above 0x40, often chip specific. 271 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 272 * Input latch register 0x40 + 2 * bank_size RW 273 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 274 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 275 * Interrupt mask register 0x40 + 5 * bank_size RW 276 * Interrupt status register 0x40 + 6 * bank_size R 277 * 278 * - Registers with bit 0x80 set, the AI bit 279 * The bit is cleared and the registers fall into one of the 280 * categories above. 281 */ 282 283 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 284 u32 checkbank) 285 { 286 int bank_shift = pca953x_bank_shift(chip); 287 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 288 int offset = reg & (BIT(bank_shift) - 1); 289 290 /* Special PCAL extended register check. */ 291 if (reg & REG_ADDR_EXT) { 292 if (!(chip->driver_data & PCA_PCAL)) 293 return false; 294 bank += 8; 295 } 296 297 /* Register is not in the matching bank. */ 298 if (!(BIT(bank) & checkbank)) 299 return false; 300 301 /* Register is not within allowed range of bank. */ 302 if (offset >= NBANK(chip)) 303 return false; 304 305 return true; 306 } 307 308 /* 309 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 310 * same register layout as the PCAL6524, the spacing of the registers has been 311 * fundamentally altered by compacting them and thus does not obey the same 312 * rules, including being able to use bit shifting to determine bank. These 313 * chips hence need special handling here. 314 */ 315 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 316 u32 checkbank) 317 { 318 int bank_shift; 319 int bank; 320 int offset; 321 322 if (reg >= 0x54) { 323 /* 324 * Handle lack of reserved registers after output port 325 * configuration register to form a bank. 326 */ 327 reg -= 0x54; 328 bank_shift = 16; 329 } else if (reg >= 0x30) { 330 /* 331 * Reserved block between 14h and 2Fh does not align on 332 * expected bank boundaries like other devices. 333 */ 334 reg -= 0x30; 335 bank_shift = 8; 336 } else { 337 bank_shift = 0; 338 } 339 340 bank = bank_shift + reg / NBANK(chip); 341 offset = reg % NBANK(chip); 342 343 /* Register is not in the matching bank. */ 344 if (!(BIT(bank) & checkbank)) 345 return false; 346 347 /* Register is not within allowed range of bank. */ 348 if (offset >= NBANK(chip)) 349 return false; 350 351 return true; 352 } 353 354 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 355 { 356 struct pca953x_chip *chip = dev_get_drvdata(dev); 357 u32 bank; 358 359 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 360 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 361 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 362 PCA957x_BANK_BUSHOLD; 363 } else { 364 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 365 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 366 } 367 368 if (chip->driver_data & PCA_PCAL) { 369 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 370 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 371 PCAL9xxx_BANK_IRQ_STAT; 372 } 373 374 return chip->check_reg(chip, reg, bank); 375 } 376 377 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 378 { 379 struct pca953x_chip *chip = dev_get_drvdata(dev); 380 u32 bank; 381 382 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 383 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 384 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 385 } else { 386 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 387 PCA953x_BANK_CONFIG; 388 } 389 390 if (chip->driver_data & PCA_PCAL) 391 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 392 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 393 394 return chip->check_reg(chip, reg, bank); 395 } 396 397 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 398 { 399 struct pca953x_chip *chip = dev_get_drvdata(dev); 400 u32 bank; 401 402 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) 403 bank = PCA957x_BANK_INPUT; 404 else 405 bank = PCA953x_BANK_INPUT; 406 407 if (chip->driver_data & PCA_PCAL) 408 bank |= PCAL9xxx_BANK_IRQ_STAT; 409 410 return chip->check_reg(chip, reg, bank); 411 } 412 413 static const struct regmap_config pca953x_i2c_regmap = { 414 .reg_bits = 8, 415 .val_bits = 8, 416 417 .use_single_read = true, 418 .use_single_write = true, 419 420 .readable_reg = pca953x_readable_register, 421 .writeable_reg = pca953x_writeable_register, 422 .volatile_reg = pca953x_volatile_register, 423 424 .disable_locking = true, 425 .cache_type = REGCACHE_MAPLE, 426 .max_register = 0x7f, 427 }; 428 429 static const struct regmap_config pca953x_ai_i2c_regmap = { 430 .reg_bits = 8, 431 .val_bits = 8, 432 433 .read_flag_mask = REG_ADDR_AI, 434 .write_flag_mask = REG_ADDR_AI, 435 436 .readable_reg = pca953x_readable_register, 437 .writeable_reg = pca953x_writeable_register, 438 .volatile_reg = pca953x_volatile_register, 439 440 .disable_locking = true, 441 .cache_type = REGCACHE_MAPLE, 442 .max_register = 0x7f, 443 }; 444 445 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 446 { 447 int bank_shift = pca953x_bank_shift(chip); 448 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 449 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 450 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 451 452 return regaddr; 453 } 454 455 /* 456 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 457 * fit within the bit shifting scheme used for other devices. 458 */ 459 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 460 { 461 int addr; 462 int pinctrl; 463 464 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 465 466 switch (reg) { 467 case PCAL953X_OUT_STRENGTH: 468 case PCAL953X_IN_LATCH: 469 case PCAL953X_PULL_EN: 470 case PCAL953X_PULL_SEL: 471 case PCAL953X_INT_MASK: 472 case PCAL953X_INT_STAT: 473 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 474 break; 475 case PCAL6524_INT_EDGE: 476 case PCAL6524_INT_CLR: 477 case PCAL6524_IN_STATUS: 478 case PCAL6524_OUT_INDCONF: 479 case PCAL6524_DEBOUNCE: 480 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 481 break; 482 default: 483 pinctrl = 0; 484 break; 485 } 486 487 return pinctrl + addr + (off / BANK_SZ); 488 } 489 490 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 491 { 492 u8 regaddr = chip->recalc_addr(chip, reg, 0); 493 u8 value[MAX_BANK]; 494 int i, ret; 495 496 for (i = 0; i < NBANK(chip); i++) 497 value[i] = bitmap_get_value8(val, i * BANK_SZ); 498 499 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 500 if (ret < 0) { 501 dev_err(&chip->client->dev, "failed writing register\n"); 502 return ret; 503 } 504 505 return 0; 506 } 507 508 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 509 { 510 u8 regaddr = chip->recalc_addr(chip, reg, 0); 511 u8 value[MAX_BANK]; 512 int i, ret; 513 514 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 515 if (ret < 0) { 516 dev_err(&chip->client->dev, "failed reading register\n"); 517 return ret; 518 } 519 520 for (i = 0; i < NBANK(chip); i++) 521 bitmap_set_value8(val, value[i], i * BANK_SZ); 522 523 return 0; 524 } 525 526 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 527 { 528 struct pca953x_chip *chip = gpiochip_get_data(gc); 529 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 530 u8 bit = BIT(off % BANK_SZ); 531 532 guard(mutex)(&chip->i2c_lock); 533 534 return regmap_write_bits(chip->regmap, dirreg, bit, bit); 535 } 536 537 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 538 unsigned off, int val) 539 { 540 struct pca953x_chip *chip = gpiochip_get_data(gc); 541 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 542 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 543 u8 bit = BIT(off % BANK_SZ); 544 int ret; 545 546 guard(mutex)(&chip->i2c_lock); 547 548 /* set output level */ 549 ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 550 if (ret) 551 return ret; 552 553 /* then direction */ 554 return regmap_write_bits(chip->regmap, dirreg, bit, 0); 555 } 556 557 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 558 { 559 struct pca953x_chip *chip = gpiochip_get_data(gc); 560 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 561 u8 bit = BIT(off % BANK_SZ); 562 u32 reg_val; 563 int ret; 564 565 scoped_guard(mutex, &chip->i2c_lock) 566 ret = regmap_read(chip->regmap, inreg, ®_val); 567 if (ret < 0) 568 return ret; 569 570 return !!(reg_val & bit); 571 } 572 573 static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val) 574 { 575 struct pca953x_chip *chip = gpiochip_get_data(gc); 576 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 577 u8 bit = BIT(off % BANK_SZ); 578 579 guard(mutex)(&chip->i2c_lock); 580 581 regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0); 582 } 583 584 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 585 { 586 struct pca953x_chip *chip = gpiochip_get_data(gc); 587 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 588 u8 bit = BIT(off % BANK_SZ); 589 u32 reg_val; 590 int ret; 591 592 scoped_guard(mutex, &chip->i2c_lock) 593 ret = regmap_read(chip->regmap, dirreg, ®_val); 594 if (ret < 0) 595 return ret; 596 597 if (reg_val & bit) 598 return GPIO_LINE_DIRECTION_IN; 599 600 return GPIO_LINE_DIRECTION_OUT; 601 } 602 603 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 604 unsigned long *mask, unsigned long *bits) 605 { 606 struct pca953x_chip *chip = gpiochip_get_data(gc); 607 DECLARE_BITMAP(reg_val, MAX_LINE); 608 int ret; 609 610 scoped_guard(mutex, &chip->i2c_lock) 611 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 612 if (ret) 613 return ret; 614 615 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 616 return 0; 617 } 618 619 static void pca953x_gpio_set_multiple(struct gpio_chip *gc, 620 unsigned long *mask, unsigned long *bits) 621 { 622 struct pca953x_chip *chip = gpiochip_get_data(gc); 623 DECLARE_BITMAP(reg_val, MAX_LINE); 624 int ret; 625 626 guard(mutex)(&chip->i2c_lock); 627 628 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 629 if (ret) 630 return; 631 632 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 633 634 pca953x_write_regs(chip, chip->regs->output, reg_val); 635 } 636 637 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 638 unsigned int offset, 639 unsigned long config) 640 { 641 enum pin_config_param param = pinconf_to_config_param(config); 642 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 643 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 644 u8 bit = BIT(offset % BANK_SZ); 645 int ret; 646 647 /* 648 * pull-up/pull-down configuration requires PCAL extended 649 * registers 650 */ 651 if (!(chip->driver_data & PCA_PCAL)) 652 return -ENOTSUPP; 653 654 guard(mutex)(&chip->i2c_lock); 655 656 /* Configure pull-up/pull-down */ 657 if (param == PIN_CONFIG_BIAS_PULL_UP) 658 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit); 659 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 660 ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0); 661 else 662 ret = 0; 663 if (ret) 664 return ret; 665 666 /* Disable/Enable pull-up/pull-down */ 667 if (param == PIN_CONFIG_BIAS_DISABLE) 668 return regmap_write_bits(chip->regmap, pull_en_reg, bit, 0); 669 else 670 return regmap_write_bits(chip->regmap, pull_en_reg, bit, bit); 671 } 672 673 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 674 unsigned long config) 675 { 676 struct pca953x_chip *chip = gpiochip_get_data(gc); 677 678 switch (pinconf_to_config_param(config)) { 679 case PIN_CONFIG_BIAS_PULL_UP: 680 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 681 case PIN_CONFIG_BIAS_PULL_DOWN: 682 case PIN_CONFIG_BIAS_DISABLE: 683 return pca953x_gpio_set_pull_up_down(chip, offset, config); 684 default: 685 return -ENOTSUPP; 686 } 687 } 688 689 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 690 { 691 struct gpio_chip *gc = &chip->gpio_chip; 692 693 gc->direction_input = pca953x_gpio_direction_input; 694 gc->direction_output = pca953x_gpio_direction_output; 695 gc->get = pca953x_gpio_get_value; 696 gc->set = pca953x_gpio_set_value; 697 gc->get_direction = pca953x_gpio_get_direction; 698 gc->get_multiple = pca953x_gpio_get_multiple; 699 gc->set_multiple = pca953x_gpio_set_multiple; 700 gc->set_config = pca953x_gpio_set_config; 701 gc->can_sleep = true; 702 703 gc->base = chip->gpio_start; 704 gc->ngpio = gpios; 705 gc->label = dev_name(&chip->client->dev); 706 gc->parent = &chip->client->dev; 707 gc->owner = THIS_MODULE; 708 } 709 710 #ifdef CONFIG_GPIO_PCA953X_IRQ 711 static void pca953x_irq_mask(struct irq_data *d) 712 { 713 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 714 struct pca953x_chip *chip = gpiochip_get_data(gc); 715 irq_hw_number_t hwirq = irqd_to_hwirq(d); 716 717 clear_bit(hwirq, chip->irq_mask); 718 gpiochip_disable_irq(gc, hwirq); 719 } 720 721 static void pca953x_irq_unmask(struct irq_data *d) 722 { 723 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 724 struct pca953x_chip *chip = gpiochip_get_data(gc); 725 irq_hw_number_t hwirq = irqd_to_hwirq(d); 726 727 gpiochip_enable_irq(gc, hwirq); 728 set_bit(hwirq, chip->irq_mask); 729 } 730 731 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 732 { 733 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 734 struct pca953x_chip *chip = gpiochip_get_data(gc); 735 736 if (on) 737 atomic_inc(&chip->wakeup_path); 738 else 739 atomic_dec(&chip->wakeup_path); 740 741 return irq_set_irq_wake(chip->client->irq, on); 742 } 743 744 static void pca953x_irq_bus_lock(struct irq_data *d) 745 { 746 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 747 struct pca953x_chip *chip = gpiochip_get_data(gc); 748 749 mutex_lock(&chip->irq_lock); 750 } 751 752 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 753 { 754 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 755 struct pca953x_chip *chip = gpiochip_get_data(gc); 756 DECLARE_BITMAP(irq_mask, MAX_LINE); 757 DECLARE_BITMAP(reg_direction, MAX_LINE); 758 int level; 759 760 if (chip->driver_data & PCA_PCAL) { 761 /* Enable latch on interrupt-enabled inputs */ 762 pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask); 763 764 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 765 766 /* Unmask enabled interrupts */ 767 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 768 } 769 770 /* Switch direction to input if needed */ 771 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 772 773 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 774 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 775 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 776 777 /* Look for any newly setup interrupt */ 778 for_each_set_bit(level, irq_mask, gc->ngpio) 779 pca953x_gpio_direction_input(&chip->gpio_chip, level); 780 781 mutex_unlock(&chip->irq_lock); 782 } 783 784 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 785 { 786 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 787 struct pca953x_chip *chip = gpiochip_get_data(gc); 788 struct device *dev = &chip->client->dev; 789 irq_hw_number_t hwirq = irqd_to_hwirq(d); 790 791 if (!(type & IRQ_TYPE_EDGE_BOTH)) { 792 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 793 return -EINVAL; 794 } 795 796 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 797 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 798 799 return 0; 800 } 801 802 static void pca953x_irq_shutdown(struct irq_data *d) 803 { 804 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 805 struct pca953x_chip *chip = gpiochip_get_data(gc); 806 irq_hw_number_t hwirq = irqd_to_hwirq(d); 807 808 clear_bit(hwirq, chip->irq_trig_raise); 809 clear_bit(hwirq, chip->irq_trig_fall); 810 } 811 812 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 813 { 814 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 815 816 seq_printf(p, dev_name(gc->parent)); 817 } 818 819 static const struct irq_chip pca953x_irq_chip = { 820 .irq_mask = pca953x_irq_mask, 821 .irq_unmask = pca953x_irq_unmask, 822 .irq_set_wake = pca953x_irq_set_wake, 823 .irq_bus_lock = pca953x_irq_bus_lock, 824 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 825 .irq_set_type = pca953x_irq_set_type, 826 .irq_shutdown = pca953x_irq_shutdown, 827 .irq_print_chip = pca953x_irq_print_chip, 828 .flags = IRQCHIP_IMMUTABLE, 829 GPIOCHIP_IRQ_RESOURCE_HELPERS, 830 }; 831 832 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 833 { 834 struct gpio_chip *gc = &chip->gpio_chip; 835 DECLARE_BITMAP(reg_direction, MAX_LINE); 836 DECLARE_BITMAP(old_stat, MAX_LINE); 837 DECLARE_BITMAP(cur_stat, MAX_LINE); 838 DECLARE_BITMAP(new_stat, MAX_LINE); 839 DECLARE_BITMAP(trigger, MAX_LINE); 840 int ret; 841 842 if (chip->driver_data & PCA_PCAL) { 843 /* Read the current interrupt status from the device */ 844 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger); 845 if (ret) 846 return false; 847 848 /* Check latched inputs and clear interrupt status */ 849 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 850 if (ret) 851 return false; 852 853 /* Apply filter for rising/falling edge selection */ 854 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, cur_stat, gc->ngpio); 855 856 bitmap_and(pending, new_stat, trigger, gc->ngpio); 857 858 return !bitmap_empty(pending, gc->ngpio); 859 } 860 861 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 862 if (ret) 863 return false; 864 865 /* Remove output pins from the equation */ 866 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 867 868 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 869 870 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 871 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 872 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 873 874 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 875 876 if (bitmap_empty(trigger, gc->ngpio)) 877 return false; 878 879 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 880 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 881 bitmap_or(new_stat, old_stat, cur_stat, gc->ngpio); 882 bitmap_and(pending, new_stat, trigger, gc->ngpio); 883 884 return !bitmap_empty(pending, gc->ngpio); 885 } 886 887 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 888 { 889 struct pca953x_chip *chip = devid; 890 struct gpio_chip *gc = &chip->gpio_chip; 891 DECLARE_BITMAP(pending, MAX_LINE); 892 int level; 893 bool ret; 894 895 bitmap_zero(pending, MAX_LINE); 896 897 scoped_guard(mutex, &chip->i2c_lock) 898 ret = pca953x_irq_pending(chip, pending); 899 if (ret) { 900 ret = 0; 901 902 for_each_set_bit(level, pending, gc->ngpio) { 903 int nested_irq = irq_find_mapping(gc->irq.domain, level); 904 905 if (unlikely(nested_irq <= 0)) { 906 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 907 continue; 908 } 909 910 handle_nested_irq(nested_irq); 911 ret = 1; 912 } 913 } 914 915 return IRQ_RETVAL(ret); 916 } 917 918 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 919 { 920 struct i2c_client *client = chip->client; 921 struct device *dev = &client->dev; 922 DECLARE_BITMAP(reg_direction, MAX_LINE); 923 DECLARE_BITMAP(irq_stat, MAX_LINE); 924 struct gpio_chip *gc = &chip->gpio_chip; 925 struct gpio_irq_chip *girq; 926 int ret; 927 928 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 929 ret = pca953x_acpi_get_irq(dev); 930 if (ret > 0) 931 client->irq = ret; 932 } 933 934 if (!client->irq) 935 return 0; 936 937 if (irq_base == -1) 938 return 0; 939 940 if (!(chip->driver_data & PCA_INT)) 941 return 0; 942 943 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 944 if (ret) 945 return ret; 946 947 /* 948 * There is no way to know which GPIO line generated the 949 * interrupt. We have to rely on the previous read for 950 * this purpose. 951 */ 952 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 953 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 954 mutex_init(&chip->irq_lock); 955 956 girq = &chip->gpio_chip.irq; 957 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 958 /* This will let us handle the parent IRQ in the driver */ 959 girq->parent_handler = NULL; 960 girq->num_parents = 0; 961 girq->parents = NULL; 962 girq->default_type = IRQ_TYPE_NONE; 963 girq->handler = handle_simple_irq; 964 girq->threaded = true; 965 girq->first = irq_base; /* FIXME: get rid of this */ 966 967 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 968 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 969 chip); 970 if (ret) 971 return dev_err_probe(dev, client->irq, "failed to request irq\n"); 972 973 return 0; 974 } 975 976 #else /* CONFIG_GPIO_PCA953X_IRQ */ 977 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 978 { 979 struct i2c_client *client = chip->client; 980 struct device *dev = &client->dev; 981 982 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 983 dev_warn(dev, "interrupt support not compiled in\n"); 984 985 return 0; 986 } 987 #endif 988 989 static int device_pca95xx_init(struct pca953x_chip *chip) 990 { 991 DECLARE_BITMAP(val, MAX_LINE); 992 u8 regaddr; 993 int ret; 994 995 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 996 ret = regcache_sync_region(chip->regmap, regaddr, 997 regaddr + NBANK(chip) - 1); 998 if (ret) 999 return ret; 1000 1001 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1002 ret = regcache_sync_region(chip->regmap, regaddr, 1003 regaddr + NBANK(chip) - 1); 1004 if (ret) 1005 return ret; 1006 1007 /* clear polarity inversion */ 1008 bitmap_zero(val, MAX_LINE); 1009 1010 return pca953x_write_regs(chip, chip->regs->invert, val); 1011 } 1012 1013 static int device_pca957x_init(struct pca953x_chip *chip) 1014 { 1015 DECLARE_BITMAP(val, MAX_LINE); 1016 unsigned int i; 1017 int ret; 1018 1019 ret = device_pca95xx_init(chip); 1020 if (ret) 1021 return ret; 1022 1023 /* To enable register 6, 7 to control pull up and pull down */ 1024 for (i = 0; i < NBANK(chip); i++) 1025 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1026 1027 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1028 } 1029 1030 static void pca953x_disable_regulator(void *reg) 1031 { 1032 regulator_disable(reg); 1033 } 1034 1035 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1036 { 1037 struct device *dev = &chip->client->dev; 1038 struct regulator *reg = chip->regulator; 1039 int ret; 1040 1041 reg = devm_regulator_get(dev, "vcc"); 1042 if (IS_ERR(reg)) 1043 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1044 1045 ret = regulator_enable(reg); 1046 if (ret) 1047 return dev_err_probe(dev, ret, "reg en err\n"); 1048 1049 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1050 if (ret) 1051 return ret; 1052 1053 chip->regulator = reg; 1054 return 0; 1055 } 1056 1057 static int pca953x_probe(struct i2c_client *client) 1058 { 1059 struct device *dev = &client->dev; 1060 struct pca953x_platform_data *pdata; 1061 struct pca953x_chip *chip; 1062 int irq_base; 1063 int ret; 1064 const struct regmap_config *regmap_config; 1065 1066 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1067 if (chip == NULL) 1068 return -ENOMEM; 1069 1070 pdata = dev_get_platdata(dev); 1071 if (pdata) { 1072 irq_base = pdata->irq_base; 1073 chip->gpio_start = pdata->gpio_base; 1074 } else { 1075 struct gpio_desc *reset_gpio; 1076 1077 chip->gpio_start = -1; 1078 irq_base = 0; 1079 1080 /* 1081 * See if we need to de-assert a reset pin. 1082 * 1083 * There is no known ACPI-enabled platforms that are 1084 * using "reset" GPIO. Otherwise any of those platform 1085 * must use _DSD method with corresponding property. 1086 */ 1087 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1088 if (IS_ERR(reset_gpio)) 1089 return PTR_ERR(reset_gpio); 1090 } 1091 1092 chip->client = client; 1093 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1094 if (!chip->driver_data) 1095 return -ENODEV; 1096 1097 ret = pca953x_get_and_enable_regulator(chip); 1098 if (ret) 1099 return ret; 1100 1101 i2c_set_clientdata(client, chip); 1102 1103 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1104 1105 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1106 dev_info(dev, "using AI\n"); 1107 regmap_config = &pca953x_ai_i2c_regmap; 1108 } else { 1109 dev_info(dev, "using no AI\n"); 1110 regmap_config = &pca953x_i2c_regmap; 1111 } 1112 1113 if (PCA_CHIP_TYPE(chip->driver_data) == PCAL653X_TYPE) { 1114 chip->recalc_addr = pcal6534_recalc_addr; 1115 chip->check_reg = pcal6534_check_register; 1116 } else { 1117 chip->recalc_addr = pca953x_recalc_addr; 1118 chip->check_reg = pca953x_check_register; 1119 } 1120 1121 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1122 if (IS_ERR(chip->regmap)) 1123 return PTR_ERR(chip->regmap); 1124 1125 regcache_mark_dirty(chip->regmap); 1126 1127 mutex_init(&chip->i2c_lock); 1128 /* 1129 * In case we have an i2c-mux controlled by a GPIO provided by an 1130 * expander using the same driver higher on the device tree, read the 1131 * i2c adapter nesting depth and use the retrieved value as lockdep 1132 * subclass for chip->i2c_lock. 1133 * 1134 * REVISIT: This solution is not complete. It protects us from lockdep 1135 * false positives when the expander controlling the i2c-mux is on 1136 * a different level on the device tree, but not when it's on the same 1137 * level on a different branch (in which case the subclass number 1138 * would be the same). 1139 * 1140 * TODO: Once a correct solution is developed, a similar fix should be 1141 * applied to all other i2c-controlled GPIO expanders (and potentially 1142 * regmap-i2c). 1143 */ 1144 lockdep_set_subclass(&chip->i2c_lock, 1145 i2c_adapter_depth(client->adapter)); 1146 1147 /* initialize cached registers from their original values. 1148 * we can't share this chip with another i2c master. 1149 */ 1150 if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1151 chip->regs = &pca957x_regs; 1152 ret = device_pca957x_init(chip); 1153 } else { 1154 chip->regs = &pca953x_regs; 1155 ret = device_pca95xx_init(chip); 1156 } 1157 if (ret) 1158 return ret; 1159 1160 ret = pca953x_irq_setup(chip, irq_base); 1161 if (ret) 1162 return ret; 1163 1164 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1165 } 1166 1167 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1168 { 1169 struct device *dev = &chip->client->dev; 1170 int ret; 1171 u8 regaddr; 1172 1173 /* 1174 * The ordering between direction and output is important, 1175 * sync these registers first and only then sync the rest. 1176 */ 1177 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1178 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1179 if (ret) { 1180 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1181 return ret; 1182 } 1183 1184 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1185 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1186 if (ret) { 1187 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1188 return ret; 1189 } 1190 1191 #ifdef CONFIG_GPIO_PCA953X_IRQ 1192 if (chip->driver_data & PCA_PCAL) { 1193 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1194 ret = regcache_sync_region(chip->regmap, regaddr, 1195 regaddr + NBANK(chip) - 1); 1196 if (ret) { 1197 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1198 ret); 1199 return ret; 1200 } 1201 1202 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1203 ret = regcache_sync_region(chip->regmap, regaddr, 1204 regaddr + NBANK(chip) - 1); 1205 if (ret) { 1206 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1207 ret); 1208 return ret; 1209 } 1210 } 1211 #endif 1212 1213 return 0; 1214 } 1215 1216 static int pca953x_restore_context(struct pca953x_chip *chip) 1217 { 1218 int ret; 1219 1220 guard(mutex)(&chip->i2c_lock); 1221 1222 regcache_cache_only(chip->regmap, false); 1223 regcache_mark_dirty(chip->regmap); 1224 ret = pca953x_regcache_sync(chip); 1225 if (ret) 1226 return ret; 1227 1228 return regcache_sync(chip->regmap); 1229 } 1230 1231 static void pca953x_save_context(struct pca953x_chip *chip) 1232 { 1233 guard(mutex)(&chip->i2c_lock); 1234 regcache_cache_only(chip->regmap, true); 1235 } 1236 1237 static int pca953x_suspend(struct device *dev) 1238 { 1239 struct pca953x_chip *chip = dev_get_drvdata(dev); 1240 1241 pca953x_save_context(chip); 1242 1243 if (atomic_read(&chip->wakeup_path)) 1244 device_set_wakeup_path(dev); 1245 else 1246 regulator_disable(chip->regulator); 1247 1248 return 0; 1249 } 1250 1251 static int pca953x_resume(struct device *dev) 1252 { 1253 struct pca953x_chip *chip = dev_get_drvdata(dev); 1254 int ret; 1255 1256 if (!atomic_read(&chip->wakeup_path)) { 1257 ret = regulator_enable(chip->regulator); 1258 if (ret) { 1259 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1260 return 0; 1261 } 1262 } 1263 1264 ret = pca953x_restore_context(chip); 1265 if (ret) 1266 dev_err(dev, "Failed to restore register map: %d\n", ret); 1267 1268 return ret; 1269 } 1270 1271 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1272 1273 /* convenience to stop overlong match-table lines */ 1274 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1275 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1276 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1277 1278 static const struct of_device_id pca953x_dt_ids[] = { 1279 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1280 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1281 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1282 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1283 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1284 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1285 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1286 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1287 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1288 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1289 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1290 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1291 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1292 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1293 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1294 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1295 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1296 1297 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1298 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1299 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1300 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1301 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1302 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1303 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1304 1305 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1306 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1307 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1308 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1309 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1310 1311 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1312 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1313 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1314 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1315 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1316 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1317 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1318 1319 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1320 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1321 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1322 1323 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1324 { } 1325 }; 1326 1327 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1328 1329 static struct i2c_driver pca953x_driver = { 1330 .driver = { 1331 .name = "pca953x", 1332 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1333 .of_match_table = pca953x_dt_ids, 1334 .acpi_match_table = pca953x_acpi_ids, 1335 }, 1336 .probe = pca953x_probe, 1337 .id_table = pca953x_id, 1338 }; 1339 1340 static int __init pca953x_init(void) 1341 { 1342 return i2c_add_driver(&pca953x_driver); 1343 } 1344 /* register after i2c postcore initcall and before 1345 * subsys initcalls that may rely on these GPIOs 1346 */ 1347 subsys_initcall(pca953x_init); 1348 1349 static void __exit pca953x_exit(void) 1350 { 1351 i2c_del_driver(&pca953x_driver); 1352 } 1353 module_exit(pca953x_exit); 1354 1355 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1356 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1357 MODULE_LICENSE("GPL"); 1358