1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/module.h> 21 #include <linux/mutex.h> 22 #include <linux/pm.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/seq_file.h> 26 #include <linux/slab.h> 27 28 #include <linux/gpio/consumer.h> 29 #include <linux/gpio/driver.h> 30 31 #include <linux/pinctrl/pinconf-generic.h> 32 33 #include <linux/platform_data/pca953x.h> 34 35 #define PCA953X_INPUT 0x00 36 #define PCA953X_OUTPUT 0x01 37 #define PCA953X_INVERT 0x02 38 #define PCA953X_DIRECTION 0x03 39 40 #define TCA6418_INPUT 0x14 41 #define TCA6418_OUTPUT 0x17 42 #define TCA6418_DIRECTION 0x23 43 44 #define REG_ADDR_MASK GENMASK(5, 0) 45 #define REG_ADDR_EXT BIT(6) 46 #define REG_ADDR_AI BIT(7) 47 48 #define PCA957X_IN 0x00 49 #define PCA957X_INVRT 0x01 50 #define PCA957X_BKEN 0x02 51 #define PCA957X_PUPD 0x03 52 #define PCA957X_CFG 0x04 53 #define PCA957X_OUT 0x05 54 #define PCA957X_MSK 0x06 55 #define PCA957X_INTS 0x07 56 57 #define PCAL953X_OUT_STRENGTH 0x20 58 #define PCAL953X_IN_LATCH 0x22 59 #define PCAL953X_PULL_EN 0x23 60 #define PCAL953X_PULL_SEL 0x24 61 #define PCAL953X_INT_MASK 0x25 62 #define PCAL953X_INT_STAT 0x26 63 #define PCAL953X_OUT_CONF 0x27 64 65 #define PCAL6524_INT_EDGE 0x28 66 #define PCAL6524_INT_CLR 0x2a 67 #define PCAL6524_IN_STATUS 0x2b 68 #define PCAL6524_OUT_INDCONF 0x2c 69 #define PCAL6524_DEBOUNCE 0x2d 70 71 #define PCA_GPIO_MASK GENMASK(7, 0) 72 73 #define PCAL_GPIO_MASK GENMASK(4, 0) 74 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 75 76 #define PCA_INT BIT(8) 77 #define PCA_PCAL BIT(9) 78 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 79 #define PCA953X_TYPE BIT(12) 80 #define PCA957X_TYPE BIT(13) 81 #define PCAL653X_TYPE BIT(14) 82 #define TCA6418_TYPE BIT(16) 83 #define PCA_TYPE_MASK GENMASK(16, 12) 84 85 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 86 87 static const struct i2c_device_id pca953x_id[] = { 88 { .name = "pca6408", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 89 { .name = "pca6416", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 90 { .name = "pca9505", .driver_data = 40 | PCA953X_TYPE | PCA_INT }, 91 { .name = "pca9506", .driver_data = 40 | PCA953X_TYPE | PCA_INT }, 92 { .name = "pca9534", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 93 { .name = "pca9535", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 94 { .name = "pca9536", .driver_data = 4 | PCA953X_TYPE }, 95 { .name = "pca9537", .driver_data = 4 | PCA953X_TYPE | PCA_INT }, 96 { .name = "pca9538", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 97 { .name = "pca9539", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 98 { .name = "pca9554", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 99 { .name = "pca9555", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 100 { .name = "pca9556", .driver_data = 8 | PCA953X_TYPE }, 101 { .name = "pca9557", .driver_data = 8 | PCA953X_TYPE }, 102 { .name = "pca9574", .driver_data = 8 | PCA957X_TYPE | PCA_INT }, 103 { .name = "pca9575", .driver_data = 16 | PCA957X_TYPE | PCA_INT }, 104 { .name = "pca9698", .driver_data = 40 | PCA953X_TYPE }, 105 106 { .name = "pcal6408", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 107 { .name = "pcal6416", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 108 { .name = "pcal6524", .driver_data = 24 | PCA953X_TYPE | PCA_LATCH_INT }, 109 { .name = "pcal6534", .driver_data = 34 | PCAL653X_TYPE | PCA_LATCH_INT }, 110 { .name = "pcal9535", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 111 { .name = "pcal9554b", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 112 { .name = "pcal9555a", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 113 114 { .name = "max7310", .driver_data = 8 | PCA953X_TYPE }, 115 { .name = "max7312", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 116 { .name = "max7313", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 117 { .name = "max7315", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 118 { .name = "max7318", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 119 { .name = "pca6107", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 120 { .name = "tca6408", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 121 { .name = "tca6416", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 122 { .name = "tca6418", .driver_data = 18 | TCA6418_TYPE | PCA_INT }, 123 { .name = "tca6424", .driver_data = 24 | PCA953X_TYPE | PCA_INT }, 124 { .name = "tca9538", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 125 { .name = "tca9539", .driver_data = 16 | PCA953X_TYPE | PCA_INT }, 126 { .name = "tca9554", .driver_data = 8 | PCA953X_TYPE | PCA_INT }, 127 { .name = "xra1202", .driver_data = 8 | PCA953X_TYPE }, 128 129 { .name = "tcal6408", .driver_data = 8 | PCA953X_TYPE | PCA_LATCH_INT }, 130 { .name = "tcal6416", .driver_data = 16 | PCA953X_TYPE | PCA_LATCH_INT }, 131 { } 132 }; 133 MODULE_DEVICE_TABLE(i2c, pca953x_id); 134 135 #ifdef CONFIG_GPIO_PCA953X_IRQ 136 137 #include <linux/acpi.h> 138 #include <linux/dmi.h> 139 140 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 141 142 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 143 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 144 { } 145 }; 146 147 static int pca953x_acpi_get_irq(struct device *dev) 148 { 149 int ret; 150 151 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 152 if (ret) 153 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 154 155 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 156 if (ret < 0) 157 return ret; 158 159 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 160 return ret; 161 } 162 163 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 164 { 165 /* 166 * On Intel Galileo Gen 2 board the IRQ pin of one of 167 * the I²C GPIO expanders, which has GpioInt() resource, 168 * is provided as an absolute number instead of being 169 * relative. Since first controller (gpio-sch.c) and 170 * second (gpio-dwapb.c) are at the fixed bases, we may 171 * safely refer to the number in the global space to get 172 * an IRQ out of it. 173 */ 174 .matches = { 175 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 176 }, 177 }, 178 {} 179 }; 180 #endif 181 182 static const struct acpi_device_id pca953x_acpi_ids[] = { 183 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 184 { } 185 }; 186 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 187 188 #define MAX_BANK 5 189 #define BANK_SZ 8 190 #define MAX_LINE (MAX_BANK * BANK_SZ) 191 192 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 193 194 struct pca953x_reg_config { 195 int direction; 196 int output; 197 int input; 198 int invert; 199 }; 200 201 static const struct pca953x_reg_config pca953x_regs = { 202 .direction = PCA953X_DIRECTION, 203 .output = PCA953X_OUTPUT, 204 .input = PCA953X_INPUT, 205 .invert = PCA953X_INVERT, 206 }; 207 208 static const struct pca953x_reg_config pca957x_regs = { 209 .direction = PCA957X_CFG, 210 .output = PCA957X_OUT, 211 .input = PCA957X_IN, 212 .invert = PCA957X_INVRT, 213 }; 214 215 static const struct pca953x_reg_config tca6418_regs = { 216 .direction = TCA6418_DIRECTION, 217 .output = TCA6418_OUTPUT, 218 .input = TCA6418_INPUT, 219 .invert = 0xFF, /* Does not apply */ 220 }; 221 222 struct pca953x_chip { 223 unsigned gpio_start; 224 struct mutex i2c_lock; 225 struct regmap *regmap; 226 227 #ifdef CONFIG_GPIO_PCA953X_IRQ 228 struct mutex irq_lock; 229 DECLARE_BITMAP(irq_mask, MAX_LINE); 230 DECLARE_BITMAP(irq_stat, MAX_LINE); 231 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 232 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 233 DECLARE_BITMAP(irq_trig_level_high, MAX_LINE); 234 DECLARE_BITMAP(irq_trig_level_low, MAX_LINE); 235 #endif 236 atomic_t wakeup_path; 237 238 struct i2c_client *client; 239 struct gpio_chip gpio_chip; 240 unsigned long driver_data; 241 struct regulator *regulator; 242 243 const struct pca953x_reg_config *regs; 244 245 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 246 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 247 u32 checkbank); 248 }; 249 250 static int pca953x_bank_shift(struct pca953x_chip *chip) 251 { 252 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 253 } 254 255 /* 256 * Helper function to get the correct bit mask for a given offset and chip type. 257 * The TCA6418's input, output, and direction banks have a peculiar bit order: 258 * the first byte uses reversed bit order, while the second byte uses standard order. 259 */ 260 static inline u8 pca953x_get_bit_mask(struct pca953x_chip *chip, unsigned int offset) 261 { 262 unsigned int bit_pos_in_bank = offset % BANK_SZ; 263 int msb = BANK_SZ - 1; 264 265 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE && offset <= msb) 266 return BIT(msb - bit_pos_in_bank); 267 268 return BIT(bit_pos_in_bank); 269 } 270 271 #define PCA953x_BANK_INPUT BIT(0) 272 #define PCA953x_BANK_OUTPUT BIT(1) 273 #define PCA953x_BANK_POLARITY BIT(2) 274 #define PCA953x_BANK_CONFIG BIT(3) 275 276 #define PCA957x_BANK_INPUT BIT(0) 277 #define PCA957x_BANK_POLARITY BIT(1) 278 #define PCA957x_BANK_BUSHOLD BIT(2) 279 #define PCA957x_BANK_CONFIG BIT(4) 280 #define PCA957x_BANK_OUTPUT BIT(5) 281 282 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 283 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 284 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 285 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 286 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 287 288 /* 289 * We care about the following registers: 290 * - Standard set, below 0x40, each port can be replicated up to 8 times 291 * - PCA953x standard 292 * Input port 0x00 + 0 * bank_size R 293 * Output port 0x00 + 1 * bank_size RW 294 * Polarity Inversion port 0x00 + 2 * bank_size RW 295 * Configuration port 0x00 + 3 * bank_size RW 296 * - PCA957x with mixed up registers 297 * Input port 0x00 + 0 * bank_size R 298 * Polarity Inversion port 0x00 + 1 * bank_size RW 299 * Bus hold port 0x00 + 2 * bank_size RW 300 * Configuration port 0x00 + 4 * bank_size RW 301 * Output port 0x00 + 5 * bank_size RW 302 * 303 * - Extended set, above 0x40, often chip specific. 304 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 305 * Input latch register 0x40 + 2 * bank_size RW 306 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 307 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 308 * Interrupt mask register 0x40 + 5 * bank_size RW 309 * Interrupt status register 0x40 + 6 * bank_size R 310 * 311 * - Registers with bit 0x80 set, the AI bit (auto increment) 312 * The bit is cleared and the registers fall into one of the 313 * categories above. 314 */ 315 316 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 317 u32 checkbank) 318 { 319 int bank_shift = pca953x_bank_shift(chip); 320 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 321 int offset = reg & (BIT(bank_shift) - 1); 322 323 /* Special PCAL extended register check. */ 324 if (reg & REG_ADDR_EXT) { 325 if (!(chip->driver_data & PCA_PCAL)) 326 return false; 327 bank += 8; 328 } 329 330 /* Register is not in the matching bank. */ 331 if (!(BIT(bank) & checkbank)) 332 return false; 333 334 /* Register is not within allowed range of bank. */ 335 if (offset >= NBANK(chip)) 336 return false; 337 338 return true; 339 } 340 341 /* 342 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 343 * same register layout as the PCAL6524, the spacing of the registers has been 344 * fundamentally altered by compacting them and thus does not obey the same 345 * rules, including being able to use bit shifting to determine bank. These 346 * chips hence need special handling here. 347 */ 348 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 349 u32 checkbank) 350 { 351 int bank_shift; 352 int bank; 353 int offset; 354 355 if (reg >= 0x54) { 356 /* 357 * Handle lack of reserved registers after output port 358 * configuration register to form a bank. 359 */ 360 reg -= 0x54; 361 bank_shift = 16; 362 } else if (reg >= 0x30) { 363 /* 364 * Reserved block between 14h and 2Fh does not align on 365 * expected bank boundaries like other devices. 366 */ 367 reg -= 0x30; 368 bank_shift = 8; 369 } else { 370 bank_shift = 0; 371 } 372 373 bank = bank_shift + reg / NBANK(chip); 374 offset = reg % NBANK(chip); 375 376 /* Register is not in the matching bank. */ 377 if (!(BIT(bank) & checkbank)) 378 return false; 379 380 /* Register is not within allowed range of bank. */ 381 if (offset >= NBANK(chip)) 382 return false; 383 384 return true; 385 } 386 387 /* TCA6418 breaks the PCA953x register order rule */ 388 static bool tca6418_check_register(struct pca953x_chip *chip, unsigned int reg, 389 u32 access_type_mask) 390 { 391 /* Valid Input Registers - BIT(0) for readable access */ 392 if (reg >= TCA6418_INPUT && reg < (TCA6418_INPUT + NBANK(chip))) 393 return (access_type_mask & BIT(0)); 394 395 /* Valid Output Registers - BIT(1) for writeable access */ 396 if (reg >= TCA6418_OUTPUT && reg < (TCA6418_OUTPUT + NBANK(chip))) 397 return (access_type_mask & (BIT(0) | BIT(1))); 398 399 /* Valid Direction Registers - BIT(2) for volatile access */ 400 if (reg >= TCA6418_DIRECTION && reg < (TCA6418_DIRECTION + NBANK(chip))) 401 return (access_type_mask & (BIT(0) | BIT(1))); 402 403 return false; 404 } 405 406 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 407 { 408 struct pca953x_chip *chip = dev_get_drvdata(dev); 409 u32 bank; 410 411 switch (PCA_CHIP_TYPE(chip->driver_data)) { 412 case PCA957X_TYPE: 413 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 414 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 415 PCA957x_BANK_BUSHOLD; 416 break; 417 case TCA6418_TYPE: 418 /* BIT(0) to indicate read access */ 419 return tca6418_check_register(chip, reg, BIT(0)); 420 default: 421 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 422 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 423 break; 424 } 425 426 if (chip->driver_data & PCA_PCAL) { 427 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 428 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 429 PCAL9xxx_BANK_IRQ_STAT; 430 } 431 432 return chip->check_reg(chip, reg, bank); 433 } 434 435 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 436 { 437 struct pca953x_chip *chip = dev_get_drvdata(dev); 438 u32 bank; 439 440 switch (PCA_CHIP_TYPE(chip->driver_data)) { 441 case PCA957X_TYPE: 442 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 443 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 444 break; 445 case TCA6418_TYPE: 446 /* BIT(1) for write access */ 447 return tca6418_check_register(chip, reg, BIT(1)); 448 default: 449 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 450 PCA953x_BANK_CONFIG; 451 break; 452 } 453 454 if (chip->driver_data & PCA_PCAL) 455 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 456 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 457 458 return chip->check_reg(chip, reg, bank); 459 } 460 461 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 462 { 463 struct pca953x_chip *chip = dev_get_drvdata(dev); 464 u32 bank; 465 466 switch (PCA_CHIP_TYPE(chip->driver_data)) { 467 case PCA957X_TYPE: 468 bank = PCA957x_BANK_INPUT; 469 break; 470 case TCA6418_TYPE: 471 /* BIT(2) for volatile access */ 472 return tca6418_check_register(chip, reg, BIT(2)); 473 default: 474 bank = PCA953x_BANK_INPUT; 475 break; 476 } 477 478 if (chip->driver_data & PCA_PCAL) 479 bank |= PCAL9xxx_BANK_IRQ_STAT; 480 481 return chip->check_reg(chip, reg, bank); 482 } 483 484 static const struct regmap_config pca953x_i2c_regmap = { 485 .reg_bits = 8, 486 .val_bits = 8, 487 488 .use_single_read = true, 489 .use_single_write = true, 490 491 .readable_reg = pca953x_readable_register, 492 .writeable_reg = pca953x_writeable_register, 493 .volatile_reg = pca953x_volatile_register, 494 495 .disable_locking = true, 496 .cache_type = REGCACHE_MAPLE, 497 .max_register = 0x7f, 498 }; 499 500 static const struct regmap_config pca953x_ai_i2c_regmap = { 501 .reg_bits = 8, 502 .val_bits = 8, 503 504 .read_flag_mask = REG_ADDR_AI, 505 .write_flag_mask = REG_ADDR_AI, 506 507 .readable_reg = pca953x_readable_register, 508 .writeable_reg = pca953x_writeable_register, 509 .volatile_reg = pca953x_volatile_register, 510 511 .disable_locking = true, 512 .cache_type = REGCACHE_MAPLE, 513 .max_register = 0x7f, 514 }; 515 516 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 517 { 518 int bank_shift = pca953x_bank_shift(chip); 519 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 520 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 521 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 522 523 return regaddr; 524 } 525 526 /* 527 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 528 * fit within the bit shifting scheme used for other devices. 529 */ 530 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 531 { 532 int addr; 533 int pinctrl; 534 535 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 536 537 switch (reg) { 538 case PCAL953X_OUT_STRENGTH: 539 case PCAL953X_IN_LATCH: 540 case PCAL953X_PULL_EN: 541 case PCAL953X_PULL_SEL: 542 case PCAL953X_INT_MASK: 543 case PCAL953X_INT_STAT: 544 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 545 break; 546 case PCAL6524_INT_EDGE: 547 case PCAL6524_INT_CLR: 548 case PCAL6524_IN_STATUS: 549 case PCAL6524_OUT_INDCONF: 550 case PCAL6524_DEBOUNCE: 551 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 552 break; 553 default: 554 pinctrl = 0; 555 break; 556 } 557 558 return pinctrl + addr + (off / BANK_SZ); 559 } 560 561 static u8 tca6418_recalc_addr(struct pca953x_chip *chip, int reg_base, int offset) 562 { 563 /* 564 * reg_base will be TCA6418_INPUT, TCA6418_OUTPUT, or TCA6418_DIRECTION 565 * offset is the global GPIO line offset (0-17) 566 * BANK_SZ is 8 for TCA6418 (8 bits per register bank) 567 */ 568 return reg_base + (offset / BANK_SZ); 569 } 570 571 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 572 { 573 u8 regaddr = chip->recalc_addr(chip, reg, 0); 574 u8 value[MAX_BANK]; 575 int i, ret; 576 577 for (i = 0; i < NBANK(chip); i++) 578 value[i] = bitmap_get_value8(val, i * BANK_SZ); 579 580 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 581 if (ret < 0) { 582 dev_err(&chip->client->dev, "failed writing register: %d\n", ret); 583 return ret; 584 } 585 586 return 0; 587 } 588 589 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 590 { 591 u8 regaddr = chip->recalc_addr(chip, reg, 0); 592 u8 value[MAX_BANK]; 593 int i, ret; 594 595 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 596 if (ret < 0) { 597 dev_err(&chip->client->dev, "failed reading register: %d\n", ret); 598 return ret; 599 } 600 601 for (i = 0; i < NBANK(chip); i++) 602 bitmap_set_value8(val, value[i], i * BANK_SZ); 603 604 return 0; 605 } 606 607 static int pca953x_gpio_direction_input_unlocked(struct gpio_chip *gc, 608 unsigned int off) 609 { 610 struct pca953x_chip *chip = gpiochip_get_data(gc); 611 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 612 u8 bit = pca953x_get_bit_mask(chip, off); 613 614 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 615 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 616 617 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 618 } 619 620 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned int off) 621 { 622 struct pca953x_chip *chip = gpiochip_get_data(gc); 623 624 guard(mutex)(&chip->i2c_lock); 625 626 return pca953x_gpio_direction_input_unlocked(gc, off); 627 } 628 629 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 630 unsigned off, int val) 631 { 632 struct pca953x_chip *chip = gpiochip_get_data(gc); 633 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 634 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 635 u8 bit = pca953x_get_bit_mask(chip, off); 636 int ret; 637 638 guard(mutex)(&chip->i2c_lock); 639 640 /* set output level */ 641 ret = regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 642 if (ret) 643 return ret; 644 645 /* 646 * then direction 647 * (in/out logic is inverted on TCA6418) 648 */ 649 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 650 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 651 652 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 653 } 654 655 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 656 { 657 struct pca953x_chip *chip = gpiochip_get_data(gc); 658 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 659 u8 bit = pca953x_get_bit_mask(chip, off); 660 u32 reg_val; 661 int ret; 662 663 scoped_guard(mutex, &chip->i2c_lock) 664 ret = regmap_read(chip->regmap, inreg, ®_val); 665 if (ret < 0) 666 return ret; 667 668 return !!(reg_val & bit); 669 } 670 671 static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 672 int val) 673 { 674 struct pca953x_chip *chip = gpiochip_get_data(gc); 675 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 676 u8 bit = pca953x_get_bit_mask(chip, off); 677 678 guard(mutex)(&chip->i2c_lock); 679 680 return regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 681 } 682 683 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 684 { 685 struct pca953x_chip *chip = gpiochip_get_data(gc); 686 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 687 u8 bit = pca953x_get_bit_mask(chip, off); 688 u32 reg_val; 689 int ret; 690 691 scoped_guard(mutex, &chip->i2c_lock) 692 ret = regmap_read(chip->regmap, dirreg, ®_val); 693 if (ret < 0) 694 return ret; 695 696 /* (in/out logic is inverted on TCA6418) */ 697 if (reg_val & bit) { 698 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 699 return GPIO_LINE_DIRECTION_OUT; 700 701 return GPIO_LINE_DIRECTION_IN; 702 } 703 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 704 return GPIO_LINE_DIRECTION_IN; 705 706 return GPIO_LINE_DIRECTION_OUT; 707 } 708 709 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 710 unsigned long *mask, unsigned long *bits) 711 { 712 struct pca953x_chip *chip = gpiochip_get_data(gc); 713 DECLARE_BITMAP(reg_val, MAX_LINE); 714 int ret; 715 716 scoped_guard(mutex, &chip->i2c_lock) 717 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 718 if (ret) 719 return ret; 720 721 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 722 return 0; 723 } 724 725 static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 726 unsigned long *mask, unsigned long *bits) 727 { 728 struct pca953x_chip *chip = gpiochip_get_data(gc); 729 DECLARE_BITMAP(reg_val, MAX_LINE); 730 int ret; 731 732 guard(mutex)(&chip->i2c_lock); 733 734 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 735 if (ret) 736 return ret; 737 738 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 739 740 return pca953x_write_regs(chip, chip->regs->output, reg_val); 741 } 742 743 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 744 unsigned int offset, 745 unsigned long config) 746 { 747 enum pin_config_param param = pinconf_to_config_param(config); 748 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 749 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 750 u8 bit = BIT(offset % BANK_SZ); 751 int ret; 752 753 /* 754 * pull-up/pull-down configuration requires PCAL extended 755 * registers 756 */ 757 if (!(chip->driver_data & PCA_PCAL)) 758 return -ENOTSUPP; 759 760 guard(mutex)(&chip->i2c_lock); 761 762 /* Configure pull-up/pull-down */ 763 if (param == PIN_CONFIG_BIAS_PULL_UP) 764 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, bit); 765 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 766 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, 0); 767 else 768 ret = 0; 769 if (ret) 770 return ret; 771 772 /* Disable/Enable pull-up/pull-down */ 773 if (param == PIN_CONFIG_BIAS_DISABLE) 774 return regmap_update_bits(chip->regmap, pull_en_reg, bit, 0); 775 else 776 return regmap_update_bits(chip->regmap, pull_en_reg, bit, bit); 777 } 778 779 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 780 unsigned long config) 781 { 782 struct pca953x_chip *chip = gpiochip_get_data(gc); 783 784 switch (pinconf_to_config_param(config)) { 785 case PIN_CONFIG_BIAS_PULL_UP: 786 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 787 case PIN_CONFIG_BIAS_PULL_DOWN: 788 case PIN_CONFIG_BIAS_DISABLE: 789 return pca953x_gpio_set_pull_up_down(chip, offset, config); 790 default: 791 return -ENOTSUPP; 792 } 793 } 794 795 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 796 { 797 struct gpio_chip *gc = &chip->gpio_chip; 798 799 gc->direction_input = pca953x_gpio_direction_input; 800 gc->direction_output = pca953x_gpio_direction_output; 801 gc->get = pca953x_gpio_get_value; 802 gc->set = pca953x_gpio_set_value; 803 gc->get_direction = pca953x_gpio_get_direction; 804 gc->get_multiple = pca953x_gpio_get_multiple; 805 gc->set_multiple = pca953x_gpio_set_multiple; 806 gc->set_config = pca953x_gpio_set_config; 807 gc->can_sleep = true; 808 809 gc->base = chip->gpio_start; 810 gc->ngpio = gpios; 811 gc->label = dev_name(&chip->client->dev); 812 gc->parent = &chip->client->dev; 813 gc->owner = THIS_MODULE; 814 } 815 816 #ifdef CONFIG_GPIO_PCA953X_IRQ 817 static void pca953x_irq_mask(struct irq_data *d) 818 { 819 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 820 struct pca953x_chip *chip = gpiochip_get_data(gc); 821 irq_hw_number_t hwirq = irqd_to_hwirq(d); 822 823 clear_bit(hwirq, chip->irq_mask); 824 gpiochip_disable_irq(gc, hwirq); 825 } 826 827 static void pca953x_irq_unmask(struct irq_data *d) 828 { 829 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 830 struct pca953x_chip *chip = gpiochip_get_data(gc); 831 irq_hw_number_t hwirq = irqd_to_hwirq(d); 832 833 gpiochip_enable_irq(gc, hwirq); 834 set_bit(hwirq, chip->irq_mask); 835 } 836 837 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 838 { 839 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 840 struct pca953x_chip *chip = gpiochip_get_data(gc); 841 842 if (on) 843 atomic_inc(&chip->wakeup_path); 844 else 845 atomic_dec(&chip->wakeup_path); 846 847 return irq_set_irq_wake(chip->client->irq, on); 848 } 849 850 static void pca953x_irq_bus_lock(struct irq_data *d) 851 { 852 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 853 struct pca953x_chip *chip = gpiochip_get_data(gc); 854 855 mutex_lock(&chip->irq_lock); 856 } 857 858 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 859 { 860 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 861 struct pca953x_chip *chip = gpiochip_get_data(gc); 862 DECLARE_BITMAP(irq_mask, MAX_LINE); 863 DECLARE_BITMAP(reg_direction, MAX_LINE); 864 int level; 865 866 guard(mutex)(&chip->i2c_lock); 867 868 if (chip->driver_data & PCA_PCAL) { 869 DECLARE_BITMAP(latched_inputs, MAX_LINE); 870 871 /* Enable latch on edge-triggered interrupt-enabled inputs */ 872 bitmap_or(latched_inputs, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 873 bitmap_and(latched_inputs, latched_inputs, chip->irq_mask, gc->ngpio); 874 pca953x_write_regs(chip, PCAL953X_IN_LATCH, latched_inputs); 875 876 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 877 878 /* Unmask enabled interrupts */ 879 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 880 } 881 882 /* Switch direction to input if needed */ 883 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 884 885 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 886 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_high, gc->ngpio); 887 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_low, gc->ngpio); 888 889 /* Look for any newly setup interrupt */ 890 for_each_andnot_bit(level, irq_mask, reg_direction, gc->ngpio) 891 pca953x_gpio_direction_input_unlocked(&chip->gpio_chip, level); 892 893 mutex_unlock(&chip->irq_lock); 894 } 895 896 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 897 { 898 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 899 struct pca953x_chip *chip = gpiochip_get_data(gc); 900 struct device *dev = &chip->client->dev; 901 irq_hw_number_t hwirq = irqd_to_hwirq(d); 902 903 if (!(type & IRQ_TYPE_SENSE_MASK)) { 904 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 905 return -EINVAL; 906 } 907 908 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 909 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 910 assign_bit(hwirq, chip->irq_trig_level_low, type & IRQ_TYPE_LEVEL_LOW); 911 assign_bit(hwirq, chip->irq_trig_level_high, type & IRQ_TYPE_LEVEL_HIGH); 912 913 return 0; 914 } 915 916 static void pca953x_irq_shutdown(struct irq_data *d) 917 { 918 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 919 struct pca953x_chip *chip = gpiochip_get_data(gc); 920 irq_hw_number_t hwirq = irqd_to_hwirq(d); 921 922 clear_bit(hwirq, chip->irq_trig_raise); 923 clear_bit(hwirq, chip->irq_trig_fall); 924 clear_bit(hwirq, chip->irq_trig_level_low); 925 clear_bit(hwirq, chip->irq_trig_level_high); 926 927 pca953x_irq_mask(d); 928 } 929 930 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 931 { 932 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 933 934 seq_puts(p, dev_name(gc->parent)); 935 } 936 937 static const struct irq_chip pca953x_irq_chip = { 938 .irq_mask = pca953x_irq_mask, 939 .irq_unmask = pca953x_irq_unmask, 940 .irq_set_wake = pca953x_irq_set_wake, 941 .irq_bus_lock = pca953x_irq_bus_lock, 942 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 943 .irq_set_type = pca953x_irq_set_type, 944 .irq_shutdown = pca953x_irq_shutdown, 945 .irq_print_chip = pca953x_irq_print_chip, 946 .flags = IRQCHIP_IMMUTABLE, 947 GPIOCHIP_IRQ_RESOURCE_HELPERS, 948 }; 949 950 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 951 { 952 struct gpio_chip *gc = &chip->gpio_chip; 953 DECLARE_BITMAP(reg_direction, MAX_LINE); 954 DECLARE_BITMAP(old_stat, MAX_LINE); 955 DECLARE_BITMAP(cur_stat, MAX_LINE); 956 DECLARE_BITMAP(new_stat, MAX_LINE); 957 DECLARE_BITMAP(int_stat, MAX_LINE); 958 DECLARE_BITMAP(trigger, MAX_LINE); 959 DECLARE_BITMAP(edges, MAX_LINE); 960 int ret; 961 962 if (chip->driver_data & PCA_PCAL) { 963 /* Read INT_STAT before it is cleared by the input-port read. */ 964 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, int_stat); 965 if (ret) 966 return false; 967 } 968 969 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 970 if (ret) 971 return false; 972 973 if (chip->driver_data & PCA_PCAL) { 974 /* Detect short pulses via INT_STAT. */ 975 bitmap_and(trigger, int_stat, chip->irq_mask, gc->ngpio); 976 977 /* Apply filter for rising/falling edge selection. */ 978 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 979 cur_stat, gc->ngpio); 980 981 bitmap_and(int_stat, new_stat, trigger, gc->ngpio); 982 } else { 983 bitmap_zero(int_stat, gc->ngpio); 984 } 985 986 /* Remove output pins from the equation */ 987 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 988 989 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 990 991 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 992 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 993 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 994 995 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 996 997 if (bitmap_empty(chip->irq_trig_level_high, gc->ngpio) && 998 bitmap_empty(chip->irq_trig_level_low, gc->ngpio)) { 999 if (bitmap_empty(trigger, gc->ngpio) && 1000 bitmap_empty(int_stat, gc->ngpio)) 1001 return false; 1002 } 1003 1004 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 1005 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 1006 bitmap_or(edges, old_stat, cur_stat, gc->ngpio); 1007 bitmap_and(pending, edges, trigger, gc->ngpio); 1008 bitmap_or(pending, pending, int_stat, gc->ngpio); 1009 1010 bitmap_and(cur_stat, new_stat, chip->irq_trig_level_high, gc->ngpio); 1011 bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio); 1012 bitmap_or(pending, pending, cur_stat, gc->ngpio); 1013 1014 bitmap_andnot(cur_stat, reg_direction, new_stat, gc->ngpio); 1015 bitmap_and(old_stat, cur_stat, chip->irq_trig_level_low, gc->ngpio); 1016 bitmap_and(old_stat, old_stat, chip->irq_mask, gc->ngpio); 1017 bitmap_or(pending, pending, old_stat, gc->ngpio); 1018 1019 return !bitmap_empty(pending, gc->ngpio); 1020 } 1021 1022 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 1023 { 1024 struct pca953x_chip *chip = devid; 1025 struct gpio_chip *gc = &chip->gpio_chip; 1026 DECLARE_BITMAP(pending, MAX_LINE); 1027 int level; 1028 bool ret; 1029 1030 bitmap_zero(pending, MAX_LINE); 1031 1032 scoped_guard(mutex, &chip->i2c_lock) 1033 ret = pca953x_irq_pending(chip, pending); 1034 if (ret) { 1035 ret = 0; 1036 1037 for_each_set_bit(level, pending, gc->ngpio) { 1038 int nested_irq = irq_find_mapping(gc->irq.domain, level); 1039 1040 if (unlikely(nested_irq <= 0)) { 1041 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1042 continue; 1043 } 1044 1045 handle_nested_irq(nested_irq); 1046 ret = 1; 1047 } 1048 } 1049 1050 return IRQ_RETVAL(ret); 1051 } 1052 1053 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1054 { 1055 struct i2c_client *client = chip->client; 1056 struct device *dev = &client->dev; 1057 DECLARE_BITMAP(reg_direction, MAX_LINE); 1058 DECLARE_BITMAP(irq_stat, MAX_LINE); 1059 struct gpio_chip *gc = &chip->gpio_chip; 1060 struct gpio_irq_chip *girq; 1061 int ret; 1062 1063 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 1064 ret = pca953x_acpi_get_irq(dev); 1065 if (ret > 0) 1066 client->irq = ret; 1067 } 1068 1069 if (!client->irq) 1070 return 0; 1071 1072 if (irq_base == -1) 1073 return 0; 1074 1075 if (!(chip->driver_data & PCA_INT)) 1076 return 0; 1077 1078 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 1079 if (ret) 1080 return ret; 1081 1082 /* 1083 * There is no way to know which GPIO line generated the 1084 * interrupt. We have to rely on the previous read for 1085 * this purpose. 1086 */ 1087 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 1088 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 1089 mutex_init(&chip->irq_lock); 1090 1091 girq = &chip->gpio_chip.irq; 1092 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 1093 /* This will let us handle the parent IRQ in the driver */ 1094 girq->parent_handler = NULL; 1095 girq->num_parents = 0; 1096 girq->parents = NULL; 1097 girq->default_type = IRQ_TYPE_NONE; 1098 girq->handler = handle_simple_irq; 1099 girq->threaded = true; 1100 girq->first = irq_base; /* FIXME: get rid of this */ 1101 1102 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 1103 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 1104 chip); 1105 if (ret) 1106 return dev_err_probe(dev, ret, "failed to request irq\n"); 1107 1108 return 0; 1109 } 1110 1111 #else /* CONFIG_GPIO_PCA953X_IRQ */ 1112 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1113 { 1114 struct i2c_client *client = chip->client; 1115 struct device *dev = &client->dev; 1116 1117 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 1118 dev_warn(dev, "interrupt support not compiled in\n"); 1119 1120 return 0; 1121 } 1122 #endif 1123 1124 static int device_pca95xx_init(struct pca953x_chip *chip) 1125 { 1126 DECLARE_BITMAP(val, MAX_LINE); 1127 u8 regaddr; 1128 int ret; 1129 1130 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1131 ret = regcache_sync_region(chip->regmap, regaddr, 1132 regaddr + NBANK(chip) - 1); 1133 if (ret) 1134 return ret; 1135 1136 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1137 ret = regcache_sync_region(chip->regmap, regaddr, 1138 regaddr + NBANK(chip) - 1); 1139 if (ret) 1140 return ret; 1141 1142 /* clear polarity inversion */ 1143 bitmap_zero(val, MAX_LINE); 1144 1145 return pca953x_write_regs(chip, chip->regs->invert, val); 1146 } 1147 1148 static int device_pca957x_init(struct pca953x_chip *chip) 1149 { 1150 DECLARE_BITMAP(val, MAX_LINE); 1151 unsigned int i; 1152 int ret; 1153 1154 ret = device_pca95xx_init(chip); 1155 if (ret) 1156 return ret; 1157 1158 /* To enable register 6, 7 to control pull up and pull down */ 1159 for (i = 0; i < NBANK(chip); i++) 1160 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1161 1162 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1163 } 1164 1165 static void pca953x_disable_regulator(void *reg) 1166 { 1167 regulator_disable(reg); 1168 } 1169 1170 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1171 { 1172 struct device *dev = &chip->client->dev; 1173 struct regulator *reg = chip->regulator; 1174 int ret; 1175 1176 reg = devm_regulator_get(dev, "vcc"); 1177 if (IS_ERR(reg)) 1178 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1179 1180 ret = regulator_enable(reg); 1181 if (ret) 1182 return dev_err_probe(dev, ret, "reg en err\n"); 1183 1184 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1185 if (ret) 1186 return ret; 1187 1188 chip->regulator = reg; 1189 return 0; 1190 } 1191 1192 static int pca953x_probe(struct i2c_client *client) 1193 { 1194 struct device *dev = &client->dev; 1195 struct pca953x_platform_data *pdata; 1196 struct pca953x_chip *chip; 1197 int irq_base; 1198 int ret; 1199 const struct regmap_config *regmap_config; 1200 1201 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1202 if (chip == NULL) 1203 return -ENOMEM; 1204 1205 pdata = dev_get_platdata(dev); 1206 if (pdata) { 1207 irq_base = pdata->irq_base; 1208 chip->gpio_start = pdata->gpio_base; 1209 } else { 1210 struct gpio_desc *reset_gpio; 1211 1212 chip->gpio_start = -1; 1213 irq_base = 0; 1214 1215 /* 1216 * See if we need to de-assert a reset pin. 1217 * 1218 * There is no known ACPI-enabled platforms that are 1219 * using "reset" GPIO. Otherwise any of those platform 1220 * must use _DSD method with corresponding property. 1221 */ 1222 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1223 if (IS_ERR(reset_gpio)) 1224 return dev_err_probe(dev, PTR_ERR(reset_gpio), 1225 "Failed to get reset gpio\n"); 1226 } 1227 1228 chip->client = client; 1229 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1230 if (!chip->driver_data) 1231 return -ENODEV; 1232 1233 ret = pca953x_get_and_enable_regulator(chip); 1234 if (ret) 1235 return ret; 1236 1237 i2c_set_clientdata(client, chip); 1238 1239 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1240 1241 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1242 dev_info(dev, "using auto increment\n"); 1243 regmap_config = &pca953x_ai_i2c_regmap; 1244 } else { 1245 dev_info(dev, "using no auto increment\n"); 1246 regmap_config = &pca953x_i2c_regmap; 1247 } 1248 1249 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1250 case PCAL653X_TYPE: 1251 chip->recalc_addr = pcal6534_recalc_addr; 1252 chip->check_reg = pcal6534_check_register; 1253 break; 1254 case TCA6418_TYPE: 1255 chip->recalc_addr = tca6418_recalc_addr; 1256 /* 1257 * We don't assign chip->check_reg = tca6418_check_register directly here. 1258 * Instead, the wrappers handle the dispatch based on PCA_CHIP_TYPE. 1259 */ 1260 break; 1261 default: 1262 chip->recalc_addr = pca953x_recalc_addr; 1263 chip->check_reg = pca953x_check_register; 1264 break; 1265 } 1266 1267 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1268 if (IS_ERR(chip->regmap)) 1269 return PTR_ERR(chip->regmap); 1270 1271 regcache_mark_dirty(chip->regmap); 1272 1273 mutex_init(&chip->i2c_lock); 1274 /* 1275 * In case we have an i2c-mux controlled by a GPIO provided by an 1276 * expander using the same driver higher on the device tree, read the 1277 * i2c adapter nesting depth and use the retrieved value as lockdep 1278 * subclass for chip->i2c_lock. 1279 * 1280 * REVISIT: This solution is not complete. It protects us from lockdep 1281 * false positives when the expander controlling the i2c-mux is on 1282 * a different level on the device tree, but not when it's on the same 1283 * level on a different branch (in which case the subclass number 1284 * would be the same). 1285 * 1286 * TODO: Once a correct solution is developed, a similar fix should be 1287 * applied to all other i2c-controlled GPIO expanders (and potentially 1288 * regmap-i2c). 1289 */ 1290 lockdep_set_subclass(&chip->i2c_lock, 1291 i2c_adapter_depth(client->adapter)); 1292 1293 /* 1294 * initialize cached registers from their original values. 1295 * we can't share this chip with another i2c master. 1296 */ 1297 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1298 case PCA957X_TYPE: 1299 chip->regs = &pca957x_regs; 1300 ret = device_pca957x_init(chip); 1301 break; 1302 case TCA6418_TYPE: 1303 chip->regs = &tca6418_regs; 1304 break; 1305 default: 1306 chip->regs = &pca953x_regs; 1307 ret = device_pca95xx_init(chip); 1308 break; 1309 } 1310 if (ret) 1311 return ret; 1312 1313 ret = pca953x_irq_setup(chip, irq_base); 1314 if (ret) 1315 return ret; 1316 1317 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1318 } 1319 1320 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1321 { 1322 struct device *dev = &chip->client->dev; 1323 int ret; 1324 u8 regaddr; 1325 1326 /* 1327 * The ordering between direction and output is important, 1328 * sync these registers first and only then sync the rest. 1329 */ 1330 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1331 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1332 if (ret) { 1333 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1334 return ret; 1335 } 1336 1337 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1338 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1339 if (ret) { 1340 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1341 return ret; 1342 } 1343 1344 #ifdef CONFIG_GPIO_PCA953X_IRQ 1345 if (chip->driver_data & PCA_PCAL) { 1346 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1347 ret = regcache_sync_region(chip->regmap, regaddr, 1348 regaddr + NBANK(chip) - 1); 1349 if (ret) { 1350 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1351 ret); 1352 return ret; 1353 } 1354 1355 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1356 ret = regcache_sync_region(chip->regmap, regaddr, 1357 regaddr + NBANK(chip) - 1); 1358 if (ret) { 1359 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1360 ret); 1361 return ret; 1362 } 1363 } 1364 #endif 1365 1366 return 0; 1367 } 1368 1369 static int pca953x_restore_context(struct pca953x_chip *chip) 1370 { 1371 int ret; 1372 1373 guard(mutex)(&chip->i2c_lock); 1374 1375 if (chip->client->irq > 0) 1376 enable_irq(chip->client->irq); 1377 regcache_cache_only(chip->regmap, false); 1378 regcache_mark_dirty(chip->regmap); 1379 ret = pca953x_regcache_sync(chip); 1380 if (ret) 1381 goto err; 1382 1383 ret = regcache_sync(chip->regmap); 1384 if (ret) 1385 goto err; 1386 1387 return 0; 1388 1389 err: 1390 if (chip->client->irq > 0) 1391 disable_irq(chip->client->irq); 1392 regcache_cache_only(chip->regmap, true); 1393 1394 return ret; 1395 } 1396 1397 static void pca953x_save_context(struct pca953x_chip *chip) 1398 { 1399 guard(mutex)(&chip->i2c_lock); 1400 1401 /* Disable IRQ to prevent early triggering while regmap "cache only" is on */ 1402 if (chip->client->irq > 0) 1403 disable_irq(chip->client->irq); 1404 regcache_cache_only(chip->regmap, true); 1405 } 1406 1407 static int pca953x_suspend(struct device *dev) 1408 { 1409 struct pca953x_chip *chip = dev_get_drvdata(dev); 1410 1411 pca953x_save_context(chip); 1412 1413 if (atomic_read(&chip->wakeup_path)) 1414 device_set_wakeup_path(dev); 1415 else 1416 regulator_disable(chip->regulator); 1417 1418 return 0; 1419 } 1420 1421 static int pca953x_resume(struct device *dev) 1422 { 1423 struct pca953x_chip *chip = dev_get_drvdata(dev); 1424 int ret; 1425 1426 if (!atomic_read(&chip->wakeup_path)) { 1427 ret = regulator_enable(chip->regulator); 1428 if (ret) { 1429 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1430 return ret; 1431 } 1432 } 1433 1434 ret = pca953x_restore_context(chip); 1435 if (ret) 1436 dev_err(dev, "Failed to restore register map: %d\n", ret); 1437 1438 return ret; 1439 } 1440 1441 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1442 1443 /* convenience to stop overlong match-table lines */ 1444 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1445 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1446 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1447 1448 static const struct of_device_id pca953x_dt_ids[] = { 1449 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1450 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1451 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1452 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1453 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1454 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1455 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1456 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1457 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1458 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1459 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1460 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1461 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1462 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1463 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1464 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1465 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1466 1467 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1468 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1469 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1470 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1471 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1472 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1473 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1474 1475 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1476 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1477 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1478 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1479 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1480 1481 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1482 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1483 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1484 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1485 { .compatible = "ti,tca6418", .data = (void *)(18 | TCA6418_TYPE | PCA_INT), }, 1486 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1487 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1488 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1489 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1490 1491 { .compatible = "ti,tcal6408", .data = OF_953X( 8, PCA_LATCH_INT), }, 1492 { .compatible = "ti,tcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1493 1494 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1495 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1496 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1497 1498 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1499 { } 1500 }; 1501 1502 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1503 1504 static struct i2c_driver pca953x_driver = { 1505 .driver = { 1506 .name = "pca953x", 1507 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1508 .of_match_table = pca953x_dt_ids, 1509 .acpi_match_table = pca953x_acpi_ids, 1510 }, 1511 .probe = pca953x_probe, 1512 .id_table = pca953x_id, 1513 }; 1514 1515 static int __init pca953x_init(void) 1516 { 1517 return i2c_add_driver(&pca953x_driver); 1518 } 1519 1520 /* 1521 * register after i2c postcore initcall and before 1522 * subsys initcalls that may rely on these GPIOs 1523 */ 1524 subsys_initcall(pca953x_init); 1525 1526 static void __exit pca953x_exit(void) 1527 { 1528 i2c_del_driver(&pca953x_driver); 1529 } 1530 module_exit(pca953x_exit); 1531 1532 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1533 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1534 MODULE_LICENSE("GPL"); 1535