1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * PCA953x 4/8/16/24/40 bit I/O ports 4 * 5 * Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com> 6 * Copyright (C) 2007 Marvell International Ltd. 7 * 8 * Derived from drivers/i2c/chips/pca9539.c 9 */ 10 11 #include <linux/atomic.h> 12 #include <linux/bitmap.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/errno.h> 16 #include <linux/i2c.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/module.h> 22 #include <linux/mutex.h> 23 #include <linux/pm.h> 24 #include <linux/regmap.h> 25 #include <linux/regulator/consumer.h> 26 #include <linux/seq_file.h> 27 #include <linux/slab.h> 28 29 #include <linux/gpio/consumer.h> 30 #include <linux/gpio/driver.h> 31 32 #include <linux/pinctrl/pinconf-generic.h> 33 34 #include <linux/platform_data/pca953x.h> 35 36 #define PCA953X_INPUT 0x00 37 #define PCA953X_OUTPUT 0x01 38 #define PCA953X_INVERT 0x02 39 #define PCA953X_DIRECTION 0x03 40 41 #define TCA6418_INPUT 0x14 42 #define TCA6418_OUTPUT 0x17 43 #define TCA6418_DIRECTION 0x23 44 45 #define REG_ADDR_MASK GENMASK(5, 0) 46 #define REG_ADDR_EXT BIT(6) 47 #define REG_ADDR_AI BIT(7) 48 49 #define PCA957X_IN 0x00 50 #define PCA957X_INVRT 0x01 51 #define PCA957X_BKEN 0x02 52 #define PCA957X_PUPD 0x03 53 #define PCA957X_CFG 0x04 54 #define PCA957X_OUT 0x05 55 #define PCA957X_MSK 0x06 56 #define PCA957X_INTS 0x07 57 58 #define PCAL953X_OUT_STRENGTH 0x20 59 #define PCAL953X_IN_LATCH 0x22 60 #define PCAL953X_PULL_EN 0x23 61 #define PCAL953X_PULL_SEL 0x24 62 #define PCAL953X_INT_MASK 0x25 63 #define PCAL953X_INT_STAT 0x26 64 #define PCAL953X_OUT_CONF 0x27 65 66 #define PCAL6524_INT_EDGE 0x28 67 #define PCAL6524_INT_CLR 0x2a 68 #define PCAL6524_IN_STATUS 0x2b 69 #define PCAL6524_OUT_INDCONF 0x2c 70 #define PCAL6524_DEBOUNCE 0x2d 71 72 #define PCA_GPIO_MASK GENMASK(7, 0) 73 74 #define PCAL_GPIO_MASK GENMASK(4, 0) 75 #define PCAL_PINCTRL_MASK GENMASK(6, 5) 76 77 #define PCA_INT BIT(8) 78 #define PCA_PCAL BIT(9) 79 #define PCA_LATCH_INT (PCA_PCAL | PCA_INT) 80 #define PCA953X_TYPE BIT(12) 81 #define PCA957X_TYPE BIT(13) 82 #define PCAL653X_TYPE BIT(14) 83 #define TCA6418_TYPE BIT(16) 84 #define PCA_TYPE_MASK GENMASK(16, 12) 85 86 #define PCA_CHIP_TYPE(x) ((x) & PCA_TYPE_MASK) 87 88 static const struct i2c_device_id pca953x_id[] = { 89 { "pca6408", 8 | PCA953X_TYPE | PCA_INT, }, 90 { "pca6416", 16 | PCA953X_TYPE | PCA_INT, }, 91 { "pca9505", 40 | PCA953X_TYPE | PCA_INT, }, 92 { "pca9506", 40 | PCA953X_TYPE | PCA_INT, }, 93 { "pca9534", 8 | PCA953X_TYPE | PCA_INT, }, 94 { "pca9535", 16 | PCA953X_TYPE | PCA_INT, }, 95 { "pca9536", 4 | PCA953X_TYPE, }, 96 { "pca9537", 4 | PCA953X_TYPE | PCA_INT, }, 97 { "pca9538", 8 | PCA953X_TYPE | PCA_INT, }, 98 { "pca9539", 16 | PCA953X_TYPE | PCA_INT, }, 99 { "pca9554", 8 | PCA953X_TYPE | PCA_INT, }, 100 { "pca9555", 16 | PCA953X_TYPE | PCA_INT, }, 101 { "pca9556", 8 | PCA953X_TYPE, }, 102 { "pca9557", 8 | PCA953X_TYPE, }, 103 { "pca9574", 8 | PCA957X_TYPE | PCA_INT, }, 104 { "pca9575", 16 | PCA957X_TYPE | PCA_INT, }, 105 { "pca9698", 40 | PCA953X_TYPE, }, 106 107 { "pcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 108 { "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 109 { "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, }, 110 { "pcal6534", 34 | PCAL653X_TYPE | PCA_LATCH_INT, }, 111 { "pcal9535", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 112 { "pcal9554b", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 113 { "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 114 115 { "max7310", 8 | PCA953X_TYPE, }, 116 { "max7312", 16 | PCA953X_TYPE | PCA_INT, }, 117 { "max7313", 16 | PCA953X_TYPE | PCA_INT, }, 118 { "max7315", 8 | PCA953X_TYPE | PCA_INT, }, 119 { "max7318", 16 | PCA953X_TYPE | PCA_INT, }, 120 { "pca6107", 8 | PCA953X_TYPE | PCA_INT, }, 121 { "tca6408", 8 | PCA953X_TYPE | PCA_INT, }, 122 { "tca6416", 16 | PCA953X_TYPE | PCA_INT, }, 123 { "tca6418", 18 | TCA6418_TYPE | PCA_INT, }, 124 { "tca6424", 24 | PCA953X_TYPE | PCA_INT, }, 125 { "tca9538", 8 | PCA953X_TYPE | PCA_INT, }, 126 { "tca9539", 16 | PCA953X_TYPE | PCA_INT, }, 127 { "tca9554", 8 | PCA953X_TYPE | PCA_INT, }, 128 { "xra1202", 8 | PCA953X_TYPE }, 129 130 { "tcal6408", 8 | PCA953X_TYPE | PCA_LATCH_INT, }, 131 { "tcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 132 { } 133 }; 134 MODULE_DEVICE_TABLE(i2c, pca953x_id); 135 136 #ifdef CONFIG_GPIO_PCA953X_IRQ 137 138 #include <linux/acpi.h> 139 #include <linux/dmi.h> 140 141 static const struct acpi_gpio_params pca953x_irq_gpios = { 0, 0, true }; 142 143 static const struct acpi_gpio_mapping pca953x_acpi_irq_gpios[] = { 144 { "irq-gpios", &pca953x_irq_gpios, 1, ACPI_GPIO_QUIRK_ABSOLUTE_NUMBER }, 145 { } 146 }; 147 148 static int pca953x_acpi_get_irq(struct device *dev) 149 { 150 int ret; 151 152 ret = devm_acpi_dev_add_driver_gpios(dev, pca953x_acpi_irq_gpios); 153 if (ret) 154 dev_warn(dev, "can't add GPIO ACPI mapping\n"); 155 156 ret = acpi_dev_gpio_irq_get_by(ACPI_COMPANION(dev), "irq", 0); 157 if (ret < 0) 158 return ret; 159 160 dev_info(dev, "ACPI interrupt quirk (IRQ %d)\n", ret); 161 return ret; 162 } 163 164 static const struct dmi_system_id pca953x_dmi_acpi_irq_info[] = { 165 { 166 /* 167 * On Intel Galileo Gen 2 board the IRQ pin of one of 168 * the I²C GPIO expanders, which has GpioInt() resource, 169 * is provided as an absolute number instead of being 170 * relative. Since first controller (gpio-sch.c) and 171 * second (gpio-dwapb.c) are at the fixed bases, we may 172 * safely refer to the number in the global space to get 173 * an IRQ out of it. 174 */ 175 .matches = { 176 DMI_EXACT_MATCH(DMI_BOARD_NAME, "GalileoGen2"), 177 }, 178 }, 179 {} 180 }; 181 #endif 182 183 static const struct acpi_device_id pca953x_acpi_ids[] = { 184 { "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, }, 185 { } 186 }; 187 MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids); 188 189 #define MAX_BANK 5 190 #define BANK_SZ 8 191 #define MAX_LINE (MAX_BANK * BANK_SZ) 192 193 #define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ) 194 195 struct pca953x_reg_config { 196 int direction; 197 int output; 198 int input; 199 int invert; 200 }; 201 202 static const struct pca953x_reg_config pca953x_regs = { 203 .direction = PCA953X_DIRECTION, 204 .output = PCA953X_OUTPUT, 205 .input = PCA953X_INPUT, 206 .invert = PCA953X_INVERT, 207 }; 208 209 static const struct pca953x_reg_config pca957x_regs = { 210 .direction = PCA957X_CFG, 211 .output = PCA957X_OUT, 212 .input = PCA957X_IN, 213 .invert = PCA957X_INVRT, 214 }; 215 216 static const struct pca953x_reg_config tca6418_regs = { 217 .direction = TCA6418_DIRECTION, 218 .output = TCA6418_OUTPUT, 219 .input = TCA6418_INPUT, 220 .invert = 0xFF, /* Does not apply */ 221 }; 222 223 struct pca953x_chip { 224 unsigned gpio_start; 225 struct mutex i2c_lock; 226 struct regmap *regmap; 227 228 #ifdef CONFIG_GPIO_PCA953X_IRQ 229 struct mutex irq_lock; 230 DECLARE_BITMAP(irq_mask, MAX_LINE); 231 DECLARE_BITMAP(irq_stat, MAX_LINE); 232 DECLARE_BITMAP(irq_trig_raise, MAX_LINE); 233 DECLARE_BITMAP(irq_trig_fall, MAX_LINE); 234 DECLARE_BITMAP(irq_trig_level_high, MAX_LINE); 235 DECLARE_BITMAP(irq_trig_level_low, MAX_LINE); 236 #endif 237 atomic_t wakeup_path; 238 239 struct i2c_client *client; 240 struct gpio_chip gpio_chip; 241 unsigned long driver_data; 242 struct regulator *regulator; 243 244 const struct pca953x_reg_config *regs; 245 246 u8 (*recalc_addr)(struct pca953x_chip *chip, int reg, int off); 247 bool (*check_reg)(struct pca953x_chip *chip, unsigned int reg, 248 u32 checkbank); 249 }; 250 251 static int pca953x_bank_shift(struct pca953x_chip *chip) 252 { 253 return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ); 254 } 255 256 /* 257 * Helper function to get the correct bit mask for a given offset and chip type. 258 * The TCA6418's input, output, and direction banks have a peculiar bit order: 259 * the first byte uses reversed bit order, while the second byte uses standard order. 260 */ 261 static inline u8 pca953x_get_bit_mask(struct pca953x_chip *chip, unsigned int offset) 262 { 263 unsigned int bit_pos_in_bank = offset % BANK_SZ; 264 int msb = BANK_SZ - 1; 265 266 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE && offset <= msb) 267 return BIT(msb - bit_pos_in_bank); 268 269 return BIT(bit_pos_in_bank); 270 } 271 272 #define PCA953x_BANK_INPUT BIT(0) 273 #define PCA953x_BANK_OUTPUT BIT(1) 274 #define PCA953x_BANK_POLARITY BIT(2) 275 #define PCA953x_BANK_CONFIG BIT(3) 276 277 #define PCA957x_BANK_INPUT BIT(0) 278 #define PCA957x_BANK_POLARITY BIT(1) 279 #define PCA957x_BANK_BUSHOLD BIT(2) 280 #define PCA957x_BANK_CONFIG BIT(4) 281 #define PCA957x_BANK_OUTPUT BIT(5) 282 283 #define PCAL9xxx_BANK_IN_LATCH BIT(8 + 2) 284 #define PCAL9xxx_BANK_PULL_EN BIT(8 + 3) 285 #define PCAL9xxx_BANK_PULL_SEL BIT(8 + 4) 286 #define PCAL9xxx_BANK_IRQ_MASK BIT(8 + 5) 287 #define PCAL9xxx_BANK_IRQ_STAT BIT(8 + 6) 288 289 /* 290 * We care about the following registers: 291 * - Standard set, below 0x40, each port can be replicated up to 8 times 292 * - PCA953x standard 293 * Input port 0x00 + 0 * bank_size R 294 * Output port 0x00 + 1 * bank_size RW 295 * Polarity Inversion port 0x00 + 2 * bank_size RW 296 * Configuration port 0x00 + 3 * bank_size RW 297 * - PCA957x with mixed up registers 298 * Input port 0x00 + 0 * bank_size R 299 * Polarity Inversion port 0x00 + 1 * bank_size RW 300 * Bus hold port 0x00 + 2 * bank_size RW 301 * Configuration port 0x00 + 4 * bank_size RW 302 * Output port 0x00 + 5 * bank_size RW 303 * 304 * - Extended set, above 0x40, often chip specific. 305 * - PCAL6524/PCAL9555A with custom PCAL IRQ handling: 306 * Input latch register 0x40 + 2 * bank_size RW 307 * Pull-up/pull-down enable reg 0x40 + 3 * bank_size RW 308 * Pull-up/pull-down select reg 0x40 + 4 * bank_size RW 309 * Interrupt mask register 0x40 + 5 * bank_size RW 310 * Interrupt status register 0x40 + 6 * bank_size R 311 * 312 * - Registers with bit 0x80 set, the AI bit (auto increment) 313 * The bit is cleared and the registers fall into one of the 314 * categories above. 315 */ 316 317 static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg, 318 u32 checkbank) 319 { 320 int bank_shift = pca953x_bank_shift(chip); 321 int bank = (reg & REG_ADDR_MASK) >> bank_shift; 322 int offset = reg & (BIT(bank_shift) - 1); 323 324 /* Special PCAL extended register check. */ 325 if (reg & REG_ADDR_EXT) { 326 if (!(chip->driver_data & PCA_PCAL)) 327 return false; 328 bank += 8; 329 } 330 331 /* Register is not in the matching bank. */ 332 if (!(BIT(bank) & checkbank)) 333 return false; 334 335 /* Register is not within allowed range of bank. */ 336 if (offset >= NBANK(chip)) 337 return false; 338 339 return true; 340 } 341 342 /* 343 * Unfortunately, whilst the PCAL6534 chip (and compatibles) broadly follow the 344 * same register layout as the PCAL6524, the spacing of the registers has been 345 * fundamentally altered by compacting them and thus does not obey the same 346 * rules, including being able to use bit shifting to determine bank. These 347 * chips hence need special handling here. 348 */ 349 static bool pcal6534_check_register(struct pca953x_chip *chip, unsigned int reg, 350 u32 checkbank) 351 { 352 int bank_shift; 353 int bank; 354 int offset; 355 356 if (reg >= 0x54) { 357 /* 358 * Handle lack of reserved registers after output port 359 * configuration register to form a bank. 360 */ 361 reg -= 0x54; 362 bank_shift = 16; 363 } else if (reg >= 0x30) { 364 /* 365 * Reserved block between 14h and 2Fh does not align on 366 * expected bank boundaries like other devices. 367 */ 368 reg -= 0x30; 369 bank_shift = 8; 370 } else { 371 bank_shift = 0; 372 } 373 374 bank = bank_shift + reg / NBANK(chip); 375 offset = reg % NBANK(chip); 376 377 /* Register is not in the matching bank. */ 378 if (!(BIT(bank) & checkbank)) 379 return false; 380 381 /* Register is not within allowed range of bank. */ 382 if (offset >= NBANK(chip)) 383 return false; 384 385 return true; 386 } 387 388 /* TCA6418 breaks the PCA953x register order rule */ 389 static bool tca6418_check_register(struct pca953x_chip *chip, unsigned int reg, 390 u32 access_type_mask) 391 { 392 /* Valid Input Registers - BIT(0) for readable access */ 393 if (reg >= TCA6418_INPUT && reg < (TCA6418_INPUT + NBANK(chip))) 394 return (access_type_mask & BIT(0)); 395 396 /* Valid Output Registers - BIT(1) for writeable access */ 397 if (reg >= TCA6418_OUTPUT && reg < (TCA6418_OUTPUT + NBANK(chip))) 398 return (access_type_mask & (BIT(0) | BIT(1))); 399 400 /* Valid Direction Registers - BIT(2) for volatile access */ 401 if (reg >= TCA6418_DIRECTION && reg < (TCA6418_DIRECTION + NBANK(chip))) 402 return (access_type_mask & (BIT(0) | BIT(1))); 403 404 return false; 405 } 406 407 static bool pca953x_readable_register(struct device *dev, unsigned int reg) 408 { 409 struct pca953x_chip *chip = dev_get_drvdata(dev); 410 u32 bank; 411 412 switch (PCA_CHIP_TYPE(chip->driver_data)) { 413 case PCA957X_TYPE: 414 bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT | 415 PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG | 416 PCA957x_BANK_BUSHOLD; 417 break; 418 case TCA6418_TYPE: 419 /* BIT(0) to indicate read access */ 420 return tca6418_check_register(chip, reg, BIT(0)); 421 default: 422 bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT | 423 PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG; 424 break; 425 } 426 427 if (chip->driver_data & PCA_PCAL) { 428 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 429 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK | 430 PCAL9xxx_BANK_IRQ_STAT; 431 } 432 433 return chip->check_reg(chip, reg, bank); 434 } 435 436 static bool pca953x_writeable_register(struct device *dev, unsigned int reg) 437 { 438 struct pca953x_chip *chip = dev_get_drvdata(dev); 439 u32 bank; 440 441 switch (PCA_CHIP_TYPE(chip->driver_data)) { 442 case PCA957X_TYPE: 443 bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY | 444 PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD; 445 break; 446 case TCA6418_TYPE: 447 /* BIT(1) for write access */ 448 return tca6418_check_register(chip, reg, BIT(1)); 449 default: 450 bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY | 451 PCA953x_BANK_CONFIG; 452 break; 453 } 454 455 if (chip->driver_data & PCA_PCAL) 456 bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN | 457 PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK; 458 459 return chip->check_reg(chip, reg, bank); 460 } 461 462 static bool pca953x_volatile_register(struct device *dev, unsigned int reg) 463 { 464 struct pca953x_chip *chip = dev_get_drvdata(dev); 465 u32 bank; 466 467 switch (PCA_CHIP_TYPE(chip->driver_data)) { 468 case PCA957X_TYPE: 469 bank = PCA957x_BANK_INPUT; 470 break; 471 case TCA6418_TYPE: 472 /* BIT(2) for volatile access */ 473 return tca6418_check_register(chip, reg, BIT(2)); 474 default: 475 bank = PCA953x_BANK_INPUT; 476 break; 477 } 478 479 if (chip->driver_data & PCA_PCAL) 480 bank |= PCAL9xxx_BANK_IRQ_STAT; 481 482 return chip->check_reg(chip, reg, bank); 483 } 484 485 static const struct regmap_config pca953x_i2c_regmap = { 486 .reg_bits = 8, 487 .val_bits = 8, 488 489 .use_single_read = true, 490 .use_single_write = true, 491 492 .readable_reg = pca953x_readable_register, 493 .writeable_reg = pca953x_writeable_register, 494 .volatile_reg = pca953x_volatile_register, 495 496 .disable_locking = true, 497 .cache_type = REGCACHE_MAPLE, 498 .max_register = 0x7f, 499 }; 500 501 static const struct regmap_config pca953x_ai_i2c_regmap = { 502 .reg_bits = 8, 503 .val_bits = 8, 504 505 .read_flag_mask = REG_ADDR_AI, 506 .write_flag_mask = REG_ADDR_AI, 507 508 .readable_reg = pca953x_readable_register, 509 .writeable_reg = pca953x_writeable_register, 510 .volatile_reg = pca953x_volatile_register, 511 512 .disable_locking = true, 513 .cache_type = REGCACHE_MAPLE, 514 .max_register = 0x7f, 515 }; 516 517 static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off) 518 { 519 int bank_shift = pca953x_bank_shift(chip); 520 int addr = (reg & PCAL_GPIO_MASK) << bank_shift; 521 int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1; 522 u8 regaddr = pinctrl | addr | (off / BANK_SZ); 523 524 return regaddr; 525 } 526 527 /* 528 * The PCAL6534 and compatible chips have altered bank alignment that doesn't 529 * fit within the bit shifting scheme used for other devices. 530 */ 531 static u8 pcal6534_recalc_addr(struct pca953x_chip *chip, int reg, int off) 532 { 533 int addr; 534 int pinctrl; 535 536 addr = (reg & PCAL_GPIO_MASK) * NBANK(chip); 537 538 switch (reg) { 539 case PCAL953X_OUT_STRENGTH: 540 case PCAL953X_IN_LATCH: 541 case PCAL953X_PULL_EN: 542 case PCAL953X_PULL_SEL: 543 case PCAL953X_INT_MASK: 544 case PCAL953X_INT_STAT: 545 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x20; 546 break; 547 case PCAL6524_INT_EDGE: 548 case PCAL6524_INT_CLR: 549 case PCAL6524_IN_STATUS: 550 case PCAL6524_OUT_INDCONF: 551 case PCAL6524_DEBOUNCE: 552 pinctrl = ((reg & PCAL_PINCTRL_MASK) >> 1) + 0x1c; 553 break; 554 default: 555 pinctrl = 0; 556 break; 557 } 558 559 return pinctrl + addr + (off / BANK_SZ); 560 } 561 562 static u8 tca6418_recalc_addr(struct pca953x_chip *chip, int reg_base, int offset) 563 { 564 /* 565 * reg_base will be TCA6418_INPUT, TCA6418_OUTPUT, or TCA6418_DIRECTION 566 * offset is the global GPIO line offset (0-17) 567 * BANK_SZ is 8 for TCA6418 (8 bits per register bank) 568 */ 569 return reg_base + (offset / BANK_SZ); 570 } 571 572 static int pca953x_write_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 573 { 574 u8 regaddr = chip->recalc_addr(chip, reg, 0); 575 u8 value[MAX_BANK]; 576 int i, ret; 577 578 for (i = 0; i < NBANK(chip); i++) 579 value[i] = bitmap_get_value8(val, i * BANK_SZ); 580 581 ret = regmap_bulk_write(chip->regmap, regaddr, value, NBANK(chip)); 582 if (ret < 0) { 583 dev_err(&chip->client->dev, "failed writing register: %d\n", ret); 584 return ret; 585 } 586 587 return 0; 588 } 589 590 static int pca953x_read_regs(struct pca953x_chip *chip, int reg, unsigned long *val) 591 { 592 u8 regaddr = chip->recalc_addr(chip, reg, 0); 593 u8 value[MAX_BANK]; 594 int i, ret; 595 596 ret = regmap_bulk_read(chip->regmap, regaddr, value, NBANK(chip)); 597 if (ret < 0) { 598 dev_err(&chip->client->dev, "failed reading register: %d\n", ret); 599 return ret; 600 } 601 602 for (i = 0; i < NBANK(chip); i++) 603 bitmap_set_value8(val, value[i], i * BANK_SZ); 604 605 return 0; 606 } 607 608 static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off) 609 { 610 struct pca953x_chip *chip = gpiochip_get_data(gc); 611 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 612 u8 bit = pca953x_get_bit_mask(chip, off); 613 614 guard(mutex)(&chip->i2c_lock); 615 616 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 617 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 618 619 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 620 } 621 622 static int pca953x_gpio_direction_output(struct gpio_chip *gc, 623 unsigned off, int val) 624 { 625 struct pca953x_chip *chip = gpiochip_get_data(gc); 626 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 627 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 628 u8 bit = pca953x_get_bit_mask(chip, off); 629 int ret; 630 631 guard(mutex)(&chip->i2c_lock); 632 633 /* set output level */ 634 ret = regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 635 if (ret) 636 return ret; 637 638 /* 639 * then direction 640 * (in/out logic is inverted on TCA6418) 641 */ 642 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 643 return regmap_update_bits(chip->regmap, dirreg, bit, bit); 644 645 return regmap_update_bits(chip->regmap, dirreg, bit, 0); 646 } 647 648 static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off) 649 { 650 struct pca953x_chip *chip = gpiochip_get_data(gc); 651 u8 inreg = chip->recalc_addr(chip, chip->regs->input, off); 652 u8 bit = pca953x_get_bit_mask(chip, off); 653 u32 reg_val; 654 int ret; 655 656 scoped_guard(mutex, &chip->i2c_lock) 657 ret = regmap_read(chip->regmap, inreg, ®_val); 658 if (ret < 0) 659 return ret; 660 661 return !!(reg_val & bit); 662 } 663 664 static int pca953x_gpio_set_value(struct gpio_chip *gc, unsigned int off, 665 int val) 666 { 667 struct pca953x_chip *chip = gpiochip_get_data(gc); 668 u8 outreg = chip->recalc_addr(chip, chip->regs->output, off); 669 u8 bit = pca953x_get_bit_mask(chip, off); 670 671 guard(mutex)(&chip->i2c_lock); 672 673 return regmap_update_bits(chip->regmap, outreg, bit, val ? bit : 0); 674 } 675 676 static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off) 677 { 678 struct pca953x_chip *chip = gpiochip_get_data(gc); 679 u8 dirreg = chip->recalc_addr(chip, chip->regs->direction, off); 680 u8 bit = pca953x_get_bit_mask(chip, off); 681 u32 reg_val; 682 int ret; 683 684 scoped_guard(mutex, &chip->i2c_lock) 685 ret = regmap_read(chip->regmap, dirreg, ®_val); 686 if (ret < 0) 687 return ret; 688 689 /* (in/out logic is inverted on TCA6418) */ 690 if (reg_val & bit) { 691 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 692 return GPIO_LINE_DIRECTION_OUT; 693 694 return GPIO_LINE_DIRECTION_IN; 695 } 696 if (PCA_CHIP_TYPE(chip->driver_data) == TCA6418_TYPE) 697 return GPIO_LINE_DIRECTION_IN; 698 699 return GPIO_LINE_DIRECTION_OUT; 700 } 701 702 static int pca953x_gpio_get_multiple(struct gpio_chip *gc, 703 unsigned long *mask, unsigned long *bits) 704 { 705 struct pca953x_chip *chip = gpiochip_get_data(gc); 706 DECLARE_BITMAP(reg_val, MAX_LINE); 707 int ret; 708 709 scoped_guard(mutex, &chip->i2c_lock) 710 ret = pca953x_read_regs(chip, chip->regs->input, reg_val); 711 if (ret) 712 return ret; 713 714 bitmap_replace(bits, bits, reg_val, mask, gc->ngpio); 715 return 0; 716 } 717 718 static int pca953x_gpio_set_multiple(struct gpio_chip *gc, 719 unsigned long *mask, unsigned long *bits) 720 { 721 struct pca953x_chip *chip = gpiochip_get_data(gc); 722 DECLARE_BITMAP(reg_val, MAX_LINE); 723 int ret; 724 725 guard(mutex)(&chip->i2c_lock); 726 727 ret = pca953x_read_regs(chip, chip->regs->output, reg_val); 728 if (ret) 729 return ret; 730 731 bitmap_replace(reg_val, reg_val, bits, mask, gc->ngpio); 732 733 return pca953x_write_regs(chip, chip->regs->output, reg_val); 734 } 735 736 static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip, 737 unsigned int offset, 738 unsigned long config) 739 { 740 enum pin_config_param param = pinconf_to_config_param(config); 741 u8 pull_en_reg = chip->recalc_addr(chip, PCAL953X_PULL_EN, offset); 742 u8 pull_sel_reg = chip->recalc_addr(chip, PCAL953X_PULL_SEL, offset); 743 u8 bit = BIT(offset % BANK_SZ); 744 int ret; 745 746 /* 747 * pull-up/pull-down configuration requires PCAL extended 748 * registers 749 */ 750 if (!(chip->driver_data & PCA_PCAL)) 751 return -ENOTSUPP; 752 753 guard(mutex)(&chip->i2c_lock); 754 755 /* Configure pull-up/pull-down */ 756 if (param == PIN_CONFIG_BIAS_PULL_UP) 757 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, bit); 758 else if (param == PIN_CONFIG_BIAS_PULL_DOWN) 759 ret = regmap_update_bits(chip->regmap, pull_sel_reg, bit, 0); 760 else 761 ret = 0; 762 if (ret) 763 return ret; 764 765 /* Disable/Enable pull-up/pull-down */ 766 if (param == PIN_CONFIG_BIAS_DISABLE) 767 return regmap_update_bits(chip->regmap, pull_en_reg, bit, 0); 768 else 769 return regmap_update_bits(chip->regmap, pull_en_reg, bit, bit); 770 } 771 772 static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset, 773 unsigned long config) 774 { 775 struct pca953x_chip *chip = gpiochip_get_data(gc); 776 777 switch (pinconf_to_config_param(config)) { 778 case PIN_CONFIG_BIAS_PULL_UP: 779 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 780 case PIN_CONFIG_BIAS_PULL_DOWN: 781 case PIN_CONFIG_BIAS_DISABLE: 782 return pca953x_gpio_set_pull_up_down(chip, offset, config); 783 default: 784 return -ENOTSUPP; 785 } 786 } 787 788 static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios) 789 { 790 struct gpio_chip *gc = &chip->gpio_chip; 791 792 gc->direction_input = pca953x_gpio_direction_input; 793 gc->direction_output = pca953x_gpio_direction_output; 794 gc->get = pca953x_gpio_get_value; 795 gc->set = pca953x_gpio_set_value; 796 gc->get_direction = pca953x_gpio_get_direction; 797 gc->get_multiple = pca953x_gpio_get_multiple; 798 gc->set_multiple = pca953x_gpio_set_multiple; 799 gc->set_config = pca953x_gpio_set_config; 800 gc->can_sleep = true; 801 802 gc->base = chip->gpio_start; 803 gc->ngpio = gpios; 804 gc->label = dev_name(&chip->client->dev); 805 gc->parent = &chip->client->dev; 806 gc->owner = THIS_MODULE; 807 } 808 809 #ifdef CONFIG_GPIO_PCA953X_IRQ 810 static void pca953x_irq_mask(struct irq_data *d) 811 { 812 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 813 struct pca953x_chip *chip = gpiochip_get_data(gc); 814 irq_hw_number_t hwirq = irqd_to_hwirq(d); 815 816 clear_bit(hwirq, chip->irq_mask); 817 gpiochip_disable_irq(gc, hwirq); 818 } 819 820 static void pca953x_irq_unmask(struct irq_data *d) 821 { 822 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 823 struct pca953x_chip *chip = gpiochip_get_data(gc); 824 irq_hw_number_t hwirq = irqd_to_hwirq(d); 825 826 gpiochip_enable_irq(gc, hwirq); 827 set_bit(hwirq, chip->irq_mask); 828 } 829 830 static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on) 831 { 832 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 833 struct pca953x_chip *chip = gpiochip_get_data(gc); 834 835 if (on) 836 atomic_inc(&chip->wakeup_path); 837 else 838 atomic_dec(&chip->wakeup_path); 839 840 return irq_set_irq_wake(chip->client->irq, on); 841 } 842 843 static void pca953x_irq_bus_lock(struct irq_data *d) 844 { 845 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 846 struct pca953x_chip *chip = gpiochip_get_data(gc); 847 848 mutex_lock(&chip->irq_lock); 849 } 850 851 static void pca953x_irq_bus_sync_unlock(struct irq_data *d) 852 { 853 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 854 struct pca953x_chip *chip = gpiochip_get_data(gc); 855 DECLARE_BITMAP(irq_mask, MAX_LINE); 856 DECLARE_BITMAP(reg_direction, MAX_LINE); 857 int level; 858 859 if (chip->driver_data & PCA_PCAL) { 860 DECLARE_BITMAP(latched_inputs, MAX_LINE); 861 guard(mutex)(&chip->i2c_lock); 862 863 /* Enable latch on edge-triggered interrupt-enabled inputs */ 864 bitmap_or(latched_inputs, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 865 bitmap_and(latched_inputs, latched_inputs, chip->irq_mask, gc->ngpio); 866 pca953x_write_regs(chip, PCAL953X_IN_LATCH, latched_inputs); 867 868 bitmap_complement(irq_mask, chip->irq_mask, gc->ngpio); 869 870 /* Unmask enabled interrupts */ 871 pca953x_write_regs(chip, PCAL953X_INT_MASK, irq_mask); 872 } 873 874 /* Switch direction to input if needed */ 875 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 876 877 bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio); 878 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_high, gc->ngpio); 879 bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_low, gc->ngpio); 880 bitmap_complement(reg_direction, reg_direction, gc->ngpio); 881 bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio); 882 883 /* Look for any newly setup interrupt */ 884 for_each_set_bit(level, irq_mask, gc->ngpio) 885 pca953x_gpio_direction_input(&chip->gpio_chip, level); 886 887 mutex_unlock(&chip->irq_lock); 888 } 889 890 static int pca953x_irq_set_type(struct irq_data *d, unsigned int type) 891 { 892 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 893 struct pca953x_chip *chip = gpiochip_get_data(gc); 894 struct device *dev = &chip->client->dev; 895 irq_hw_number_t hwirq = irqd_to_hwirq(d); 896 897 if (!(type & IRQ_TYPE_SENSE_MASK)) { 898 dev_err(dev, "irq %d: unsupported type %d\n", d->irq, type); 899 return -EINVAL; 900 } 901 902 assign_bit(hwirq, chip->irq_trig_fall, type & IRQ_TYPE_EDGE_FALLING); 903 assign_bit(hwirq, chip->irq_trig_raise, type & IRQ_TYPE_EDGE_RISING); 904 assign_bit(hwirq, chip->irq_trig_level_low, type & IRQ_TYPE_LEVEL_LOW); 905 assign_bit(hwirq, chip->irq_trig_level_high, type & IRQ_TYPE_LEVEL_HIGH); 906 907 return 0; 908 } 909 910 static void pca953x_irq_shutdown(struct irq_data *d) 911 { 912 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 913 struct pca953x_chip *chip = gpiochip_get_data(gc); 914 irq_hw_number_t hwirq = irqd_to_hwirq(d); 915 916 clear_bit(hwirq, chip->irq_trig_raise); 917 clear_bit(hwirq, chip->irq_trig_fall); 918 clear_bit(hwirq, chip->irq_trig_level_low); 919 clear_bit(hwirq, chip->irq_trig_level_high); 920 921 pca953x_irq_mask(d); 922 } 923 924 static void pca953x_irq_print_chip(struct irq_data *data, struct seq_file *p) 925 { 926 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 927 928 seq_puts(p, dev_name(gc->parent)); 929 } 930 931 static const struct irq_chip pca953x_irq_chip = { 932 .irq_mask = pca953x_irq_mask, 933 .irq_unmask = pca953x_irq_unmask, 934 .irq_set_wake = pca953x_irq_set_wake, 935 .irq_bus_lock = pca953x_irq_bus_lock, 936 .irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock, 937 .irq_set_type = pca953x_irq_set_type, 938 .irq_shutdown = pca953x_irq_shutdown, 939 .irq_print_chip = pca953x_irq_print_chip, 940 .flags = IRQCHIP_IMMUTABLE, 941 GPIOCHIP_IRQ_RESOURCE_HELPERS, 942 }; 943 944 static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pending) 945 { 946 struct gpio_chip *gc = &chip->gpio_chip; 947 DECLARE_BITMAP(reg_direction, MAX_LINE); 948 DECLARE_BITMAP(old_stat, MAX_LINE); 949 DECLARE_BITMAP(cur_stat, MAX_LINE); 950 DECLARE_BITMAP(new_stat, MAX_LINE); 951 DECLARE_BITMAP(int_stat, MAX_LINE); 952 DECLARE_BITMAP(trigger, MAX_LINE); 953 DECLARE_BITMAP(edges, MAX_LINE); 954 int ret; 955 956 if (chip->driver_data & PCA_PCAL) { 957 /* Read INT_STAT before it is cleared by the input-port read. */ 958 ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, int_stat); 959 if (ret) 960 return false; 961 } 962 963 ret = pca953x_read_regs(chip, chip->regs->input, cur_stat); 964 if (ret) 965 return false; 966 967 if (chip->driver_data & PCA_PCAL) { 968 /* Detect short pulses via INT_STAT. */ 969 bitmap_and(trigger, int_stat, chip->irq_mask, gc->ngpio); 970 971 /* Apply filter for rising/falling edge selection. */ 972 bitmap_replace(new_stat, chip->irq_trig_fall, chip->irq_trig_raise, 973 cur_stat, gc->ngpio); 974 975 bitmap_and(int_stat, new_stat, trigger, gc->ngpio); 976 } else { 977 bitmap_zero(int_stat, gc->ngpio); 978 } 979 980 /* Remove output pins from the equation */ 981 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 982 983 bitmap_copy(old_stat, chip->irq_stat, gc->ngpio); 984 985 bitmap_and(new_stat, cur_stat, reg_direction, gc->ngpio); 986 bitmap_xor(cur_stat, new_stat, old_stat, gc->ngpio); 987 bitmap_and(trigger, cur_stat, chip->irq_mask, gc->ngpio); 988 989 bitmap_copy(chip->irq_stat, new_stat, gc->ngpio); 990 991 if (bitmap_empty(chip->irq_trig_level_high, gc->ngpio) && 992 bitmap_empty(chip->irq_trig_level_low, gc->ngpio)) { 993 if (bitmap_empty(trigger, gc->ngpio) && 994 bitmap_empty(int_stat, gc->ngpio)) 995 return false; 996 } 997 998 bitmap_and(cur_stat, chip->irq_trig_fall, old_stat, gc->ngpio); 999 bitmap_and(old_stat, chip->irq_trig_raise, new_stat, gc->ngpio); 1000 bitmap_or(edges, old_stat, cur_stat, gc->ngpio); 1001 bitmap_and(pending, edges, trigger, gc->ngpio); 1002 bitmap_or(pending, pending, int_stat, gc->ngpio); 1003 1004 bitmap_and(cur_stat, new_stat, chip->irq_trig_level_high, gc->ngpio); 1005 bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio); 1006 bitmap_or(pending, pending, cur_stat, gc->ngpio); 1007 1008 bitmap_complement(cur_stat, new_stat, gc->ngpio); 1009 bitmap_and(cur_stat, cur_stat, reg_direction, gc->ngpio); 1010 bitmap_and(old_stat, cur_stat, chip->irq_trig_level_low, gc->ngpio); 1011 bitmap_and(old_stat, old_stat, chip->irq_mask, gc->ngpio); 1012 bitmap_or(pending, pending, old_stat, gc->ngpio); 1013 1014 return !bitmap_empty(pending, gc->ngpio); 1015 } 1016 1017 static irqreturn_t pca953x_irq_handler(int irq, void *devid) 1018 { 1019 struct pca953x_chip *chip = devid; 1020 struct gpio_chip *gc = &chip->gpio_chip; 1021 DECLARE_BITMAP(pending, MAX_LINE); 1022 int level; 1023 bool ret; 1024 1025 bitmap_zero(pending, MAX_LINE); 1026 1027 scoped_guard(mutex, &chip->i2c_lock) 1028 ret = pca953x_irq_pending(chip, pending); 1029 if (ret) { 1030 ret = 0; 1031 1032 for_each_set_bit(level, pending, gc->ngpio) { 1033 int nested_irq = irq_find_mapping(gc->irq.domain, level); 1034 1035 if (unlikely(nested_irq <= 0)) { 1036 dev_warn_ratelimited(gc->parent, "unmapped interrupt %d\n", level); 1037 continue; 1038 } 1039 1040 handle_nested_irq(nested_irq); 1041 ret = 1; 1042 } 1043 } 1044 1045 return IRQ_RETVAL(ret); 1046 } 1047 1048 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1049 { 1050 struct i2c_client *client = chip->client; 1051 struct device *dev = &client->dev; 1052 DECLARE_BITMAP(reg_direction, MAX_LINE); 1053 DECLARE_BITMAP(irq_stat, MAX_LINE); 1054 struct gpio_chip *gc = &chip->gpio_chip; 1055 struct gpio_irq_chip *girq; 1056 int ret; 1057 1058 if (dmi_first_match(pca953x_dmi_acpi_irq_info)) { 1059 ret = pca953x_acpi_get_irq(dev); 1060 if (ret > 0) 1061 client->irq = ret; 1062 } 1063 1064 if (!client->irq) 1065 return 0; 1066 1067 if (irq_base == -1) 1068 return 0; 1069 1070 if (!(chip->driver_data & PCA_INT)) 1071 return 0; 1072 1073 ret = pca953x_read_regs(chip, chip->regs->input, irq_stat); 1074 if (ret) 1075 return ret; 1076 1077 /* 1078 * There is no way to know which GPIO line generated the 1079 * interrupt. We have to rely on the previous read for 1080 * this purpose. 1081 */ 1082 pca953x_read_regs(chip, chip->regs->direction, reg_direction); 1083 bitmap_and(chip->irq_stat, irq_stat, reg_direction, gc->ngpio); 1084 mutex_init(&chip->irq_lock); 1085 1086 girq = &chip->gpio_chip.irq; 1087 gpio_irq_chip_set_chip(girq, &pca953x_irq_chip); 1088 /* This will let us handle the parent IRQ in the driver */ 1089 girq->parent_handler = NULL; 1090 girq->num_parents = 0; 1091 girq->parents = NULL; 1092 girq->default_type = IRQ_TYPE_NONE; 1093 girq->handler = handle_simple_irq; 1094 girq->threaded = true; 1095 girq->first = irq_base; /* FIXME: get rid of this */ 1096 1097 ret = devm_request_threaded_irq(dev, client->irq, NULL, pca953x_irq_handler, 1098 IRQF_ONESHOT | IRQF_SHARED, dev_name(dev), 1099 chip); 1100 if (ret) 1101 return dev_err_probe(dev, ret, "failed to request irq\n"); 1102 1103 return 0; 1104 } 1105 1106 #else /* CONFIG_GPIO_PCA953X_IRQ */ 1107 static int pca953x_irq_setup(struct pca953x_chip *chip, int irq_base) 1108 { 1109 struct i2c_client *client = chip->client; 1110 struct device *dev = &client->dev; 1111 1112 if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT)) 1113 dev_warn(dev, "interrupt support not compiled in\n"); 1114 1115 return 0; 1116 } 1117 #endif 1118 1119 static int device_pca95xx_init(struct pca953x_chip *chip) 1120 { 1121 DECLARE_BITMAP(val, MAX_LINE); 1122 u8 regaddr; 1123 int ret; 1124 1125 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1126 ret = regcache_sync_region(chip->regmap, regaddr, 1127 regaddr + NBANK(chip) - 1); 1128 if (ret) 1129 return ret; 1130 1131 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1132 ret = regcache_sync_region(chip->regmap, regaddr, 1133 regaddr + NBANK(chip) - 1); 1134 if (ret) 1135 return ret; 1136 1137 /* clear polarity inversion */ 1138 bitmap_zero(val, MAX_LINE); 1139 1140 return pca953x_write_regs(chip, chip->regs->invert, val); 1141 } 1142 1143 static int device_pca957x_init(struct pca953x_chip *chip) 1144 { 1145 DECLARE_BITMAP(val, MAX_LINE); 1146 unsigned int i; 1147 int ret; 1148 1149 ret = device_pca95xx_init(chip); 1150 if (ret) 1151 return ret; 1152 1153 /* To enable register 6, 7 to control pull up and pull down */ 1154 for (i = 0; i < NBANK(chip); i++) 1155 bitmap_set_value8(val, 0x02, i * BANK_SZ); 1156 1157 return pca953x_write_regs(chip, PCA957X_BKEN, val); 1158 } 1159 1160 static void pca953x_disable_regulator(void *reg) 1161 { 1162 regulator_disable(reg); 1163 } 1164 1165 static int pca953x_get_and_enable_regulator(struct pca953x_chip *chip) 1166 { 1167 struct device *dev = &chip->client->dev; 1168 struct regulator *reg = chip->regulator; 1169 int ret; 1170 1171 reg = devm_regulator_get(dev, "vcc"); 1172 if (IS_ERR(reg)) 1173 return dev_err_probe(dev, PTR_ERR(reg), "reg get err\n"); 1174 1175 ret = regulator_enable(reg); 1176 if (ret) 1177 return dev_err_probe(dev, ret, "reg en err\n"); 1178 1179 ret = devm_add_action_or_reset(dev, pca953x_disable_regulator, reg); 1180 if (ret) 1181 return ret; 1182 1183 chip->regulator = reg; 1184 return 0; 1185 } 1186 1187 static int pca953x_probe(struct i2c_client *client) 1188 { 1189 struct device *dev = &client->dev; 1190 struct pca953x_platform_data *pdata; 1191 struct pca953x_chip *chip; 1192 int irq_base; 1193 int ret; 1194 const struct regmap_config *regmap_config; 1195 1196 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 1197 if (chip == NULL) 1198 return -ENOMEM; 1199 1200 pdata = dev_get_platdata(dev); 1201 if (pdata) { 1202 irq_base = pdata->irq_base; 1203 chip->gpio_start = pdata->gpio_base; 1204 } else { 1205 struct gpio_desc *reset_gpio; 1206 1207 chip->gpio_start = -1; 1208 irq_base = 0; 1209 1210 /* 1211 * See if we need to de-assert a reset pin. 1212 * 1213 * There is no known ACPI-enabled platforms that are 1214 * using "reset" GPIO. Otherwise any of those platform 1215 * must use _DSD method with corresponding property. 1216 */ 1217 reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1218 if (IS_ERR(reset_gpio)) 1219 return dev_err_probe(dev, PTR_ERR(reset_gpio), 1220 "Failed to get reset gpio\n"); 1221 } 1222 1223 chip->client = client; 1224 chip->driver_data = (uintptr_t)i2c_get_match_data(client); 1225 if (!chip->driver_data) 1226 return -ENODEV; 1227 1228 ret = pca953x_get_and_enable_regulator(chip); 1229 if (ret) 1230 return ret; 1231 1232 i2c_set_clientdata(client, chip); 1233 1234 pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK); 1235 1236 if (NBANK(chip) > 2 || PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE) { 1237 dev_info(dev, "using auto increment\n"); 1238 regmap_config = &pca953x_ai_i2c_regmap; 1239 } else { 1240 dev_info(dev, "using no auto increment\n"); 1241 regmap_config = &pca953x_i2c_regmap; 1242 } 1243 1244 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1245 case PCAL653X_TYPE: 1246 chip->recalc_addr = pcal6534_recalc_addr; 1247 chip->check_reg = pcal6534_check_register; 1248 break; 1249 case TCA6418_TYPE: 1250 chip->recalc_addr = tca6418_recalc_addr; 1251 /* 1252 * We don't assign chip->check_reg = tca6418_check_register directly here. 1253 * Instead, the wrappers handle the dispatch based on PCA_CHIP_TYPE. 1254 */ 1255 break; 1256 default: 1257 chip->recalc_addr = pca953x_recalc_addr; 1258 chip->check_reg = pca953x_check_register; 1259 break; 1260 } 1261 1262 chip->regmap = devm_regmap_init_i2c(client, regmap_config); 1263 if (IS_ERR(chip->regmap)) 1264 return PTR_ERR(chip->regmap); 1265 1266 regcache_mark_dirty(chip->regmap); 1267 1268 mutex_init(&chip->i2c_lock); 1269 /* 1270 * In case we have an i2c-mux controlled by a GPIO provided by an 1271 * expander using the same driver higher on the device tree, read the 1272 * i2c adapter nesting depth and use the retrieved value as lockdep 1273 * subclass for chip->i2c_lock. 1274 * 1275 * REVISIT: This solution is not complete. It protects us from lockdep 1276 * false positives when the expander controlling the i2c-mux is on 1277 * a different level on the device tree, but not when it's on the same 1278 * level on a different branch (in which case the subclass number 1279 * would be the same). 1280 * 1281 * TODO: Once a correct solution is developed, a similar fix should be 1282 * applied to all other i2c-controlled GPIO expanders (and potentially 1283 * regmap-i2c). 1284 */ 1285 lockdep_set_subclass(&chip->i2c_lock, 1286 i2c_adapter_depth(client->adapter)); 1287 1288 /* 1289 * initialize cached registers from their original values. 1290 * we can't share this chip with another i2c master. 1291 */ 1292 switch (PCA_CHIP_TYPE(chip->driver_data)) { 1293 case PCA957X_TYPE: 1294 chip->regs = &pca957x_regs; 1295 ret = device_pca957x_init(chip); 1296 break; 1297 case TCA6418_TYPE: 1298 chip->regs = &tca6418_regs; 1299 break; 1300 default: 1301 chip->regs = &pca953x_regs; 1302 ret = device_pca95xx_init(chip); 1303 break; 1304 } 1305 if (ret) 1306 return ret; 1307 1308 ret = pca953x_irq_setup(chip, irq_base); 1309 if (ret) 1310 return ret; 1311 1312 return devm_gpiochip_add_data(dev, &chip->gpio_chip, chip); 1313 } 1314 1315 static int pca953x_regcache_sync(struct pca953x_chip *chip) 1316 { 1317 struct device *dev = &chip->client->dev; 1318 int ret; 1319 u8 regaddr; 1320 1321 /* 1322 * The ordering between direction and output is important, 1323 * sync these registers first and only then sync the rest. 1324 */ 1325 regaddr = chip->recalc_addr(chip, chip->regs->direction, 0); 1326 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1327 if (ret) { 1328 dev_err(dev, "Failed to sync GPIO dir registers: %d\n", ret); 1329 return ret; 1330 } 1331 1332 regaddr = chip->recalc_addr(chip, chip->regs->output, 0); 1333 ret = regcache_sync_region(chip->regmap, regaddr, regaddr + NBANK(chip) - 1); 1334 if (ret) { 1335 dev_err(dev, "Failed to sync GPIO out registers: %d\n", ret); 1336 return ret; 1337 } 1338 1339 #ifdef CONFIG_GPIO_PCA953X_IRQ 1340 if (chip->driver_data & PCA_PCAL) { 1341 regaddr = chip->recalc_addr(chip, PCAL953X_IN_LATCH, 0); 1342 ret = regcache_sync_region(chip->regmap, regaddr, 1343 regaddr + NBANK(chip) - 1); 1344 if (ret) { 1345 dev_err(dev, "Failed to sync INT latch registers: %d\n", 1346 ret); 1347 return ret; 1348 } 1349 1350 regaddr = chip->recalc_addr(chip, PCAL953X_INT_MASK, 0); 1351 ret = regcache_sync_region(chip->regmap, regaddr, 1352 regaddr + NBANK(chip) - 1); 1353 if (ret) { 1354 dev_err(dev, "Failed to sync INT mask registers: %d\n", 1355 ret); 1356 return ret; 1357 } 1358 } 1359 #endif 1360 1361 return 0; 1362 } 1363 1364 static int pca953x_restore_context(struct pca953x_chip *chip) 1365 { 1366 int ret; 1367 1368 guard(mutex)(&chip->i2c_lock); 1369 1370 if (chip->client->irq > 0) 1371 enable_irq(chip->client->irq); 1372 regcache_cache_only(chip->regmap, false); 1373 regcache_mark_dirty(chip->regmap); 1374 ret = pca953x_regcache_sync(chip); 1375 if (ret) 1376 return ret; 1377 1378 return regcache_sync(chip->regmap); 1379 } 1380 1381 static void pca953x_save_context(struct pca953x_chip *chip) 1382 { 1383 guard(mutex)(&chip->i2c_lock); 1384 1385 /* Disable IRQ to prevent early triggering while regmap "cache only" is on */ 1386 if (chip->client->irq > 0) 1387 disable_irq(chip->client->irq); 1388 regcache_cache_only(chip->regmap, true); 1389 } 1390 1391 static int pca953x_suspend(struct device *dev) 1392 { 1393 struct pca953x_chip *chip = dev_get_drvdata(dev); 1394 1395 pca953x_save_context(chip); 1396 1397 if (atomic_read(&chip->wakeup_path)) 1398 device_set_wakeup_path(dev); 1399 else 1400 regulator_disable(chip->regulator); 1401 1402 return 0; 1403 } 1404 1405 static int pca953x_resume(struct device *dev) 1406 { 1407 struct pca953x_chip *chip = dev_get_drvdata(dev); 1408 int ret; 1409 1410 if (!atomic_read(&chip->wakeup_path)) { 1411 ret = regulator_enable(chip->regulator); 1412 if (ret) { 1413 dev_err(dev, "Failed to enable regulator: %d\n", ret); 1414 return 0; 1415 } 1416 } 1417 1418 ret = pca953x_restore_context(chip); 1419 if (ret) 1420 dev_err(dev, "Failed to restore register map: %d\n", ret); 1421 1422 return ret; 1423 } 1424 1425 static DEFINE_SIMPLE_DEV_PM_OPS(pca953x_pm_ops, pca953x_suspend, pca953x_resume); 1426 1427 /* convenience to stop overlong match-table lines */ 1428 #define OF_653X(__nrgpio, __int) ((void *)(__nrgpio | PCAL653X_TYPE | __int)) 1429 #define OF_953X(__nrgpio, __int) (void *)(__nrgpio | PCA953X_TYPE | __int) 1430 #define OF_957X(__nrgpio, __int) (void *)(__nrgpio | PCA957X_TYPE | __int) 1431 1432 static const struct of_device_id pca953x_dt_ids[] = { 1433 { .compatible = "nxp,pca6408", .data = OF_953X(8, PCA_INT), }, 1434 { .compatible = "nxp,pca6416", .data = OF_953X(16, PCA_INT), }, 1435 { .compatible = "nxp,pca9505", .data = OF_953X(40, PCA_INT), }, 1436 { .compatible = "nxp,pca9506", .data = OF_953X(40, PCA_INT), }, 1437 { .compatible = "nxp,pca9534", .data = OF_953X( 8, PCA_INT), }, 1438 { .compatible = "nxp,pca9535", .data = OF_953X(16, PCA_INT), }, 1439 { .compatible = "nxp,pca9536", .data = OF_953X( 4, 0), }, 1440 { .compatible = "nxp,pca9537", .data = OF_953X( 4, PCA_INT), }, 1441 { .compatible = "nxp,pca9538", .data = OF_953X( 8, PCA_INT), }, 1442 { .compatible = "nxp,pca9539", .data = OF_953X(16, PCA_INT), }, 1443 { .compatible = "nxp,pca9554", .data = OF_953X( 8, PCA_INT), }, 1444 { .compatible = "nxp,pca9555", .data = OF_953X(16, PCA_INT), }, 1445 { .compatible = "nxp,pca9556", .data = OF_953X( 8, 0), }, 1446 { .compatible = "nxp,pca9557", .data = OF_953X( 8, 0), }, 1447 { .compatible = "nxp,pca9574", .data = OF_957X( 8, PCA_INT), }, 1448 { .compatible = "nxp,pca9575", .data = OF_957X(16, PCA_INT), }, 1449 { .compatible = "nxp,pca9698", .data = OF_953X(40, 0), }, 1450 1451 { .compatible = "nxp,pcal6408", .data = OF_953X(8, PCA_LATCH_INT), }, 1452 { .compatible = "nxp,pcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1453 { .compatible = "nxp,pcal6524", .data = OF_953X(24, PCA_LATCH_INT), }, 1454 { .compatible = "nxp,pcal6534", .data = OF_653X(34, PCA_LATCH_INT), }, 1455 { .compatible = "nxp,pcal9535", .data = OF_953X(16, PCA_LATCH_INT), }, 1456 { .compatible = "nxp,pcal9554b", .data = OF_953X( 8, PCA_LATCH_INT), }, 1457 { .compatible = "nxp,pcal9555a", .data = OF_953X(16, PCA_LATCH_INT), }, 1458 1459 { .compatible = "maxim,max7310", .data = OF_953X( 8, 0), }, 1460 { .compatible = "maxim,max7312", .data = OF_953X(16, PCA_INT), }, 1461 { .compatible = "maxim,max7313", .data = OF_953X(16, PCA_INT), }, 1462 { .compatible = "maxim,max7315", .data = OF_953X( 8, PCA_INT), }, 1463 { .compatible = "maxim,max7318", .data = OF_953X(16, PCA_INT), }, 1464 1465 { .compatible = "ti,pca6107", .data = OF_953X( 8, PCA_INT), }, 1466 { .compatible = "ti,pca9536", .data = OF_953X( 4, 0), }, 1467 { .compatible = "ti,tca6408", .data = OF_953X( 8, PCA_INT), }, 1468 { .compatible = "ti,tca6416", .data = OF_953X(16, PCA_INT), }, 1469 { .compatible = "ti,tca6418", .data = (void *)(18 | TCA6418_TYPE | PCA_INT), }, 1470 { .compatible = "ti,tca6424", .data = OF_953X(24, PCA_INT), }, 1471 { .compatible = "ti,tca9535", .data = OF_953X(16, PCA_INT), }, 1472 { .compatible = "ti,tca9538", .data = OF_953X( 8, PCA_INT), }, 1473 { .compatible = "ti,tca9539", .data = OF_953X(16, PCA_INT), }, 1474 1475 { .compatible = "ti,tcal6408", .data = OF_953X( 8, PCA_LATCH_INT), }, 1476 { .compatible = "ti,tcal6416", .data = OF_953X(16, PCA_LATCH_INT), }, 1477 1478 { .compatible = "onnn,cat9554", .data = OF_953X( 8, PCA_INT), }, 1479 { .compatible = "onnn,pca9654", .data = OF_953X( 8, PCA_INT), }, 1480 { .compatible = "onnn,pca9655", .data = OF_953X(16, PCA_INT), }, 1481 1482 { .compatible = "exar,xra1202", .data = OF_953X( 8, 0), }, 1483 { } 1484 }; 1485 1486 MODULE_DEVICE_TABLE(of, pca953x_dt_ids); 1487 1488 static struct i2c_driver pca953x_driver = { 1489 .driver = { 1490 .name = "pca953x", 1491 .pm = pm_sleep_ptr(&pca953x_pm_ops), 1492 .of_match_table = pca953x_dt_ids, 1493 .acpi_match_table = pca953x_acpi_ids, 1494 }, 1495 .probe = pca953x_probe, 1496 .id_table = pca953x_id, 1497 }; 1498 1499 static int __init pca953x_init(void) 1500 { 1501 return i2c_add_driver(&pca953x_driver); 1502 } 1503 1504 /* 1505 * register after i2c postcore initcall and before 1506 * subsys initcalls that may rely on these GPIOs 1507 */ 1508 subsys_initcall(pca953x_init); 1509 1510 static void __exit pca953x_exit(void) 1511 { 1512 i2c_del_driver(&pca953x_driver); 1513 } 1514 module_exit(pca953x_exit); 1515 1516 MODULE_AUTHOR("eric miao <eric.miao@marvell.com>"); 1517 MODULE_DESCRIPTION("GPIO expander driver for PCA953x"); 1518 MODULE_LICENSE("GPL"); 1519