1 /* 2 * Support functions for OMAP GPIO 3 * 4 * Copyright (C) 2003-2005 Nokia Corporation 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com> 6 * 7 * Copyright (C) 2009 Texas Instruments 8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/err.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/slab.h> 23 #include <linux/pm_runtime.h> 24 25 #include <mach/hardware.h> 26 #include <asm/irq.h> 27 #include <mach/irqs.h> 28 #include <asm/gpio.h> 29 #include <asm/mach/irq.h> 30 31 struct gpio_bank { 32 unsigned long pbase; 33 void __iomem *base; 34 u16 irq; 35 u16 virtual_irq_start; 36 int method; 37 u32 suspend_wakeup; 38 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 39 u32 saved_wakeup; 40 #endif 41 u32 non_wakeup_gpios; 42 u32 enabled_non_wakeup_gpios; 43 44 u32 saved_datain; 45 u32 saved_fallingdetect; 46 u32 saved_risingdetect; 47 u32 level_mask; 48 u32 toggle_mask; 49 spinlock_t lock; 50 struct gpio_chip chip; 51 struct clk *dbck; 52 u32 mod_usage; 53 u32 dbck_enable_mask; 54 struct device *dev; 55 bool dbck_flag; 56 int stride; 57 u32 width; 58 59 void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable); 60 61 struct omap_gpio_reg_offs *regs; 62 }; 63 64 #ifdef CONFIG_ARCH_OMAP3 65 struct omap3_gpio_regs { 66 u32 irqenable1; 67 u32 irqenable2; 68 u32 wake_en; 69 u32 ctrl; 70 u32 oe; 71 u32 leveldetect0; 72 u32 leveldetect1; 73 u32 risingdetect; 74 u32 fallingdetect; 75 u32 dataout; 76 }; 77 78 static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS]; 79 #endif 80 81 /* 82 * TODO: Cleanup gpio_bank usage as it is having information 83 * related to all instances of the device 84 */ 85 static struct gpio_bank *gpio_bank; 86 87 /* TODO: Analyze removing gpio_bank_count usage from driver code */ 88 int gpio_bank_count; 89 90 #define GPIO_INDEX(bank, gpio) (gpio % bank->width) 91 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) 92 93 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) 94 { 95 void __iomem *reg = bank->base; 96 u32 l; 97 98 reg += bank->regs->direction; 99 l = __raw_readl(reg); 100 if (is_input) 101 l |= 1 << gpio; 102 else 103 l &= ~(1 << gpio); 104 __raw_writel(l, reg); 105 } 106 107 108 /* set data out value using dedicate set/clear register */ 109 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable) 110 { 111 void __iomem *reg = bank->base; 112 u32 l = GPIO_BIT(bank, gpio); 113 114 if (enable) 115 reg += bank->regs->set_dataout; 116 else 117 reg += bank->regs->clr_dataout; 118 119 __raw_writel(l, reg); 120 } 121 122 /* set data out value using mask register */ 123 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable) 124 { 125 void __iomem *reg = bank->base + bank->regs->dataout; 126 u32 gpio_bit = GPIO_BIT(bank, gpio); 127 u32 l; 128 129 l = __raw_readl(reg); 130 if (enable) 131 l |= gpio_bit; 132 else 133 l &= ~gpio_bit; 134 __raw_writel(l, reg); 135 } 136 137 static int _get_gpio_datain(struct gpio_bank *bank, int gpio) 138 { 139 void __iomem *reg = bank->base + bank->regs->datain; 140 141 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 142 } 143 144 static int _get_gpio_dataout(struct gpio_bank *bank, int gpio) 145 { 146 void __iomem *reg = bank->base + bank->regs->dataout; 147 148 return (__raw_readl(reg) & GPIO_BIT(bank, gpio)) != 0; 149 } 150 151 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) 152 { 153 int l = __raw_readl(base + reg); 154 155 if (set) 156 l |= mask; 157 else 158 l &= ~mask; 159 160 __raw_writel(l, base + reg); 161 } 162 163 /** 164 * _set_gpio_debounce - low level gpio debounce time 165 * @bank: the gpio bank we're acting upon 166 * @gpio: the gpio number on this @gpio 167 * @debounce: debounce time to use 168 * 169 * OMAP's debounce time is in 31us steps so we need 170 * to convert and round up to the closest unit. 171 */ 172 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio, 173 unsigned debounce) 174 { 175 void __iomem *reg; 176 u32 val; 177 u32 l; 178 179 if (!bank->dbck_flag) 180 return; 181 182 if (debounce < 32) 183 debounce = 0x01; 184 else if (debounce > 7936) 185 debounce = 0xff; 186 else 187 debounce = (debounce / 0x1f) - 1; 188 189 l = GPIO_BIT(bank, gpio); 190 191 reg = bank->base + bank->regs->debounce; 192 __raw_writel(debounce, reg); 193 194 reg = bank->base + bank->regs->debounce_en; 195 val = __raw_readl(reg); 196 197 if (debounce) { 198 val |= l; 199 clk_enable(bank->dbck); 200 } else { 201 val &= ~l; 202 clk_disable(bank->dbck); 203 } 204 bank->dbck_enable_mask = val; 205 206 __raw_writel(val, reg); 207 } 208 209 #ifdef CONFIG_ARCH_OMAP2PLUS 210 static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio, 211 int trigger) 212 { 213 void __iomem *base = bank->base; 214 u32 gpio_bit = 1 << gpio; 215 216 if (cpu_is_omap44xx()) { 217 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT0, gpio_bit, 218 trigger & IRQ_TYPE_LEVEL_LOW); 219 _gpio_rmw(base, OMAP4_GPIO_LEVELDETECT1, gpio_bit, 220 trigger & IRQ_TYPE_LEVEL_HIGH); 221 _gpio_rmw(base, OMAP4_GPIO_RISINGDETECT, gpio_bit, 222 trigger & IRQ_TYPE_EDGE_RISING); 223 _gpio_rmw(base, OMAP4_GPIO_FALLINGDETECT, gpio_bit, 224 trigger & IRQ_TYPE_EDGE_FALLING); 225 } else { 226 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT0, gpio_bit, 227 trigger & IRQ_TYPE_LEVEL_LOW); 228 _gpio_rmw(base, OMAP24XX_GPIO_LEVELDETECT1, gpio_bit, 229 trigger & IRQ_TYPE_LEVEL_HIGH); 230 _gpio_rmw(base, OMAP24XX_GPIO_RISINGDETECT, gpio_bit, 231 trigger & IRQ_TYPE_EDGE_RISING); 232 _gpio_rmw(base, OMAP24XX_GPIO_FALLINGDETECT, gpio_bit, 233 trigger & IRQ_TYPE_EDGE_FALLING); 234 } 235 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 236 if (cpu_is_omap44xx()) { 237 _gpio_rmw(base, OMAP4_GPIO_IRQWAKEN0, gpio_bit, 238 trigger != 0); 239 } else { 240 /* 241 * GPIO wakeup request can only be generated on edge 242 * transitions 243 */ 244 if (trigger & IRQ_TYPE_EDGE_BOTH) 245 __raw_writel(1 << gpio, bank->base 246 + OMAP24XX_GPIO_SETWKUENA); 247 else 248 __raw_writel(1 << gpio, bank->base 249 + OMAP24XX_GPIO_CLEARWKUENA); 250 } 251 } 252 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 253 if (cpu_is_omap34xx() || cpu_is_omap44xx() || 254 (bank->non_wakeup_gpios & gpio_bit)) { 255 /* 256 * Log the edge gpio and manually trigger the IRQ 257 * after resume if the input level changes 258 * to avoid irq lost during PER RET/OFF mode 259 * Applies for omap2 non-wakeup gpio and all omap3 gpios 260 */ 261 if (trigger & IRQ_TYPE_EDGE_BOTH) 262 bank->enabled_non_wakeup_gpios |= gpio_bit; 263 else 264 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 265 } 266 267 if (cpu_is_omap44xx()) { 268 bank->level_mask = 269 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) | 270 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1); 271 } else { 272 bank->level_mask = 273 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) | 274 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 275 } 276 } 277 #endif 278 279 #ifdef CONFIG_ARCH_OMAP1 280 /* 281 * This only applies to chips that can't do both rising and falling edge 282 * detection at once. For all other chips, this function is a noop. 283 */ 284 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 285 { 286 void __iomem *reg = bank->base; 287 u32 l = 0; 288 289 switch (bank->method) { 290 case METHOD_MPUIO: 291 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; 292 break; 293 #ifdef CONFIG_ARCH_OMAP15XX 294 case METHOD_GPIO_1510: 295 reg += OMAP1510_GPIO_INT_CONTROL; 296 break; 297 #endif 298 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 299 case METHOD_GPIO_7XX: 300 reg += OMAP7XX_GPIO_INT_CONTROL; 301 break; 302 #endif 303 default: 304 return; 305 } 306 307 l = __raw_readl(reg); 308 if ((l >> gpio) & 1) 309 l &= ~(1 << gpio); 310 else 311 l |= 1 << gpio; 312 313 __raw_writel(l, reg); 314 } 315 #endif 316 317 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger) 318 { 319 void __iomem *reg = bank->base; 320 u32 l = 0; 321 322 switch (bank->method) { 323 #ifdef CONFIG_ARCH_OMAP1 324 case METHOD_MPUIO: 325 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride; 326 l = __raw_readl(reg); 327 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 328 bank->toggle_mask |= 1 << gpio; 329 if (trigger & IRQ_TYPE_EDGE_RISING) 330 l |= 1 << gpio; 331 else if (trigger & IRQ_TYPE_EDGE_FALLING) 332 l &= ~(1 << gpio); 333 else 334 goto bad; 335 break; 336 #endif 337 #ifdef CONFIG_ARCH_OMAP15XX 338 case METHOD_GPIO_1510: 339 reg += OMAP1510_GPIO_INT_CONTROL; 340 l = __raw_readl(reg); 341 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 342 bank->toggle_mask |= 1 << gpio; 343 if (trigger & IRQ_TYPE_EDGE_RISING) 344 l |= 1 << gpio; 345 else if (trigger & IRQ_TYPE_EDGE_FALLING) 346 l &= ~(1 << gpio); 347 else 348 goto bad; 349 break; 350 #endif 351 #ifdef CONFIG_ARCH_OMAP16XX 352 case METHOD_GPIO_1610: 353 if (gpio & 0x08) 354 reg += OMAP1610_GPIO_EDGE_CTRL2; 355 else 356 reg += OMAP1610_GPIO_EDGE_CTRL1; 357 gpio &= 0x07; 358 l = __raw_readl(reg); 359 l &= ~(3 << (gpio << 1)); 360 if (trigger & IRQ_TYPE_EDGE_RISING) 361 l |= 2 << (gpio << 1); 362 if (trigger & IRQ_TYPE_EDGE_FALLING) 363 l |= 1 << (gpio << 1); 364 if (trigger) 365 /* Enable wake-up during idle for dynamic tick */ 366 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA); 367 else 368 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA); 369 break; 370 #endif 371 #if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) 372 case METHOD_GPIO_7XX: 373 reg += OMAP7XX_GPIO_INT_CONTROL; 374 l = __raw_readl(reg); 375 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 376 bank->toggle_mask |= 1 << gpio; 377 if (trigger & IRQ_TYPE_EDGE_RISING) 378 l |= 1 << gpio; 379 else if (trigger & IRQ_TYPE_EDGE_FALLING) 380 l &= ~(1 << gpio); 381 else 382 goto bad; 383 break; 384 #endif 385 #ifdef CONFIG_ARCH_OMAP2PLUS 386 case METHOD_GPIO_24XX: 387 case METHOD_GPIO_44XX: 388 set_24xx_gpio_triggering(bank, gpio, trigger); 389 return 0; 390 #endif 391 default: 392 goto bad; 393 } 394 __raw_writel(l, reg); 395 return 0; 396 bad: 397 return -EINVAL; 398 } 399 400 static int gpio_irq_type(struct irq_data *d, unsigned type) 401 { 402 struct gpio_bank *bank; 403 unsigned gpio; 404 int retval; 405 unsigned long flags; 406 407 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE) 408 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE); 409 else 410 gpio = d->irq - IH_GPIO_BASE; 411 412 if (type & ~IRQ_TYPE_SENSE_MASK) 413 return -EINVAL; 414 415 /* OMAP1 allows only only edge triggering */ 416 if (!cpu_class_is_omap2() 417 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 418 return -EINVAL; 419 420 bank = irq_data_get_irq_chip_data(d); 421 spin_lock_irqsave(&bank->lock, flags); 422 retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type); 423 spin_unlock_irqrestore(&bank->lock, flags); 424 425 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 426 __irq_set_handler_locked(d->irq, handle_level_irq); 427 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 428 __irq_set_handler_locked(d->irq, handle_edge_irq); 429 430 return retval; 431 } 432 433 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 434 { 435 void __iomem *reg = bank->base; 436 437 reg += bank->regs->irqstatus; 438 __raw_writel(gpio_mask, reg); 439 440 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 441 if (bank->regs->irqstatus2) { 442 reg = bank->base + bank->regs->irqstatus2; 443 __raw_writel(gpio_mask, reg); 444 } 445 446 /* Flush posted write for the irq status to avoid spurious interrupts */ 447 __raw_readl(reg); 448 } 449 450 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio) 451 { 452 _clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 453 } 454 455 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank) 456 { 457 void __iomem *reg = bank->base; 458 u32 l; 459 u32 mask = (1 << bank->width) - 1; 460 461 reg += bank->regs->irqenable; 462 l = __raw_readl(reg); 463 if (bank->regs->irqenable_inv) 464 l = ~l; 465 l &= mask; 466 return l; 467 } 468 469 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 470 { 471 void __iomem *reg = bank->base; 472 u32 l; 473 474 if (bank->regs->set_irqenable) { 475 reg += bank->regs->set_irqenable; 476 l = gpio_mask; 477 } else { 478 reg += bank->regs->irqenable; 479 l = __raw_readl(reg); 480 if (bank->regs->irqenable_inv) 481 l &= ~gpio_mask; 482 else 483 l |= gpio_mask; 484 } 485 486 __raw_writel(l, reg); 487 } 488 489 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 490 { 491 void __iomem *reg = bank->base; 492 u32 l; 493 494 if (bank->regs->clr_irqenable) { 495 reg += bank->regs->clr_irqenable; 496 l = gpio_mask; 497 } else { 498 reg += bank->regs->irqenable; 499 l = __raw_readl(reg); 500 if (bank->regs->irqenable_inv) 501 l |= gpio_mask; 502 else 503 l &= ~gpio_mask; 504 } 505 506 __raw_writel(l, reg); 507 } 508 509 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable) 510 { 511 _enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio)); 512 } 513 514 /* 515 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. 516 * 1510 does not seem to have a wake-up register. If JTAG is connected 517 * to the target, system will wake up always on GPIO events. While 518 * system is running all registered GPIO interrupts need to have wake-up 519 * enabled. When system is suspended, only selected GPIO interrupts need 520 * to have wake-up enabled. 521 */ 522 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable) 523 { 524 u32 gpio_bit = GPIO_BIT(bank, gpio); 525 unsigned long flags; 526 527 if (bank->non_wakeup_gpios & gpio_bit) { 528 dev_err(bank->dev, 529 "Unable to modify wakeup on non-wakeup GPIO%d\n", gpio); 530 return -EINVAL; 531 } 532 533 spin_lock_irqsave(&bank->lock, flags); 534 if (enable) 535 bank->suspend_wakeup |= gpio_bit; 536 else 537 bank->suspend_wakeup &= ~gpio_bit; 538 539 spin_unlock_irqrestore(&bank->lock, flags); 540 541 return 0; 542 } 543 544 static void _reset_gpio(struct gpio_bank *bank, int gpio) 545 { 546 _set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1); 547 _set_gpio_irqenable(bank, gpio, 0); 548 _clear_gpio_irqstatus(bank, gpio); 549 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); 550 } 551 552 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 553 static int gpio_wake_enable(struct irq_data *d, unsigned int enable) 554 { 555 unsigned int gpio = d->irq - IH_GPIO_BASE; 556 struct gpio_bank *bank; 557 int retval; 558 559 bank = irq_data_get_irq_chip_data(d); 560 retval = _set_gpio_wakeup(bank, gpio, enable); 561 562 return retval; 563 } 564 565 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 566 { 567 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 568 unsigned long flags; 569 570 spin_lock_irqsave(&bank->lock, flags); 571 572 /* Set trigger to none. You need to enable the desired trigger with 573 * request_irq() or set_irq_type(). 574 */ 575 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 576 577 #ifdef CONFIG_ARCH_OMAP15XX 578 if (bank->method == METHOD_GPIO_1510) { 579 void __iomem *reg; 580 581 /* Claim the pin for MPU */ 582 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL; 583 __raw_writel(__raw_readl(reg) | (1 << offset), reg); 584 } 585 #endif 586 if (!cpu_class_is_omap1()) { 587 if (!bank->mod_usage) { 588 void __iomem *reg = bank->base; 589 u32 ctrl; 590 591 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 592 reg += OMAP24XX_GPIO_CTRL; 593 else if (cpu_is_omap44xx()) 594 reg += OMAP4_GPIO_CTRL; 595 ctrl = __raw_readl(reg); 596 /* Module is enabled, clocks are not gated */ 597 ctrl &= 0xFFFFFFFE; 598 __raw_writel(ctrl, reg); 599 } 600 bank->mod_usage |= 1 << offset; 601 } 602 spin_unlock_irqrestore(&bank->lock, flags); 603 604 return 0; 605 } 606 607 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 608 { 609 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 610 unsigned long flags; 611 612 spin_lock_irqsave(&bank->lock, flags); 613 #ifdef CONFIG_ARCH_OMAP16XX 614 if (bank->method == METHOD_GPIO_1610) { 615 /* Disable wake-up during idle for dynamic tick */ 616 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 617 __raw_writel(1 << offset, reg); 618 } 619 #endif 620 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 621 if (bank->method == METHOD_GPIO_24XX) { 622 /* Disable wake-up during idle for dynamic tick */ 623 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 624 __raw_writel(1 << offset, reg); 625 } 626 #endif 627 #ifdef CONFIG_ARCH_OMAP4 628 if (bank->method == METHOD_GPIO_44XX) { 629 /* Disable wake-up during idle for dynamic tick */ 630 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0; 631 __raw_writel(1 << offset, reg); 632 } 633 #endif 634 if (!cpu_class_is_omap1()) { 635 bank->mod_usage &= ~(1 << offset); 636 if (!bank->mod_usage) { 637 void __iomem *reg = bank->base; 638 u32 ctrl; 639 640 if (cpu_is_omap24xx() || cpu_is_omap34xx()) 641 reg += OMAP24XX_GPIO_CTRL; 642 else if (cpu_is_omap44xx()) 643 reg += OMAP4_GPIO_CTRL; 644 ctrl = __raw_readl(reg); 645 /* Module is disabled, clocks are gated */ 646 ctrl |= 1; 647 __raw_writel(ctrl, reg); 648 } 649 } 650 _reset_gpio(bank, bank->chip.base + offset); 651 spin_unlock_irqrestore(&bank->lock, flags); 652 } 653 654 /* 655 * We need to unmask the GPIO bank interrupt as soon as possible to 656 * avoid missing GPIO interrupts for other lines in the bank. 657 * Then we need to mask-read-clear-unmask the triggered GPIO lines 658 * in the bank to avoid missing nested interrupts for a GPIO line. 659 * If we wait to unmask individual GPIO lines in the bank after the 660 * line's interrupt handler has been run, we may miss some nested 661 * interrupts. 662 */ 663 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 664 { 665 void __iomem *isr_reg = NULL; 666 u32 isr; 667 unsigned int gpio_irq, gpio_index; 668 struct gpio_bank *bank; 669 u32 retrigger = 0; 670 int unmasked = 0; 671 struct irq_chip *chip = irq_desc_get_chip(desc); 672 673 chained_irq_enter(chip, desc); 674 675 bank = irq_get_handler_data(irq); 676 isr_reg = bank->base + bank->regs->irqstatus; 677 678 if (WARN_ON(!isr_reg)) 679 goto exit; 680 681 while(1) { 682 u32 isr_saved, level_mask = 0; 683 u32 enabled; 684 685 enabled = _get_gpio_irqbank_mask(bank); 686 isr_saved = isr = __raw_readl(isr_reg) & enabled; 687 688 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO)) 689 isr &= 0x0000ffff; 690 691 if (cpu_class_is_omap2()) { 692 level_mask = bank->level_mask & enabled; 693 } 694 695 /* clear edge sensitive interrupts before handler(s) are 696 called so that we don't miss any interrupt occurred while 697 executing them */ 698 _disable_gpio_irqbank(bank, isr_saved & ~level_mask); 699 _clear_gpio_irqbank(bank, isr_saved & ~level_mask); 700 _enable_gpio_irqbank(bank, isr_saved & ~level_mask); 701 702 /* if there is only edge sensitive GPIO pin interrupts 703 configured, we could unmask GPIO bank interrupt immediately */ 704 if (!level_mask && !unmasked) { 705 unmasked = 1; 706 chained_irq_exit(chip, desc); 707 } 708 709 isr |= retrigger; 710 retrigger = 0; 711 if (!isr) 712 break; 713 714 gpio_irq = bank->virtual_irq_start; 715 for (; isr != 0; isr >>= 1, gpio_irq++) { 716 gpio_index = GPIO_INDEX(bank, irq_to_gpio(gpio_irq)); 717 718 if (!(isr & 1)) 719 continue; 720 721 #ifdef CONFIG_ARCH_OMAP1 722 /* 723 * Some chips can't respond to both rising and falling 724 * at the same time. If this irq was requested with 725 * both flags, we need to flip the ICR data for the IRQ 726 * to respond to the IRQ for the opposite direction. 727 * This will be indicated in the bank toggle_mask. 728 */ 729 if (bank->toggle_mask & (1 << gpio_index)) 730 _toggle_gpio_edge_triggering(bank, gpio_index); 731 #endif 732 733 generic_handle_irq(gpio_irq); 734 } 735 } 736 /* if bank has any level sensitive GPIO pin interrupt 737 configured, we must unmask the bank interrupt only after 738 handler(s) are executed in order to avoid spurious bank 739 interrupt */ 740 exit: 741 if (!unmasked) 742 chained_irq_exit(chip, desc); 743 } 744 745 static void gpio_irq_shutdown(struct irq_data *d) 746 { 747 unsigned int gpio = d->irq - IH_GPIO_BASE; 748 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 749 unsigned long flags; 750 751 spin_lock_irqsave(&bank->lock, flags); 752 _reset_gpio(bank, gpio); 753 spin_unlock_irqrestore(&bank->lock, flags); 754 } 755 756 static void gpio_ack_irq(struct irq_data *d) 757 { 758 unsigned int gpio = d->irq - IH_GPIO_BASE; 759 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 760 761 _clear_gpio_irqstatus(bank, gpio); 762 } 763 764 static void gpio_mask_irq(struct irq_data *d) 765 { 766 unsigned int gpio = d->irq - IH_GPIO_BASE; 767 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 768 unsigned long flags; 769 770 spin_lock_irqsave(&bank->lock, flags); 771 _set_gpio_irqenable(bank, gpio, 0); 772 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE); 773 spin_unlock_irqrestore(&bank->lock, flags); 774 } 775 776 static void gpio_unmask_irq(struct irq_data *d) 777 { 778 unsigned int gpio = d->irq - IH_GPIO_BASE; 779 struct gpio_bank *bank = irq_data_get_irq_chip_data(d); 780 unsigned int irq_mask = GPIO_BIT(bank, gpio); 781 u32 trigger = irqd_get_trigger_type(d); 782 unsigned long flags; 783 784 spin_lock_irqsave(&bank->lock, flags); 785 if (trigger) 786 _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger); 787 788 /* For level-triggered GPIOs, the clearing must be done after 789 * the HW source is cleared, thus after the handler has run */ 790 if (bank->level_mask & irq_mask) { 791 _set_gpio_irqenable(bank, gpio, 0); 792 _clear_gpio_irqstatus(bank, gpio); 793 } 794 795 _set_gpio_irqenable(bank, gpio, 1); 796 spin_unlock_irqrestore(&bank->lock, flags); 797 } 798 799 static struct irq_chip gpio_irq_chip = { 800 .name = "GPIO", 801 .irq_shutdown = gpio_irq_shutdown, 802 .irq_ack = gpio_ack_irq, 803 .irq_mask = gpio_mask_irq, 804 .irq_unmask = gpio_unmask_irq, 805 .irq_set_type = gpio_irq_type, 806 .irq_set_wake = gpio_wake_enable, 807 }; 808 809 /*---------------------------------------------------------------------*/ 810 811 #ifdef CONFIG_ARCH_OMAP1 812 813 #define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO) 814 815 #ifdef CONFIG_ARCH_OMAP16XX 816 817 #include <linux/platform_device.h> 818 819 static int omap_mpuio_suspend_noirq(struct device *dev) 820 { 821 struct platform_device *pdev = to_platform_device(dev); 822 struct gpio_bank *bank = platform_get_drvdata(pdev); 823 void __iomem *mask_reg = bank->base + 824 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 825 unsigned long flags; 826 827 spin_lock_irqsave(&bank->lock, flags); 828 bank->saved_wakeup = __raw_readl(mask_reg); 829 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg); 830 spin_unlock_irqrestore(&bank->lock, flags); 831 832 return 0; 833 } 834 835 static int omap_mpuio_resume_noirq(struct device *dev) 836 { 837 struct platform_device *pdev = to_platform_device(dev); 838 struct gpio_bank *bank = platform_get_drvdata(pdev); 839 void __iomem *mask_reg = bank->base + 840 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 841 unsigned long flags; 842 843 spin_lock_irqsave(&bank->lock, flags); 844 __raw_writel(bank->saved_wakeup, mask_reg); 845 spin_unlock_irqrestore(&bank->lock, flags); 846 847 return 0; 848 } 849 850 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 851 .suspend_noirq = omap_mpuio_suspend_noirq, 852 .resume_noirq = omap_mpuio_resume_noirq, 853 }; 854 855 /* use platform_driver for this. */ 856 static struct platform_driver omap_mpuio_driver = { 857 .driver = { 858 .name = "mpuio", 859 .pm = &omap_mpuio_dev_pm_ops, 860 }, 861 }; 862 863 static struct platform_device omap_mpuio_device = { 864 .name = "mpuio", 865 .id = -1, 866 .dev = { 867 .driver = &omap_mpuio_driver.driver, 868 } 869 /* could list the /proc/iomem resources */ 870 }; 871 872 static inline void mpuio_init(void) 873 { 874 struct gpio_bank *bank = &gpio_bank[0]; 875 platform_set_drvdata(&omap_mpuio_device, bank); 876 877 if (platform_driver_register(&omap_mpuio_driver) == 0) 878 (void) platform_device_register(&omap_mpuio_device); 879 } 880 881 #else 882 static inline void mpuio_init(void) {} 883 #endif /* 16xx */ 884 885 #else 886 887 #define bank_is_mpuio(bank) 0 888 static inline void mpuio_init(void) {} 889 890 #endif 891 892 /*---------------------------------------------------------------------*/ 893 894 /* REVISIT these are stupid implementations! replace by ones that 895 * don't switch on METHOD_* and which mostly avoid spinlocks 896 */ 897 898 static int gpio_input(struct gpio_chip *chip, unsigned offset) 899 { 900 struct gpio_bank *bank; 901 unsigned long flags; 902 903 bank = container_of(chip, struct gpio_bank, chip); 904 spin_lock_irqsave(&bank->lock, flags); 905 _set_gpio_direction(bank, offset, 1); 906 spin_unlock_irqrestore(&bank->lock, flags); 907 return 0; 908 } 909 910 static int gpio_is_input(struct gpio_bank *bank, int mask) 911 { 912 void __iomem *reg = bank->base + bank->regs->direction; 913 914 return __raw_readl(reg) & mask; 915 } 916 917 static int gpio_get(struct gpio_chip *chip, unsigned offset) 918 { 919 struct gpio_bank *bank; 920 void __iomem *reg; 921 int gpio; 922 u32 mask; 923 924 gpio = chip->base + offset; 925 bank = container_of(chip, struct gpio_bank, chip); 926 reg = bank->base; 927 mask = GPIO_BIT(bank, gpio); 928 929 if (gpio_is_input(bank, mask)) 930 return _get_gpio_datain(bank, gpio); 931 else 932 return _get_gpio_dataout(bank, gpio); 933 } 934 935 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value) 936 { 937 struct gpio_bank *bank; 938 unsigned long flags; 939 940 bank = container_of(chip, struct gpio_bank, chip); 941 spin_lock_irqsave(&bank->lock, flags); 942 bank->set_dataout(bank, offset, value); 943 _set_gpio_direction(bank, offset, 0); 944 spin_unlock_irqrestore(&bank->lock, flags); 945 return 0; 946 } 947 948 static int gpio_debounce(struct gpio_chip *chip, unsigned offset, 949 unsigned debounce) 950 { 951 struct gpio_bank *bank; 952 unsigned long flags; 953 954 bank = container_of(chip, struct gpio_bank, chip); 955 956 if (!bank->dbck) { 957 bank->dbck = clk_get(bank->dev, "dbclk"); 958 if (IS_ERR(bank->dbck)) 959 dev_err(bank->dev, "Could not get gpio dbck\n"); 960 } 961 962 spin_lock_irqsave(&bank->lock, flags); 963 _set_gpio_debounce(bank, offset, debounce); 964 spin_unlock_irqrestore(&bank->lock, flags); 965 966 return 0; 967 } 968 969 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value) 970 { 971 struct gpio_bank *bank; 972 unsigned long flags; 973 974 bank = container_of(chip, struct gpio_bank, chip); 975 spin_lock_irqsave(&bank->lock, flags); 976 bank->set_dataout(bank, offset, value); 977 spin_unlock_irqrestore(&bank->lock, flags); 978 } 979 980 static int gpio_2irq(struct gpio_chip *chip, unsigned offset) 981 { 982 struct gpio_bank *bank; 983 984 bank = container_of(chip, struct gpio_bank, chip); 985 return bank->virtual_irq_start + offset; 986 } 987 988 /*---------------------------------------------------------------------*/ 989 990 static void __init omap_gpio_show_rev(struct gpio_bank *bank) 991 { 992 static bool called; 993 u32 rev; 994 995 if (called || bank->regs->revision == USHRT_MAX) 996 return; 997 998 rev = __raw_readw(bank->base + bank->regs->revision); 999 pr_info("OMAP GPIO hardware version %d.%d\n", 1000 (rev >> 4) & 0x0f, rev & 0x0f); 1001 1002 called = true; 1003 } 1004 1005 /* This lock class tells lockdep that GPIO irqs are in a different 1006 * category than their parents, so it won't report false recursion. 1007 */ 1008 static struct lock_class_key gpio_lock_class; 1009 1010 static inline int init_gpio_info(struct platform_device *pdev) 1011 { 1012 /* TODO: Analyze removing gpio_bank_count usage from driver code */ 1013 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank), 1014 GFP_KERNEL); 1015 if (!gpio_bank) { 1016 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n"); 1017 return -ENOMEM; 1018 } 1019 return 0; 1020 } 1021 1022 /* TODO: Cleanup cpu_is_* checks */ 1023 static void omap_gpio_mod_init(struct gpio_bank *bank, int id) 1024 { 1025 if (cpu_class_is_omap2()) { 1026 if (cpu_is_omap44xx()) { 1027 __raw_writel(0xffffffff, bank->base + 1028 OMAP4_GPIO_IRQSTATUSCLR0); 1029 __raw_writel(0x00000000, bank->base + 1030 OMAP4_GPIO_DEBOUNCENABLE); 1031 /* Initialize interface clk ungated, module enabled */ 1032 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL); 1033 } else if (cpu_is_omap34xx()) { 1034 __raw_writel(0x00000000, bank->base + 1035 OMAP24XX_GPIO_IRQENABLE1); 1036 __raw_writel(0xffffffff, bank->base + 1037 OMAP24XX_GPIO_IRQSTATUS1); 1038 __raw_writel(0x00000000, bank->base + 1039 OMAP24XX_GPIO_DEBOUNCE_EN); 1040 1041 /* Initialize interface clk ungated, module enabled */ 1042 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL); 1043 } else if (cpu_is_omap24xx()) { 1044 static const u32 non_wakeup_gpios[] = { 1045 0xe203ffc0, 0x08700040 1046 }; 1047 if (id < ARRAY_SIZE(non_wakeup_gpios)) 1048 bank->non_wakeup_gpios = non_wakeup_gpios[id]; 1049 } 1050 } else if (cpu_class_is_omap1()) { 1051 if (bank_is_mpuio(bank)) 1052 __raw_writew(0xffff, bank->base + 1053 OMAP_MPUIO_GPIO_MASKIT / bank->stride); 1054 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) { 1055 __raw_writew(0xffff, bank->base 1056 + OMAP1510_GPIO_INT_MASK); 1057 __raw_writew(0x0000, bank->base 1058 + OMAP1510_GPIO_INT_STATUS); 1059 } 1060 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) { 1061 __raw_writew(0x0000, bank->base 1062 + OMAP1610_GPIO_IRQENABLE1); 1063 __raw_writew(0xffff, bank->base 1064 + OMAP1610_GPIO_IRQSTATUS1); 1065 __raw_writew(0x0014, bank->base 1066 + OMAP1610_GPIO_SYSCONFIG); 1067 1068 /* 1069 * Enable system clock for GPIO module. 1070 * The CAM_CLK_CTRL *is* really the right place. 1071 */ 1072 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, 1073 ULPD_CAM_CLK_CTRL); 1074 } 1075 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) { 1076 __raw_writel(0xffffffff, bank->base 1077 + OMAP7XX_GPIO_INT_MASK); 1078 __raw_writel(0x00000000, bank->base 1079 + OMAP7XX_GPIO_INT_STATUS); 1080 } 1081 } 1082 } 1083 1084 static __init void 1085 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start, 1086 unsigned int num) 1087 { 1088 struct irq_chip_generic *gc; 1089 struct irq_chip_type *ct; 1090 1091 gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base, 1092 handle_simple_irq); 1093 if (!gc) { 1094 dev_err(bank->dev, "Memory alloc failed for gc\n"); 1095 return; 1096 } 1097 1098 ct = gc->chip_types; 1099 1100 /* NOTE: No ack required, reading IRQ status clears it. */ 1101 ct->chip.irq_mask = irq_gc_mask_set_bit; 1102 ct->chip.irq_unmask = irq_gc_mask_clr_bit; 1103 ct->chip.irq_set_type = gpio_irq_type; 1104 /* REVISIT: assuming only 16xx supports MPUIO wake events */ 1105 if (cpu_is_omap16xx()) 1106 ct->chip.irq_set_wake = gpio_wake_enable, 1107 1108 ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride; 1109 irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 1110 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 1111 } 1112 1113 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank) 1114 { 1115 int j; 1116 static int gpio; 1117 1118 bank->mod_usage = 0; 1119 /* 1120 * REVISIT eventually switch from OMAP-specific gpio structs 1121 * over to the generic ones 1122 */ 1123 bank->chip.request = omap_gpio_request; 1124 bank->chip.free = omap_gpio_free; 1125 bank->chip.direction_input = gpio_input; 1126 bank->chip.get = gpio_get; 1127 bank->chip.direction_output = gpio_output; 1128 bank->chip.set_debounce = gpio_debounce; 1129 bank->chip.set = gpio_set; 1130 bank->chip.to_irq = gpio_2irq; 1131 if (bank_is_mpuio(bank)) { 1132 bank->chip.label = "mpuio"; 1133 #ifdef CONFIG_ARCH_OMAP16XX 1134 bank->chip.dev = &omap_mpuio_device.dev; 1135 #endif 1136 bank->chip.base = OMAP_MPUIO(0); 1137 } else { 1138 bank->chip.label = "gpio"; 1139 bank->chip.base = gpio; 1140 gpio += bank->width; 1141 } 1142 bank->chip.ngpio = bank->width; 1143 1144 gpiochip_add(&bank->chip); 1145 1146 for (j = bank->virtual_irq_start; 1147 j < bank->virtual_irq_start + bank->width; j++) { 1148 irq_set_lockdep_class(j, &gpio_lock_class); 1149 irq_set_chip_data(j, bank); 1150 if (bank_is_mpuio(bank)) { 1151 omap_mpuio_alloc_gc(bank, j, bank->width); 1152 } else { 1153 irq_set_chip(j, &gpio_irq_chip); 1154 irq_set_handler(j, handle_simple_irq); 1155 set_irq_flags(j, IRQF_VALID); 1156 } 1157 } 1158 irq_set_chained_handler(bank->irq, gpio_irq_handler); 1159 irq_set_handler_data(bank->irq, bank); 1160 } 1161 1162 static int __devinit omap_gpio_probe(struct platform_device *pdev) 1163 { 1164 static int gpio_init_done; 1165 struct omap_gpio_platform_data *pdata; 1166 struct resource *res; 1167 int id; 1168 struct gpio_bank *bank; 1169 1170 if (!pdev->dev.platform_data) 1171 return -EINVAL; 1172 1173 pdata = pdev->dev.platform_data; 1174 1175 if (!gpio_init_done) { 1176 int ret; 1177 1178 ret = init_gpio_info(pdev); 1179 if (ret) 1180 return ret; 1181 } 1182 1183 id = pdev->id; 1184 bank = &gpio_bank[id]; 1185 1186 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1187 if (unlikely(!res)) { 1188 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id); 1189 return -ENODEV; 1190 } 1191 1192 bank->irq = res->start; 1193 bank->virtual_irq_start = pdata->virtual_irq_start; 1194 bank->method = pdata->bank_type; 1195 bank->dev = &pdev->dev; 1196 bank->dbck_flag = pdata->dbck_flag; 1197 bank->stride = pdata->bank_stride; 1198 bank->width = pdata->bank_width; 1199 1200 bank->regs = pdata->regs; 1201 1202 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1203 bank->set_dataout = _set_gpio_dataout_reg; 1204 else 1205 bank->set_dataout = _set_gpio_dataout_mask; 1206 1207 spin_lock_init(&bank->lock); 1208 1209 /* Static mapping, never released */ 1210 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1211 if (unlikely(!res)) { 1212 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id); 1213 return -ENODEV; 1214 } 1215 1216 bank->base = ioremap(res->start, resource_size(res)); 1217 if (!bank->base) { 1218 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id); 1219 return -ENOMEM; 1220 } 1221 1222 pm_runtime_enable(bank->dev); 1223 pm_runtime_get_sync(bank->dev); 1224 1225 omap_gpio_mod_init(bank, id); 1226 omap_gpio_chip_init(bank); 1227 omap_gpio_show_rev(bank); 1228 1229 if (!gpio_init_done) 1230 gpio_init_done = 1; 1231 1232 return 0; 1233 } 1234 1235 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 1236 static int omap_gpio_suspend(void) 1237 { 1238 int i; 1239 1240 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1241 return 0; 1242 1243 for (i = 0; i < gpio_bank_count; i++) { 1244 struct gpio_bank *bank = &gpio_bank[i]; 1245 void __iomem *wake_status; 1246 void __iomem *wake_clear; 1247 void __iomem *wake_set; 1248 unsigned long flags; 1249 1250 switch (bank->method) { 1251 #ifdef CONFIG_ARCH_OMAP16XX 1252 case METHOD_GPIO_1610: 1253 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE; 1254 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1255 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1256 break; 1257 #endif 1258 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1259 case METHOD_GPIO_24XX: 1260 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN; 1261 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1262 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1263 break; 1264 #endif 1265 #ifdef CONFIG_ARCH_OMAP4 1266 case METHOD_GPIO_44XX: 1267 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0; 1268 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 1269 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 1270 break; 1271 #endif 1272 default: 1273 continue; 1274 } 1275 1276 spin_lock_irqsave(&bank->lock, flags); 1277 bank->saved_wakeup = __raw_readl(wake_status); 1278 __raw_writel(0xffffffff, wake_clear); 1279 __raw_writel(bank->suspend_wakeup, wake_set); 1280 spin_unlock_irqrestore(&bank->lock, flags); 1281 } 1282 1283 return 0; 1284 } 1285 1286 static void omap_gpio_resume(void) 1287 { 1288 int i; 1289 1290 if (!cpu_class_is_omap2() && !cpu_is_omap16xx()) 1291 return; 1292 1293 for (i = 0; i < gpio_bank_count; i++) { 1294 struct gpio_bank *bank = &gpio_bank[i]; 1295 void __iomem *wake_clear; 1296 void __iomem *wake_set; 1297 unsigned long flags; 1298 1299 switch (bank->method) { 1300 #ifdef CONFIG_ARCH_OMAP16XX 1301 case METHOD_GPIO_1610: 1302 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA; 1303 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA; 1304 break; 1305 #endif 1306 #if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) 1307 case METHOD_GPIO_24XX: 1308 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA; 1309 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA; 1310 break; 1311 #endif 1312 #ifdef CONFIG_ARCH_OMAP4 1313 case METHOD_GPIO_44XX: 1314 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0; 1315 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0; 1316 break; 1317 #endif 1318 default: 1319 continue; 1320 } 1321 1322 spin_lock_irqsave(&bank->lock, flags); 1323 __raw_writel(0xffffffff, wake_clear); 1324 __raw_writel(bank->saved_wakeup, wake_set); 1325 spin_unlock_irqrestore(&bank->lock, flags); 1326 } 1327 } 1328 1329 static struct syscore_ops omap_gpio_syscore_ops = { 1330 .suspend = omap_gpio_suspend, 1331 .resume = omap_gpio_resume, 1332 }; 1333 1334 #endif 1335 1336 #ifdef CONFIG_ARCH_OMAP2PLUS 1337 1338 static int workaround_enabled; 1339 1340 void omap2_gpio_prepare_for_idle(int off_mode) 1341 { 1342 int i, c = 0; 1343 int min = 0; 1344 1345 if (cpu_is_omap34xx()) 1346 min = 1; 1347 1348 for (i = min; i < gpio_bank_count; i++) { 1349 struct gpio_bank *bank = &gpio_bank[i]; 1350 u32 l1 = 0, l2 = 0; 1351 int j; 1352 1353 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1354 clk_disable(bank->dbck); 1355 1356 if (!off_mode) 1357 continue; 1358 1359 /* If going to OFF, remove triggering for all 1360 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1361 * generated. See OMAP2420 Errata item 1.101. */ 1362 if (!(bank->enabled_non_wakeup_gpios)) 1363 continue; 1364 1365 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1366 bank->saved_datain = __raw_readl(bank->base + 1367 OMAP24XX_GPIO_DATAIN); 1368 l1 = __raw_readl(bank->base + 1369 OMAP24XX_GPIO_FALLINGDETECT); 1370 l2 = __raw_readl(bank->base + 1371 OMAP24XX_GPIO_RISINGDETECT); 1372 } 1373 1374 if (cpu_is_omap44xx()) { 1375 bank->saved_datain = __raw_readl(bank->base + 1376 OMAP4_GPIO_DATAIN); 1377 l1 = __raw_readl(bank->base + 1378 OMAP4_GPIO_FALLINGDETECT); 1379 l2 = __raw_readl(bank->base + 1380 OMAP4_GPIO_RISINGDETECT); 1381 } 1382 1383 bank->saved_fallingdetect = l1; 1384 bank->saved_risingdetect = l2; 1385 l1 &= ~bank->enabled_non_wakeup_gpios; 1386 l2 &= ~bank->enabled_non_wakeup_gpios; 1387 1388 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1389 __raw_writel(l1, bank->base + 1390 OMAP24XX_GPIO_FALLINGDETECT); 1391 __raw_writel(l2, bank->base + 1392 OMAP24XX_GPIO_RISINGDETECT); 1393 } 1394 1395 if (cpu_is_omap44xx()) { 1396 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT); 1397 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT); 1398 } 1399 1400 c++; 1401 } 1402 if (!c) { 1403 workaround_enabled = 0; 1404 return; 1405 } 1406 workaround_enabled = 1; 1407 } 1408 1409 void omap2_gpio_resume_after_idle(void) 1410 { 1411 int i; 1412 int min = 0; 1413 1414 if (cpu_is_omap34xx()) 1415 min = 1; 1416 for (i = min; i < gpio_bank_count; i++) { 1417 struct gpio_bank *bank = &gpio_bank[i]; 1418 u32 l = 0, gen, gen0, gen1; 1419 int j; 1420 1421 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++) 1422 clk_enable(bank->dbck); 1423 1424 if (!workaround_enabled) 1425 continue; 1426 1427 if (!(bank->enabled_non_wakeup_gpios)) 1428 continue; 1429 1430 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1431 __raw_writel(bank->saved_fallingdetect, 1432 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1433 __raw_writel(bank->saved_risingdetect, 1434 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1435 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN); 1436 } 1437 1438 if (cpu_is_omap44xx()) { 1439 __raw_writel(bank->saved_fallingdetect, 1440 bank->base + OMAP4_GPIO_FALLINGDETECT); 1441 __raw_writel(bank->saved_risingdetect, 1442 bank->base + OMAP4_GPIO_RISINGDETECT); 1443 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN); 1444 } 1445 1446 /* Check if any of the non-wakeup interrupt GPIOs have changed 1447 * state. If so, generate an IRQ by software. This is 1448 * horribly racy, but it's the best we can do to work around 1449 * this silicon bug. */ 1450 l ^= bank->saved_datain; 1451 l &= bank->enabled_non_wakeup_gpios; 1452 1453 /* 1454 * No need to generate IRQs for the rising edge for gpio IRQs 1455 * configured with falling edge only; and vice versa. 1456 */ 1457 gen0 = l & bank->saved_fallingdetect; 1458 gen0 &= bank->saved_datain; 1459 1460 gen1 = l & bank->saved_risingdetect; 1461 gen1 &= ~(bank->saved_datain); 1462 1463 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1464 gen = l & (~(bank->saved_fallingdetect) & 1465 ~(bank->saved_risingdetect)); 1466 /* Consider all GPIO IRQs needed to be updated */ 1467 gen |= gen0 | gen1; 1468 1469 if (gen) { 1470 u32 old0, old1; 1471 1472 if (cpu_is_omap24xx() || cpu_is_omap34xx()) { 1473 old0 = __raw_readl(bank->base + 1474 OMAP24XX_GPIO_LEVELDETECT0); 1475 old1 = __raw_readl(bank->base + 1476 OMAP24XX_GPIO_LEVELDETECT1); 1477 __raw_writel(old0 | gen, bank->base + 1478 OMAP24XX_GPIO_LEVELDETECT0); 1479 __raw_writel(old1 | gen, bank->base + 1480 OMAP24XX_GPIO_LEVELDETECT1); 1481 __raw_writel(old0, bank->base + 1482 OMAP24XX_GPIO_LEVELDETECT0); 1483 __raw_writel(old1, bank->base + 1484 OMAP24XX_GPIO_LEVELDETECT1); 1485 } 1486 1487 if (cpu_is_omap44xx()) { 1488 old0 = __raw_readl(bank->base + 1489 OMAP4_GPIO_LEVELDETECT0); 1490 old1 = __raw_readl(bank->base + 1491 OMAP4_GPIO_LEVELDETECT1); 1492 __raw_writel(old0 | l, bank->base + 1493 OMAP4_GPIO_LEVELDETECT0); 1494 __raw_writel(old1 | l, bank->base + 1495 OMAP4_GPIO_LEVELDETECT1); 1496 __raw_writel(old0, bank->base + 1497 OMAP4_GPIO_LEVELDETECT0); 1498 __raw_writel(old1, bank->base + 1499 OMAP4_GPIO_LEVELDETECT1); 1500 } 1501 } 1502 } 1503 1504 } 1505 1506 #endif 1507 1508 #ifdef CONFIG_ARCH_OMAP3 1509 /* save the registers of bank 2-6 */ 1510 void omap_gpio_save_context(void) 1511 { 1512 int i; 1513 1514 /* saving banks from 2-6 only since GPIO1 is in WKUP */ 1515 for (i = 1; i < gpio_bank_count; i++) { 1516 struct gpio_bank *bank = &gpio_bank[i]; 1517 gpio_context[i].irqenable1 = 1518 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1); 1519 gpio_context[i].irqenable2 = 1520 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2); 1521 gpio_context[i].wake_en = 1522 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN); 1523 gpio_context[i].ctrl = 1524 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL); 1525 gpio_context[i].oe = 1526 __raw_readl(bank->base + OMAP24XX_GPIO_OE); 1527 gpio_context[i].leveldetect0 = 1528 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1529 gpio_context[i].leveldetect1 = 1530 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1531 gpio_context[i].risingdetect = 1532 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT); 1533 gpio_context[i].fallingdetect = 1534 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1535 gpio_context[i].dataout = 1536 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT); 1537 } 1538 } 1539 1540 /* restore the required registers of bank 2-6 */ 1541 void omap_gpio_restore_context(void) 1542 { 1543 int i; 1544 1545 for (i = 1; i < gpio_bank_count; i++) { 1546 struct gpio_bank *bank = &gpio_bank[i]; 1547 __raw_writel(gpio_context[i].irqenable1, 1548 bank->base + OMAP24XX_GPIO_IRQENABLE1); 1549 __raw_writel(gpio_context[i].irqenable2, 1550 bank->base + OMAP24XX_GPIO_IRQENABLE2); 1551 __raw_writel(gpio_context[i].wake_en, 1552 bank->base + OMAP24XX_GPIO_WAKE_EN); 1553 __raw_writel(gpio_context[i].ctrl, 1554 bank->base + OMAP24XX_GPIO_CTRL); 1555 __raw_writel(gpio_context[i].oe, 1556 bank->base + OMAP24XX_GPIO_OE); 1557 __raw_writel(gpio_context[i].leveldetect0, 1558 bank->base + OMAP24XX_GPIO_LEVELDETECT0); 1559 __raw_writel(gpio_context[i].leveldetect1, 1560 bank->base + OMAP24XX_GPIO_LEVELDETECT1); 1561 __raw_writel(gpio_context[i].risingdetect, 1562 bank->base + OMAP24XX_GPIO_RISINGDETECT); 1563 __raw_writel(gpio_context[i].fallingdetect, 1564 bank->base + OMAP24XX_GPIO_FALLINGDETECT); 1565 __raw_writel(gpio_context[i].dataout, 1566 bank->base + OMAP24XX_GPIO_DATAOUT); 1567 } 1568 } 1569 #endif 1570 1571 static struct platform_driver omap_gpio_driver = { 1572 .probe = omap_gpio_probe, 1573 .driver = { 1574 .name = "omap_gpio", 1575 }, 1576 }; 1577 1578 /* 1579 * gpio driver register needs to be done before 1580 * machine_init functions access gpio APIs. 1581 * Hence omap_gpio_drv_reg() is a postcore_initcall. 1582 */ 1583 static int __init omap_gpio_drv_reg(void) 1584 { 1585 return platform_driver_register(&omap_gpio_driver); 1586 } 1587 postcore_initcall(omap_gpio_drv_reg); 1588 1589 static int __init omap_gpio_sysinit(void) 1590 { 1591 mpuio_init(); 1592 1593 #if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS) 1594 if (cpu_is_omap16xx() || cpu_class_is_omap2()) 1595 register_syscore_ops(&omap_gpio_syscore_ops); 1596 #endif 1597 1598 return 0; 1599 } 1600 1601 arch_initcall(omap_gpio_sysinit); 1602