xref: /linux/drivers/gpio/gpio-omap.c (revision 4e95bc268b915c3a19ec8b9110f61e4ea41a1ed0)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Support functions for OMAP GPIO
4  *
5  * Copyright (C) 2003-2005 Nokia Corporation
6  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
7  *
8  * Copyright (C) 2009 Texas Instruments
9  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10  */
11 
12 #include <linux/init.h>
13 #include <linux/module.h>
14 #include <linux/interrupt.h>
15 #include <linux/syscore_ops.h>
16 #include <linux/err.h>
17 #include <linux/clk.h>
18 #include <linux/io.h>
19 #include <linux/cpu_pm.h>
20 #include <linux/device.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/pm.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/gpio/driver.h>
26 #include <linux/bitops.h>
27 #include <linux/platform_data/gpio-omap.h>
28 
29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF
30 
31 struct gpio_regs {
32 	u32 irqenable1;
33 	u32 irqenable2;
34 	u32 wake_en;
35 	u32 ctrl;
36 	u32 oe;
37 	u32 leveldetect0;
38 	u32 leveldetect1;
39 	u32 risingdetect;
40 	u32 fallingdetect;
41 	u32 dataout;
42 	u32 debounce;
43 	u32 debounce_en;
44 };
45 
46 struct gpio_bank {
47 	struct list_head node;
48 	void __iomem *base;
49 	int irq;
50 	u32 non_wakeup_gpios;
51 	u32 enabled_non_wakeup_gpios;
52 	struct gpio_regs context;
53 	u32 saved_datain;
54 	u32 level_mask;
55 	u32 toggle_mask;
56 	raw_spinlock_t lock;
57 	raw_spinlock_t wa_lock;
58 	struct gpio_chip chip;
59 	struct clk *dbck;
60 	struct notifier_block nb;
61 	unsigned int is_suspended:1;
62 	u32 mod_usage;
63 	u32 irq_usage;
64 	u32 dbck_enable_mask;
65 	bool dbck_enabled;
66 	bool is_mpuio;
67 	bool dbck_flag;
68 	bool loses_context;
69 	bool context_valid;
70 	int stride;
71 	u32 width;
72 	int context_loss_count;
73 
74 	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
75 	void (*set_dataout_multiple)(struct gpio_bank *bank,
76 				     unsigned long *mask, unsigned long *bits);
77 	int (*get_context_loss_count)(struct device *dev);
78 
79 	struct omap_gpio_reg_offs *regs;
80 };
81 
82 #define GPIO_MOD_CTRL_BIT	BIT(0)
83 
84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)
85 #define LINE_USED(line, offset) (line & (BIT(offset)))
86 
87 static void omap_gpio_unmask_irq(struct irq_data *d);
88 
89 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d)
90 {
91 	struct gpio_chip *chip = irq_data_get_irq_chip_data(d);
92 	return gpiochip_get_data(chip);
93 }
94 
95 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,
96 				    int is_input)
97 {
98 	void __iomem *reg = bank->base;
99 	u32 l;
100 
101 	reg += bank->regs->direction;
102 	l = readl_relaxed(reg);
103 	if (is_input)
104 		l |= BIT(gpio);
105 	else
106 		l &= ~(BIT(gpio));
107 	writel_relaxed(l, reg);
108 	bank->context.oe = l;
109 }
110 
111 
112 /* set data out value using dedicate set/clear register */
113 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,
114 				      int enable)
115 {
116 	void __iomem *reg = bank->base;
117 	u32 l = BIT(offset);
118 
119 	if (enable) {
120 		reg += bank->regs->set_dataout;
121 		bank->context.dataout |= l;
122 	} else {
123 		reg += bank->regs->clr_dataout;
124 		bank->context.dataout &= ~l;
125 	}
126 
127 	writel_relaxed(l, reg);
128 }
129 
130 /* set data out value using mask register */
131 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,
132 				       int enable)
133 {
134 	void __iomem *reg = bank->base + bank->regs->dataout;
135 	u32 gpio_bit = BIT(offset);
136 	u32 l;
137 
138 	l = readl_relaxed(reg);
139 	if (enable)
140 		l |= gpio_bit;
141 	else
142 		l &= ~gpio_bit;
143 	writel_relaxed(l, reg);
144 	bank->context.dataout = l;
145 }
146 
147 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)
148 {
149 	void __iomem *reg = bank->base + bank->regs->datain;
150 
151 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
152 }
153 
154 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)
155 {
156 	void __iomem *reg = bank->base + bank->regs->dataout;
157 
158 	return (readl_relaxed(reg) & (BIT(offset))) != 0;
159 }
160 
161 /* set multiple data out values using dedicate set/clear register */
162 static void omap_set_gpio_dataout_reg_multiple(struct gpio_bank *bank,
163 					       unsigned long *mask,
164 					       unsigned long *bits)
165 {
166 	void __iomem *reg = bank->base;
167 	u32 l;
168 
169 	l = *bits & *mask;
170 	writel_relaxed(l, reg + bank->regs->set_dataout);
171 	bank->context.dataout |= l;
172 
173 	l = ~*bits & *mask;
174 	writel_relaxed(l, reg + bank->regs->clr_dataout);
175 	bank->context.dataout &= ~l;
176 }
177 
178 /* set multiple data out values using mask register */
179 static void omap_set_gpio_dataout_mask_multiple(struct gpio_bank *bank,
180 						unsigned long *mask,
181 						unsigned long *bits)
182 {
183 	void __iomem *reg = bank->base + bank->regs->dataout;
184 	u32 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask);
185 
186 	writel_relaxed(l, reg);
187 	bank->context.dataout = l;
188 }
189 
190 static unsigned long omap_get_gpio_datain_multiple(struct gpio_bank *bank,
191 					      unsigned long *mask)
192 {
193 	void __iomem *reg = bank->base + bank->regs->datain;
194 
195 	return readl_relaxed(reg) & *mask;
196 }
197 
198 static unsigned long omap_get_gpio_dataout_multiple(struct gpio_bank *bank,
199 					       unsigned long *mask)
200 {
201 	void __iomem *reg = bank->base + bank->regs->dataout;
202 
203 	return readl_relaxed(reg) & *mask;
204 }
205 
206 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
207 {
208 	int l = readl_relaxed(base + reg);
209 
210 	if (set)
211 		l |= mask;
212 	else
213 		l &= ~mask;
214 
215 	writel_relaxed(l, base + reg);
216 }
217 
218 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)
219 {
220 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
221 		clk_enable(bank->dbck);
222 		bank->dbck_enabled = true;
223 
224 		writel_relaxed(bank->dbck_enable_mask,
225 			     bank->base + bank->regs->debounce_en);
226 	}
227 }
228 
229 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)
230 {
231 	if (bank->dbck_enable_mask && bank->dbck_enabled) {
232 		/*
233 		 * Disable debounce before cutting it's clock. If debounce is
234 		 * enabled but the clock is not, GPIO module seems to be unable
235 		 * to detect events and generate interrupts at least on OMAP3.
236 		 */
237 		writel_relaxed(0, bank->base + bank->regs->debounce_en);
238 
239 		clk_disable(bank->dbck);
240 		bank->dbck_enabled = false;
241 	}
242 }
243 
244 /**
245  * omap2_set_gpio_debounce - low level gpio debounce time
246  * @bank: the gpio bank we're acting upon
247  * @offset: the gpio number on this @bank
248  * @debounce: debounce time to use
249  *
250  * OMAP's debounce time is in 31us steps
251  *   <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31
252  * so we need to convert and round up to the closest unit.
253  *
254  * Return: 0 on success, negative error otherwise.
255  */
256 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,
257 				   unsigned debounce)
258 {
259 	void __iomem		*reg;
260 	u32			val;
261 	u32			l;
262 	bool			enable = !!debounce;
263 
264 	if (!bank->dbck_flag)
265 		return -ENOTSUPP;
266 
267 	if (enable) {
268 		debounce = DIV_ROUND_UP(debounce, 31) - 1;
269 		if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce)
270 			return -EINVAL;
271 	}
272 
273 	l = BIT(offset);
274 
275 	clk_enable(bank->dbck);
276 	reg = bank->base + bank->regs->debounce;
277 	writel_relaxed(debounce, reg);
278 
279 	reg = bank->base + bank->regs->debounce_en;
280 	val = readl_relaxed(reg);
281 
282 	if (enable)
283 		val |= l;
284 	else
285 		val &= ~l;
286 	bank->dbck_enable_mask = val;
287 
288 	writel_relaxed(val, reg);
289 	clk_disable(bank->dbck);
290 	/*
291 	 * Enable debounce clock per module.
292 	 * This call is mandatory because in omap_gpio_request() when
293 	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
294 	 * runtime callbck fails to turn on dbck because dbck_enable_mask
295 	 * used within _gpio_dbck_enable() is still not initialized at
296 	 * that point. Therefore we have to enable dbck here.
297 	 */
298 	omap_gpio_dbck_enable(bank);
299 	if (bank->dbck_enable_mask) {
300 		bank->context.debounce = debounce;
301 		bank->context.debounce_en = val;
302 	}
303 
304 	return 0;
305 }
306 
307 /**
308  * omap_clear_gpio_debounce - clear debounce settings for a gpio
309  * @bank: the gpio bank we're acting upon
310  * @offset: the gpio number on this @bank
311  *
312  * If a gpio is using debounce, then clear the debounce enable bit and if
313  * this is the only gpio in this bank using debounce, then clear the debounce
314  * time too. The debounce clock will also be disabled when calling this function
315  * if this is the only gpio in the bank using debounce.
316  */
317 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)
318 {
319 	u32 gpio_bit = BIT(offset);
320 
321 	if (!bank->dbck_flag)
322 		return;
323 
324 	if (!(bank->dbck_enable_mask & gpio_bit))
325 		return;
326 
327 	bank->dbck_enable_mask &= ~gpio_bit;
328 	bank->context.debounce_en &= ~gpio_bit;
329         writel_relaxed(bank->context.debounce_en,
330 		     bank->base + bank->regs->debounce_en);
331 
332 	if (!bank->dbck_enable_mask) {
333 		bank->context.debounce = 0;
334 		writel_relaxed(bank->context.debounce, bank->base +
335 			     bank->regs->debounce);
336 		clk_disable(bank->dbck);
337 		bank->dbck_enabled = false;
338 	}
339 }
340 
341 /*
342  * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain.
343  * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs
344  * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none
345  * are capable waking up the system from off mode.
346  */
347 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask)
348 {
349 	u32 no_wake = bank->non_wakeup_gpios;
350 
351 	if (no_wake)
352 		return !!(~no_wake & gpio_mask);
353 
354 	return false;
355 }
356 
357 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,
358 						unsigned trigger)
359 {
360 	void __iomem *base = bank->base;
361 	u32 gpio_bit = BIT(gpio);
362 
363 	omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
364 		      trigger & IRQ_TYPE_LEVEL_LOW);
365 	omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
366 		      trigger & IRQ_TYPE_LEVEL_HIGH);
367 
368 	/*
369 	 * We need the edge detection enabled for to allow the GPIO block
370 	 * to be woken from idle state.  Set the appropriate edge detection
371 	 * in addition to the level detection.
372 	 */
373 	omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
374 		      trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH));
375 	omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
376 		      trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW));
377 
378 	bank->context.leveldetect0 =
379 			readl_relaxed(bank->base + bank->regs->leveldetect0);
380 	bank->context.leveldetect1 =
381 			readl_relaxed(bank->base + bank->regs->leveldetect1);
382 	bank->context.risingdetect =
383 			readl_relaxed(bank->base + bank->regs->risingdetect);
384 	bank->context.fallingdetect =
385 			readl_relaxed(bank->base + bank->regs->fallingdetect);
386 
387 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
388 		omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
389 		bank->context.wake_en =
390 			readl_relaxed(bank->base + bank->regs->wkup_en);
391 	}
392 
393 	/* This part needs to be executed always for OMAP{34xx, 44xx} */
394 	if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) {
395 		/*
396 		 * Log the edge gpio and manually trigger the IRQ
397 		 * after resume if the input level changes
398 		 * to avoid irq lost during PER RET/OFF mode
399 		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
400 		 */
401 		if (trigger & IRQ_TYPE_EDGE_BOTH)
402 			bank->enabled_non_wakeup_gpios |= gpio_bit;
403 		else
404 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
405 	}
406 
407 	bank->level_mask =
408 		readl_relaxed(bank->base + bank->regs->leveldetect0) |
409 		readl_relaxed(bank->base + bank->regs->leveldetect1);
410 }
411 
412 #ifdef CONFIG_ARCH_OMAP1
413 /*
414  * This only applies to chips that can't do both rising and falling edge
415  * detection at once.  For all other chips, this function is a noop.
416  */
417 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
418 {
419 	void __iomem *reg = bank->base;
420 	u32 l = 0;
421 
422 	if (!bank->regs->irqctrl)
423 		return;
424 
425 	reg += bank->regs->irqctrl;
426 
427 	l = readl_relaxed(reg);
428 	if ((l >> gpio) & 1)
429 		l &= ~(BIT(gpio));
430 	else
431 		l |= BIT(gpio);
432 
433 	writel_relaxed(l, reg);
434 }
435 #else
436 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
437 #endif
438 
439 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,
440 				    unsigned trigger)
441 {
442 	void __iomem *reg = bank->base;
443 	void __iomem *base = bank->base;
444 	u32 l = 0;
445 
446 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
447 		omap_set_gpio_trigger(bank, gpio, trigger);
448 	} else if (bank->regs->irqctrl) {
449 		reg += bank->regs->irqctrl;
450 
451 		l = readl_relaxed(reg);
452 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
453 			bank->toggle_mask |= BIT(gpio);
454 		if (trigger & IRQ_TYPE_EDGE_RISING)
455 			l |= BIT(gpio);
456 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
457 			l &= ~(BIT(gpio));
458 		else
459 			return -EINVAL;
460 
461 		writel_relaxed(l, reg);
462 	} else if (bank->regs->edgectrl1) {
463 		if (gpio & 0x08)
464 			reg += bank->regs->edgectrl2;
465 		else
466 			reg += bank->regs->edgectrl1;
467 
468 		gpio &= 0x07;
469 		l = readl_relaxed(reg);
470 		l &= ~(3 << (gpio << 1));
471 		if (trigger & IRQ_TYPE_EDGE_RISING)
472 			l |= 2 << (gpio << 1);
473 		if (trigger & IRQ_TYPE_EDGE_FALLING)
474 			l |= BIT(gpio << 1);
475 
476 		/* Enable wake-up during idle for dynamic tick */
477 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);
478 		bank->context.wake_en =
479 			readl_relaxed(bank->base + bank->regs->wkup_en);
480 		writel_relaxed(l, reg);
481 	}
482 	return 0;
483 }
484 
485 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)
486 {
487 	if (bank->regs->pinctrl) {
488 		void __iomem *reg = bank->base + bank->regs->pinctrl;
489 
490 		/* Claim the pin for MPU */
491 		writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg);
492 	}
493 
494 	if (bank->regs->ctrl && !BANK_USED(bank)) {
495 		void __iomem *reg = bank->base + bank->regs->ctrl;
496 		u32 ctrl;
497 
498 		ctrl = readl_relaxed(reg);
499 		/* Module is enabled, clocks are not gated */
500 		ctrl &= ~GPIO_MOD_CTRL_BIT;
501 		writel_relaxed(ctrl, reg);
502 		bank->context.ctrl = ctrl;
503 	}
504 }
505 
506 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)
507 {
508 	void __iomem *base = bank->base;
509 
510 	if (bank->regs->wkup_en &&
511 	    !LINE_USED(bank->mod_usage, offset) &&
512 	    !LINE_USED(bank->irq_usage, offset)) {
513 		/* Disable wake-up during idle for dynamic tick */
514 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);
515 		bank->context.wake_en =
516 			readl_relaxed(bank->base + bank->regs->wkup_en);
517 	}
518 
519 	if (bank->regs->ctrl && !BANK_USED(bank)) {
520 		void __iomem *reg = bank->base + bank->regs->ctrl;
521 		u32 ctrl;
522 
523 		ctrl = readl_relaxed(reg);
524 		/* Module is disabled, clocks are gated */
525 		ctrl |= GPIO_MOD_CTRL_BIT;
526 		writel_relaxed(ctrl, reg);
527 		bank->context.ctrl = ctrl;
528 	}
529 }
530 
531 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)
532 {
533 	void __iomem *reg = bank->base + bank->regs->direction;
534 
535 	return readl_relaxed(reg) & BIT(offset);
536 }
537 
538 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)
539 {
540 	if (!LINE_USED(bank->mod_usage, offset)) {
541 		omap_enable_gpio_module(bank, offset);
542 		omap_set_gpio_direction(bank, offset, 1);
543 	}
544 	bank->irq_usage |= BIT(offset);
545 }
546 
547 static int omap_gpio_irq_type(struct irq_data *d, unsigned type)
548 {
549 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
550 	int retval;
551 	unsigned long flags;
552 	unsigned offset = d->hwirq;
553 
554 	if (type & ~IRQ_TYPE_SENSE_MASK)
555 		return -EINVAL;
556 
557 	if (!bank->regs->leveldetect0 &&
558 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
559 		return -EINVAL;
560 
561 	raw_spin_lock_irqsave(&bank->lock, flags);
562 	retval = omap_set_gpio_triggering(bank, offset, type);
563 	if (retval) {
564 		raw_spin_unlock_irqrestore(&bank->lock, flags);
565 		goto error;
566 	}
567 	omap_gpio_init_irq(bank, offset);
568 	if (!omap_gpio_is_input(bank, offset)) {
569 		raw_spin_unlock_irqrestore(&bank->lock, flags);
570 		retval = -EINVAL;
571 		goto error;
572 	}
573 	raw_spin_unlock_irqrestore(&bank->lock, flags);
574 
575 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
576 		irq_set_handler_locked(d, handle_level_irq);
577 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
578 		/*
579 		 * Edge IRQs are already cleared/acked in irq_handler and
580 		 * not need to be masked, as result handle_edge_irq()
581 		 * logic is excessed here and may cause lose of interrupts.
582 		 * So just use handle_simple_irq.
583 		 */
584 		irq_set_handler_locked(d, handle_simple_irq);
585 
586 	return 0;
587 
588 error:
589 	return retval;
590 }
591 
592 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
593 {
594 	void __iomem *reg = bank->base;
595 
596 	reg += bank->regs->irqstatus;
597 	writel_relaxed(gpio_mask, reg);
598 
599 	/* Workaround for clearing DSP GPIO interrupts to allow retention */
600 	if (bank->regs->irqstatus2) {
601 		reg = bank->base + bank->regs->irqstatus2;
602 		writel_relaxed(gpio_mask, reg);
603 	}
604 
605 	/* Flush posted write for the irq status to avoid spurious interrupts */
606 	readl_relaxed(reg);
607 }
608 
609 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,
610 					     unsigned offset)
611 {
612 	omap_clear_gpio_irqbank(bank, BIT(offset));
613 }
614 
615 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)
616 {
617 	void __iomem *reg = bank->base;
618 	u32 l;
619 	u32 mask = (BIT(bank->width)) - 1;
620 
621 	reg += bank->regs->irqenable;
622 	l = readl_relaxed(reg);
623 	if (bank->regs->irqenable_inv)
624 		l = ~l;
625 	l &= mask;
626 	return l;
627 }
628 
629 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
630 {
631 	void __iomem *reg = bank->base;
632 	u32 l;
633 
634 	if (bank->regs->set_irqenable) {
635 		reg += bank->regs->set_irqenable;
636 		l = gpio_mask;
637 		bank->context.irqenable1 |= gpio_mask;
638 	} else {
639 		reg += bank->regs->irqenable;
640 		l = readl_relaxed(reg);
641 		if (bank->regs->irqenable_inv)
642 			l &= ~gpio_mask;
643 		else
644 			l |= gpio_mask;
645 		bank->context.irqenable1 = l;
646 	}
647 
648 	writel_relaxed(l, reg);
649 }
650 
651 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
652 {
653 	void __iomem *reg = bank->base;
654 	u32 l;
655 
656 	if (bank->regs->clr_irqenable) {
657 		reg += bank->regs->clr_irqenable;
658 		l = gpio_mask;
659 		bank->context.irqenable1 &= ~gpio_mask;
660 	} else {
661 		reg += bank->regs->irqenable;
662 		l = readl_relaxed(reg);
663 		if (bank->regs->irqenable_inv)
664 			l |= gpio_mask;
665 		else
666 			l &= ~gpio_mask;
667 		bank->context.irqenable1 = l;
668 	}
669 
670 	writel_relaxed(l, reg);
671 }
672 
673 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,
674 					   unsigned offset, int enable)
675 {
676 	if (enable)
677 		omap_enable_gpio_irqbank(bank, BIT(offset));
678 	else
679 		omap_disable_gpio_irqbank(bank, BIT(offset));
680 }
681 
682 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
683 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable)
684 {
685 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
686 
687 	return irq_set_irq_wake(bank->irq, enable);
688 }
689 
690 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
691 {
692 	struct gpio_bank *bank = gpiochip_get_data(chip);
693 	unsigned long flags;
694 
695 	pm_runtime_get_sync(chip->parent);
696 
697 	raw_spin_lock_irqsave(&bank->lock, flags);
698 	omap_enable_gpio_module(bank, offset);
699 	bank->mod_usage |= BIT(offset);
700 	raw_spin_unlock_irqrestore(&bank->lock, flags);
701 
702 	return 0;
703 }
704 
705 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
706 {
707 	struct gpio_bank *bank = gpiochip_get_data(chip);
708 	unsigned long flags;
709 
710 	raw_spin_lock_irqsave(&bank->lock, flags);
711 	bank->mod_usage &= ~(BIT(offset));
712 	if (!LINE_USED(bank->irq_usage, offset)) {
713 		omap_set_gpio_direction(bank, offset, 1);
714 		omap_clear_gpio_debounce(bank, offset);
715 	}
716 	omap_disable_gpio_module(bank, offset);
717 	raw_spin_unlock_irqrestore(&bank->lock, flags);
718 
719 	pm_runtime_put(chip->parent);
720 }
721 
722 /*
723  * We need to unmask the GPIO bank interrupt as soon as possible to
724  * avoid missing GPIO interrupts for other lines in the bank.
725  * Then we need to mask-read-clear-unmask the triggered GPIO lines
726  * in the bank to avoid missing nested interrupts for a GPIO line.
727  * If we wait to unmask individual GPIO lines in the bank after the
728  * line's interrupt handler has been run, we may miss some nested
729  * interrupts.
730  */
731 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank)
732 {
733 	void __iomem *isr_reg = NULL;
734 	u32 enabled, isr, level_mask;
735 	unsigned int bit;
736 	struct gpio_bank *bank = gpiobank;
737 	unsigned long wa_lock_flags;
738 	unsigned long lock_flags;
739 
740 	isr_reg = bank->base + bank->regs->irqstatus;
741 	if (WARN_ON(!isr_reg))
742 		goto exit;
743 
744 	if (WARN_ONCE(!pm_runtime_active(bank->chip.parent),
745 		      "gpio irq%i while runtime suspended?\n", irq))
746 		return IRQ_NONE;
747 
748 	while (1) {
749 		raw_spin_lock_irqsave(&bank->lock, lock_flags);
750 
751 		enabled = omap_get_gpio_irqbank_mask(bank);
752 		isr = readl_relaxed(isr_reg) & enabled;
753 
754 		if (bank->level_mask)
755 			level_mask = bank->level_mask & enabled;
756 		else
757 			level_mask = 0;
758 
759 		/* clear edge sensitive interrupts before handler(s) are
760 		called so that we don't miss any interrupt occurred while
761 		executing them */
762 		if (isr & ~level_mask)
763 			omap_clear_gpio_irqbank(bank, isr & ~level_mask);
764 
765 		raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
766 
767 		if (!isr)
768 			break;
769 
770 		while (isr) {
771 			bit = __ffs(isr);
772 			isr &= ~(BIT(bit));
773 
774 			raw_spin_lock_irqsave(&bank->lock, lock_flags);
775 			/*
776 			 * Some chips can't respond to both rising and falling
777 			 * at the same time.  If this irq was requested with
778 			 * both flags, we need to flip the ICR data for the IRQ
779 			 * to respond to the IRQ for the opposite direction.
780 			 * This will be indicated in the bank toggle_mask.
781 			 */
782 			if (bank->toggle_mask & (BIT(bit)))
783 				omap_toggle_gpio_edge_triggering(bank, bit);
784 
785 			raw_spin_unlock_irqrestore(&bank->lock, lock_flags);
786 
787 			raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags);
788 
789 			generic_handle_irq(irq_find_mapping(bank->chip.irq.domain,
790 							    bit));
791 
792 			raw_spin_unlock_irqrestore(&bank->wa_lock,
793 						   wa_lock_flags);
794 		}
795 	}
796 exit:
797 	return IRQ_HANDLED;
798 }
799 
800 static unsigned int omap_gpio_irq_startup(struct irq_data *d)
801 {
802 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
803 	unsigned long flags;
804 	unsigned offset = d->hwirq;
805 
806 	raw_spin_lock_irqsave(&bank->lock, flags);
807 
808 	if (!LINE_USED(bank->mod_usage, offset))
809 		omap_set_gpio_direction(bank, offset, 1);
810 	else if (!omap_gpio_is_input(bank, offset))
811 		goto err;
812 	omap_enable_gpio_module(bank, offset);
813 	bank->irq_usage |= BIT(offset);
814 
815 	raw_spin_unlock_irqrestore(&bank->lock, flags);
816 	omap_gpio_unmask_irq(d);
817 
818 	return 0;
819 err:
820 	raw_spin_unlock_irqrestore(&bank->lock, flags);
821 	return -EINVAL;
822 }
823 
824 static void omap_gpio_irq_shutdown(struct irq_data *d)
825 {
826 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
827 	unsigned long flags;
828 	unsigned offset = d->hwirq;
829 
830 	raw_spin_lock_irqsave(&bank->lock, flags);
831 	bank->irq_usage &= ~(BIT(offset));
832 	omap_set_gpio_irqenable(bank, offset, 0);
833 	omap_clear_gpio_irqstatus(bank, offset);
834 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
835 	if (!LINE_USED(bank->mod_usage, offset))
836 		omap_clear_gpio_debounce(bank, offset);
837 	omap_disable_gpio_module(bank, offset);
838 	raw_spin_unlock_irqrestore(&bank->lock, flags);
839 }
840 
841 static void omap_gpio_irq_bus_lock(struct irq_data *data)
842 {
843 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
844 
845 	pm_runtime_get_sync(bank->chip.parent);
846 }
847 
848 static void gpio_irq_bus_sync_unlock(struct irq_data *data)
849 {
850 	struct gpio_bank *bank = omap_irq_data_get_bank(data);
851 
852 	pm_runtime_put(bank->chip.parent);
853 }
854 
855 static void omap_gpio_ack_irq(struct irq_data *d)
856 {
857 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
858 	unsigned offset = d->hwirq;
859 
860 	omap_clear_gpio_irqstatus(bank, offset);
861 }
862 
863 static void omap_gpio_mask_irq(struct irq_data *d)
864 {
865 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
866 	unsigned offset = d->hwirq;
867 	unsigned long flags;
868 
869 	raw_spin_lock_irqsave(&bank->lock, flags);
870 	omap_set_gpio_irqenable(bank, offset, 0);
871 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
872 	raw_spin_unlock_irqrestore(&bank->lock, flags);
873 }
874 
875 static void omap_gpio_unmask_irq(struct irq_data *d)
876 {
877 	struct gpio_bank *bank = omap_irq_data_get_bank(d);
878 	unsigned offset = d->hwirq;
879 	u32 trigger = irqd_get_trigger_type(d);
880 	unsigned long flags;
881 
882 	raw_spin_lock_irqsave(&bank->lock, flags);
883 	if (trigger)
884 		omap_set_gpio_triggering(bank, offset, trigger);
885 
886 	omap_set_gpio_irqenable(bank, offset, 1);
887 
888 	/*
889 	 * For level-triggered GPIOs, clearing must be done after the source
890 	 * is cleared, thus after the handler has run. OMAP4 needs this done
891 	 * after enabing the interrupt to clear the wakeup status.
892 	 */
893 	if (bank->level_mask & BIT(offset))
894 		omap_clear_gpio_irqstatus(bank, offset);
895 
896 	raw_spin_unlock_irqrestore(&bank->lock, flags);
897 }
898 
899 /*---------------------------------------------------------------------*/
900 
901 static int omap_mpuio_suspend_noirq(struct device *dev)
902 {
903 	struct gpio_bank	*bank = dev_get_drvdata(dev);
904 	void __iomem		*mask_reg = bank->base +
905 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
906 	unsigned long		flags;
907 
908 	raw_spin_lock_irqsave(&bank->lock, flags);
909 	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);
910 	raw_spin_unlock_irqrestore(&bank->lock, flags);
911 
912 	return 0;
913 }
914 
915 static int omap_mpuio_resume_noirq(struct device *dev)
916 {
917 	struct gpio_bank	*bank = dev_get_drvdata(dev);
918 	void __iomem		*mask_reg = bank->base +
919 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
920 	unsigned long		flags;
921 
922 	raw_spin_lock_irqsave(&bank->lock, flags);
923 	writel_relaxed(bank->context.wake_en, mask_reg);
924 	raw_spin_unlock_irqrestore(&bank->lock, flags);
925 
926 	return 0;
927 }
928 
929 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
930 	.suspend_noirq = omap_mpuio_suspend_noirq,
931 	.resume_noirq = omap_mpuio_resume_noirq,
932 };
933 
934 /* use platform_driver for this. */
935 static struct platform_driver omap_mpuio_driver = {
936 	.driver		= {
937 		.name	= "mpuio",
938 		.pm	= &omap_mpuio_dev_pm_ops,
939 	},
940 };
941 
942 static struct platform_device omap_mpuio_device = {
943 	.name		= "mpuio",
944 	.id		= -1,
945 	.dev = {
946 		.driver = &omap_mpuio_driver.driver,
947 	}
948 	/* could list the /proc/iomem resources */
949 };
950 
951 static inline void omap_mpuio_init(struct gpio_bank *bank)
952 {
953 	platform_set_drvdata(&omap_mpuio_device, bank);
954 
955 	if (platform_driver_register(&omap_mpuio_driver) == 0)
956 		(void) platform_device_register(&omap_mpuio_device);
957 }
958 
959 /*---------------------------------------------------------------------*/
960 
961 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
962 {
963 	struct gpio_bank *bank;
964 	unsigned long flags;
965 	void __iomem *reg;
966 	int dir;
967 
968 	bank = gpiochip_get_data(chip);
969 	reg = bank->base + bank->regs->direction;
970 	raw_spin_lock_irqsave(&bank->lock, flags);
971 	dir = !!(readl_relaxed(reg) & BIT(offset));
972 	raw_spin_unlock_irqrestore(&bank->lock, flags);
973 	return dir;
974 }
975 
976 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset)
977 {
978 	struct gpio_bank *bank;
979 	unsigned long flags;
980 
981 	bank = gpiochip_get_data(chip);
982 	raw_spin_lock_irqsave(&bank->lock, flags);
983 	omap_set_gpio_direction(bank, offset, 1);
984 	raw_spin_unlock_irqrestore(&bank->lock, flags);
985 	return 0;
986 }
987 
988 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset)
989 {
990 	struct gpio_bank *bank;
991 
992 	bank = gpiochip_get_data(chip);
993 
994 	if (omap_gpio_is_input(bank, offset))
995 		return omap_get_gpio_datain(bank, offset);
996 	else
997 		return omap_get_gpio_dataout(bank, offset);
998 }
999 
1000 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1001 {
1002 	struct gpio_bank *bank;
1003 	unsigned long flags;
1004 
1005 	bank = gpiochip_get_data(chip);
1006 	raw_spin_lock_irqsave(&bank->lock, flags);
1007 	bank->set_dataout(bank, offset, value);
1008 	omap_set_gpio_direction(bank, offset, 0);
1009 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1010 	return 0;
1011 }
1012 
1013 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask,
1014 				  unsigned long *bits)
1015 {
1016 	struct gpio_bank *bank = gpiochip_get_data(chip);
1017 	void __iomem *reg = bank->base + bank->regs->direction;
1018 	unsigned long in = readl_relaxed(reg), l;
1019 
1020 	*bits = 0;
1021 
1022 	l = in & *mask;
1023 	if (l)
1024 		*bits |= omap_get_gpio_datain_multiple(bank, &l);
1025 
1026 	l = ~in & *mask;
1027 	if (l)
1028 		*bits |= omap_get_gpio_dataout_multiple(bank, &l);
1029 
1030 	return 0;
1031 }
1032 
1033 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset,
1034 			      unsigned debounce)
1035 {
1036 	struct gpio_bank *bank;
1037 	unsigned long flags;
1038 	int ret;
1039 
1040 	bank = gpiochip_get_data(chip);
1041 
1042 	raw_spin_lock_irqsave(&bank->lock, flags);
1043 	ret = omap2_set_gpio_debounce(bank, offset, debounce);
1044 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1045 
1046 	if (ret)
1047 		dev_info(chip->parent,
1048 			 "Could not set line %u debounce to %u microseconds (%d)",
1049 			 offset, debounce, ret);
1050 
1051 	return ret;
1052 }
1053 
1054 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1055 				unsigned long config)
1056 {
1057 	u32 debounce;
1058 
1059 	if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1060 		return -ENOTSUPP;
1061 
1062 	debounce = pinconf_to_config_argument(config);
1063 	return omap_gpio_debounce(chip, offset, debounce);
1064 }
1065 
1066 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1067 {
1068 	struct gpio_bank *bank;
1069 	unsigned long flags;
1070 
1071 	bank = gpiochip_get_data(chip);
1072 	raw_spin_lock_irqsave(&bank->lock, flags);
1073 	bank->set_dataout(bank, offset, value);
1074 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1075 }
1076 
1077 static void omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask,
1078 				   unsigned long *bits)
1079 {
1080 	struct gpio_bank *bank = gpiochip_get_data(chip);
1081 	unsigned long flags;
1082 
1083 	raw_spin_lock_irqsave(&bank->lock, flags);
1084 	bank->set_dataout_multiple(bank, mask, bits);
1085 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1086 }
1087 
1088 /*---------------------------------------------------------------------*/
1089 
1090 static void omap_gpio_show_rev(struct gpio_bank *bank)
1091 {
1092 	static bool called;
1093 	u32 rev;
1094 
1095 	if (called || bank->regs->revision == USHRT_MAX)
1096 		return;
1097 
1098 	rev = readw_relaxed(bank->base + bank->regs->revision);
1099 	pr_info("OMAP GPIO hardware version %d.%d\n",
1100 		(rev >> 4) & 0x0f, rev & 0x0f);
1101 
1102 	called = true;
1103 }
1104 
1105 static void omap_gpio_mod_init(struct gpio_bank *bank)
1106 {
1107 	void __iomem *base = bank->base;
1108 	u32 l = 0xffffffff;
1109 
1110 	if (bank->width == 16)
1111 		l = 0xffff;
1112 
1113 	if (bank->is_mpuio) {
1114 		writel_relaxed(l, bank->base + bank->regs->irqenable);
1115 		return;
1116 	}
1117 
1118 	omap_gpio_rmw(base, bank->regs->irqenable, l,
1119 		      bank->regs->irqenable_inv);
1120 	omap_gpio_rmw(base, bank->regs->irqstatus, l,
1121 		      !bank->regs->irqenable_inv);
1122 	if (bank->regs->debounce_en)
1123 		writel_relaxed(0, base + bank->regs->debounce_en);
1124 
1125 	/* Save OE default value (0xffffffff) in the context */
1126 	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);
1127 	 /* Initialize interface clk ungated, module enabled */
1128 	if (bank->regs->ctrl)
1129 		writel_relaxed(0, base + bank->regs->ctrl);
1130 }
1131 
1132 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)
1133 {
1134 	struct gpio_irq_chip *irq;
1135 	static int gpio;
1136 	const char *label;
1137 	int irq_base = 0;
1138 	int ret;
1139 
1140 	/*
1141 	 * REVISIT eventually switch from OMAP-specific gpio structs
1142 	 * over to the generic ones
1143 	 */
1144 	bank->chip.request = omap_gpio_request;
1145 	bank->chip.free = omap_gpio_free;
1146 	bank->chip.get_direction = omap_gpio_get_direction;
1147 	bank->chip.direction_input = omap_gpio_input;
1148 	bank->chip.get = omap_gpio_get;
1149 	bank->chip.get_multiple = omap_gpio_get_multiple;
1150 	bank->chip.direction_output = omap_gpio_output;
1151 	bank->chip.set_config = omap_gpio_set_config;
1152 	bank->chip.set = omap_gpio_set;
1153 	bank->chip.set_multiple = omap_gpio_set_multiple;
1154 	if (bank->is_mpuio) {
1155 		bank->chip.label = "mpuio";
1156 		if (bank->regs->wkup_en)
1157 			bank->chip.parent = &omap_mpuio_device.dev;
1158 		bank->chip.base = OMAP_MPUIO(0);
1159 	} else {
1160 		label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d",
1161 				       gpio, gpio + bank->width - 1);
1162 		if (!label)
1163 			return -ENOMEM;
1164 		bank->chip.label = label;
1165 		bank->chip.base = gpio;
1166 	}
1167 	bank->chip.ngpio = bank->width;
1168 
1169 #ifdef CONFIG_ARCH_OMAP1
1170 	/*
1171 	 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop
1172 	 * irq_alloc_descs() since a base IRQ offset will no longer be needed.
1173 	 */
1174 	irq_base = devm_irq_alloc_descs(bank->chip.parent,
1175 					-1, 0, bank->width, 0);
1176 	if (irq_base < 0) {
1177 		dev_err(bank->chip.parent, "Couldn't allocate IRQ numbers\n");
1178 		return -ENODEV;
1179 	}
1180 #endif
1181 
1182 	/* MPUIO is a bit different, reading IRQ status clears it */
1183 	if (bank->is_mpuio) {
1184 		irqc->irq_ack = dummy_irq_chip.irq_ack;
1185 		if (!bank->regs->wkup_en)
1186 			irqc->irq_set_wake = NULL;
1187 	}
1188 
1189 	irq = &bank->chip.irq;
1190 	irq->chip = irqc;
1191 	irq->handler = handle_bad_irq;
1192 	irq->default_type = IRQ_TYPE_NONE;
1193 	irq->num_parents = 1;
1194 	irq->parents = &bank->irq;
1195 	irq->first = irq_base;
1196 
1197 	ret = gpiochip_add_data(&bank->chip, bank);
1198 	if (ret) {
1199 		dev_err(bank->chip.parent,
1200 			"Could not register gpio chip %d\n", ret);
1201 		return ret;
1202 	}
1203 
1204 	ret = devm_request_irq(bank->chip.parent, bank->irq,
1205 			       omap_gpio_irq_handler,
1206 			       0, dev_name(bank->chip.parent), bank);
1207 	if (ret)
1208 		gpiochip_remove(&bank->chip);
1209 
1210 	if (!bank->is_mpuio)
1211 		gpio += bank->width;
1212 
1213 	return ret;
1214 }
1215 
1216 static void omap_gpio_init_context(struct gpio_bank *p)
1217 {
1218 	struct omap_gpio_reg_offs *regs = p->regs;
1219 	void __iomem *base = p->base;
1220 
1221 	p->context.ctrl		= readl_relaxed(base + regs->ctrl);
1222 	p->context.oe		= readl_relaxed(base + regs->direction);
1223 	p->context.wake_en	= readl_relaxed(base + regs->wkup_en);
1224 	p->context.leveldetect0	= readl_relaxed(base + regs->leveldetect0);
1225 	p->context.leveldetect1	= readl_relaxed(base + regs->leveldetect1);
1226 	p->context.risingdetect	= readl_relaxed(base + regs->risingdetect);
1227 	p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect);
1228 	p->context.irqenable1	= readl_relaxed(base + regs->irqenable);
1229 	p->context.irqenable2	= readl_relaxed(base + regs->irqenable2);
1230 
1231 	if (regs->set_dataout && p->regs->clr_dataout)
1232 		p->context.dataout = readl_relaxed(base + regs->set_dataout);
1233 	else
1234 		p->context.dataout = readl_relaxed(base + regs->dataout);
1235 
1236 	p->context_valid = true;
1237 }
1238 
1239 static void omap_gpio_restore_context(struct gpio_bank *bank)
1240 {
1241 	writel_relaxed(bank->context.wake_en,
1242 				bank->base + bank->regs->wkup_en);
1243 	writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);
1244 	writel_relaxed(bank->context.leveldetect0,
1245 				bank->base + bank->regs->leveldetect0);
1246 	writel_relaxed(bank->context.leveldetect1,
1247 				bank->base + bank->regs->leveldetect1);
1248 	writel_relaxed(bank->context.risingdetect,
1249 				bank->base + bank->regs->risingdetect);
1250 	writel_relaxed(bank->context.fallingdetect,
1251 				bank->base + bank->regs->fallingdetect);
1252 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1253 		writel_relaxed(bank->context.dataout,
1254 				bank->base + bank->regs->set_dataout);
1255 	else
1256 		writel_relaxed(bank->context.dataout,
1257 				bank->base + bank->regs->dataout);
1258 	writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);
1259 
1260 	if (bank->dbck_enable_mask) {
1261 		writel_relaxed(bank->context.debounce, bank->base +
1262 					bank->regs->debounce);
1263 		writel_relaxed(bank->context.debounce_en,
1264 					bank->base + bank->regs->debounce_en);
1265 	}
1266 
1267 	writel_relaxed(bank->context.irqenable1,
1268 				bank->base + bank->regs->irqenable);
1269 	writel_relaxed(bank->context.irqenable2,
1270 				bank->base + bank->regs->irqenable2);
1271 }
1272 
1273 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context)
1274 {
1275 	struct device *dev = bank->chip.parent;
1276 	void __iomem *base = bank->base;
1277 	u32 nowake;
1278 
1279 	bank->saved_datain = readl_relaxed(base + bank->regs->datain);
1280 
1281 	if (!bank->enabled_non_wakeup_gpios)
1282 		goto update_gpio_context_count;
1283 
1284 	if (!may_lose_context)
1285 		goto update_gpio_context_count;
1286 
1287 	/*
1288 	 * If going to OFF, remove triggering for all wkup domain
1289 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1290 	 * generated.  See OMAP2420 Errata item 1.101.
1291 	 */
1292 	if (!bank->loses_context && bank->enabled_non_wakeup_gpios) {
1293 		nowake = bank->enabled_non_wakeup_gpios;
1294 		omap_gpio_rmw(base, bank->regs->fallingdetect, nowake, ~nowake);
1295 		omap_gpio_rmw(base, bank->regs->risingdetect, nowake, ~nowake);
1296 	}
1297 
1298 update_gpio_context_count:
1299 	if (bank->get_context_loss_count)
1300 		bank->context_loss_count =
1301 				bank->get_context_loss_count(dev);
1302 
1303 	omap_gpio_dbck_disable(bank);
1304 }
1305 
1306 static void omap_gpio_unidle(struct gpio_bank *bank)
1307 {
1308 	struct device *dev = bank->chip.parent;
1309 	u32 l = 0, gen, gen0, gen1;
1310 	int c;
1311 
1312 	/*
1313 	 * On the first resume during the probe, the context has not
1314 	 * been initialised and so initialise it now. Also initialise
1315 	 * the context loss count.
1316 	 */
1317 	if (bank->loses_context && !bank->context_valid) {
1318 		omap_gpio_init_context(bank);
1319 
1320 		if (bank->get_context_loss_count)
1321 			bank->context_loss_count =
1322 				bank->get_context_loss_count(dev);
1323 	}
1324 
1325 	omap_gpio_dbck_enable(bank);
1326 
1327 	if (bank->loses_context) {
1328 		if (!bank->get_context_loss_count) {
1329 			omap_gpio_restore_context(bank);
1330 		} else {
1331 			c = bank->get_context_loss_count(dev);
1332 			if (c != bank->context_loss_count) {
1333 				omap_gpio_restore_context(bank);
1334 			} else {
1335 				return;
1336 			}
1337 		}
1338 	} else {
1339 		/* Restore changes done for OMAP2420 errata 1.101 */
1340 		writel_relaxed(bank->context.fallingdetect,
1341 			       bank->base + bank->regs->fallingdetect);
1342 		writel_relaxed(bank->context.risingdetect,
1343 			       bank->base + bank->regs->risingdetect);
1344 	}
1345 
1346 	l = readl_relaxed(bank->base + bank->regs->datain);
1347 
1348 	/*
1349 	 * Check if any of the non-wakeup interrupt GPIOs have changed
1350 	 * state.  If so, generate an IRQ by software.  This is
1351 	 * horribly racy, but it's the best we can do to work around
1352 	 * this silicon bug.
1353 	 */
1354 	l ^= bank->saved_datain;
1355 	l &= bank->enabled_non_wakeup_gpios;
1356 
1357 	/*
1358 	 * No need to generate IRQs for the rising edge for gpio IRQs
1359 	 * configured with falling edge only; and vice versa.
1360 	 */
1361 	gen0 = l & bank->context.fallingdetect;
1362 	gen0 &= bank->saved_datain;
1363 
1364 	gen1 = l & bank->context.risingdetect;
1365 	gen1 &= ~(bank->saved_datain);
1366 
1367 	/* FIXME: Consider GPIO IRQs with level detections properly! */
1368 	gen = l & (~(bank->context.fallingdetect) &
1369 					 ~(bank->context.risingdetect));
1370 	/* Consider all GPIO IRQs needed to be updated */
1371 	gen |= gen0 | gen1;
1372 
1373 	if (gen) {
1374 		u32 old0, old1;
1375 
1376 		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);
1377 		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);
1378 
1379 		if (!bank->regs->irqstatus_raw0) {
1380 			writel_relaxed(old0 | gen, bank->base +
1381 						bank->regs->leveldetect0);
1382 			writel_relaxed(old1 | gen, bank->base +
1383 						bank->regs->leveldetect1);
1384 		}
1385 
1386 		if (bank->regs->irqstatus_raw0) {
1387 			writel_relaxed(old0 | l, bank->base +
1388 						bank->regs->leveldetect0);
1389 			writel_relaxed(old1 | l, bank->base +
1390 						bank->regs->leveldetect1);
1391 		}
1392 		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);
1393 		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);
1394 	}
1395 }
1396 
1397 static int gpio_omap_cpu_notifier(struct notifier_block *nb,
1398 				  unsigned long cmd, void *v)
1399 {
1400 	struct gpio_bank *bank;
1401 	unsigned long flags;
1402 
1403 	bank = container_of(nb, struct gpio_bank, nb);
1404 
1405 	raw_spin_lock_irqsave(&bank->lock, flags);
1406 	switch (cmd) {
1407 	case CPU_CLUSTER_PM_ENTER:
1408 		if (bank->is_suspended)
1409 			break;
1410 		omap_gpio_idle(bank, true);
1411 		break;
1412 	case CPU_CLUSTER_PM_ENTER_FAILED:
1413 	case CPU_CLUSTER_PM_EXIT:
1414 		if (bank->is_suspended)
1415 			break;
1416 		omap_gpio_unidle(bank);
1417 		break;
1418 	}
1419 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1420 
1421 	return NOTIFY_OK;
1422 }
1423 
1424 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1425 	.revision =		OMAP24XX_GPIO_REVISION,
1426 	.direction =		OMAP24XX_GPIO_OE,
1427 	.datain =		OMAP24XX_GPIO_DATAIN,
1428 	.dataout =		OMAP24XX_GPIO_DATAOUT,
1429 	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1430 	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1431 	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1432 	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1433 	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1434 	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1435 	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1436 	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1437 	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1438 	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1439 	.ctrl =			OMAP24XX_GPIO_CTRL,
1440 	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1441 	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1442 	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1443 	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1444 	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1445 };
1446 
1447 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1448 	.revision =		OMAP4_GPIO_REVISION,
1449 	.direction =		OMAP4_GPIO_OE,
1450 	.datain =		OMAP4_GPIO_DATAIN,
1451 	.dataout =		OMAP4_GPIO_DATAOUT,
1452 	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1453 	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1454 	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1455 	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1456 	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1457 	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1458 	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1459 	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1460 	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1461 	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1462 	.ctrl =			OMAP4_GPIO_CTRL,
1463 	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1464 	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1465 	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1466 	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1467 	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1468 };
1469 
1470 static const struct omap_gpio_platform_data omap2_pdata = {
1471 	.regs = &omap2_gpio_regs,
1472 	.bank_width = 32,
1473 	.dbck_flag = false,
1474 };
1475 
1476 static const struct omap_gpio_platform_data omap3_pdata = {
1477 	.regs = &omap2_gpio_regs,
1478 	.bank_width = 32,
1479 	.dbck_flag = true,
1480 };
1481 
1482 static const struct omap_gpio_platform_data omap4_pdata = {
1483 	.regs = &omap4_gpio_regs,
1484 	.bank_width = 32,
1485 	.dbck_flag = true,
1486 };
1487 
1488 static const struct of_device_id omap_gpio_match[] = {
1489 	{
1490 		.compatible = "ti,omap4-gpio",
1491 		.data = &omap4_pdata,
1492 	},
1493 	{
1494 		.compatible = "ti,omap3-gpio",
1495 		.data = &omap3_pdata,
1496 	},
1497 	{
1498 		.compatible = "ti,omap2-gpio",
1499 		.data = &omap2_pdata,
1500 	},
1501 	{ },
1502 };
1503 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1504 
1505 static int omap_gpio_probe(struct platform_device *pdev)
1506 {
1507 	struct device *dev = &pdev->dev;
1508 	struct device_node *node = dev->of_node;
1509 	const struct of_device_id *match;
1510 	const struct omap_gpio_platform_data *pdata;
1511 	struct gpio_bank *bank;
1512 	struct irq_chip *irqc;
1513 	int ret;
1514 
1515 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1516 
1517 	pdata = match ? match->data : dev_get_platdata(dev);
1518 	if (!pdata)
1519 		return -EINVAL;
1520 
1521 	bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
1522 	if (!bank)
1523 		return -ENOMEM;
1524 
1525 	irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL);
1526 	if (!irqc)
1527 		return -ENOMEM;
1528 
1529 	irqc->irq_startup = omap_gpio_irq_startup,
1530 	irqc->irq_shutdown = omap_gpio_irq_shutdown,
1531 	irqc->irq_ack = omap_gpio_ack_irq,
1532 	irqc->irq_mask = omap_gpio_mask_irq,
1533 	irqc->irq_unmask = omap_gpio_unmask_irq,
1534 	irqc->irq_set_type = omap_gpio_irq_type,
1535 	irqc->irq_set_wake = omap_gpio_wake_enable,
1536 	irqc->irq_bus_lock = omap_gpio_irq_bus_lock,
1537 	irqc->irq_bus_sync_unlock = gpio_irq_bus_sync_unlock,
1538 	irqc->name = dev_name(&pdev->dev);
1539 	irqc->flags = IRQCHIP_MASK_ON_SUSPEND;
1540 	irqc->parent_device = dev;
1541 
1542 	bank->irq = platform_get_irq(pdev, 0);
1543 	if (bank->irq <= 0) {
1544 		if (!bank->irq)
1545 			bank->irq = -ENXIO;
1546 		if (bank->irq != -EPROBE_DEFER)
1547 			dev_err(dev,
1548 				"can't get irq resource ret=%d\n", bank->irq);
1549 		return bank->irq;
1550 	}
1551 
1552 	bank->chip.parent = dev;
1553 	bank->chip.owner = THIS_MODULE;
1554 	bank->dbck_flag = pdata->dbck_flag;
1555 	bank->stride = pdata->bank_stride;
1556 	bank->width = pdata->bank_width;
1557 	bank->is_mpuio = pdata->is_mpuio;
1558 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1559 	bank->regs = pdata->regs;
1560 #ifdef CONFIG_OF_GPIO
1561 	bank->chip.of_node = of_node_get(node);
1562 #endif
1563 
1564 	if (node) {
1565 		if (!of_property_read_bool(node, "ti,gpio-always-on"))
1566 			bank->loses_context = true;
1567 	} else {
1568 		bank->loses_context = pdata->loses_context;
1569 
1570 		if (bank->loses_context)
1571 			bank->get_context_loss_count =
1572 				pdata->get_context_loss_count;
1573 	}
1574 
1575 	if (bank->regs->set_dataout && bank->regs->clr_dataout) {
1576 		bank->set_dataout = omap_set_gpio_dataout_reg;
1577 		bank->set_dataout_multiple = omap_set_gpio_dataout_reg_multiple;
1578 	} else {
1579 		bank->set_dataout = omap_set_gpio_dataout_mask;
1580 		bank->set_dataout_multiple =
1581 				omap_set_gpio_dataout_mask_multiple;
1582 	}
1583 
1584 	raw_spin_lock_init(&bank->lock);
1585 	raw_spin_lock_init(&bank->wa_lock);
1586 
1587 	/* Static mapping, never released */
1588 	bank->base = devm_platform_ioremap_resource(pdev, 0);
1589 	if (IS_ERR(bank->base)) {
1590 		return PTR_ERR(bank->base);
1591 	}
1592 
1593 	if (bank->dbck_flag) {
1594 		bank->dbck = devm_clk_get(dev, "dbclk");
1595 		if (IS_ERR(bank->dbck)) {
1596 			dev_err(dev,
1597 				"Could not get gpio dbck. Disable debounce\n");
1598 			bank->dbck_flag = false;
1599 		} else {
1600 			clk_prepare(bank->dbck);
1601 		}
1602 	}
1603 
1604 	platform_set_drvdata(pdev, bank);
1605 
1606 	pm_runtime_enable(dev);
1607 	pm_runtime_get_sync(dev);
1608 
1609 	if (bank->is_mpuio)
1610 		omap_mpuio_init(bank);
1611 
1612 	omap_gpio_mod_init(bank);
1613 
1614 	ret = omap_gpio_chip_init(bank, irqc);
1615 	if (ret) {
1616 		pm_runtime_put_sync(dev);
1617 		pm_runtime_disable(dev);
1618 		if (bank->dbck_flag)
1619 			clk_unprepare(bank->dbck);
1620 		return ret;
1621 	}
1622 
1623 	omap_gpio_show_rev(bank);
1624 
1625 	bank->nb.notifier_call = gpio_omap_cpu_notifier;
1626 	cpu_pm_register_notifier(&bank->nb);
1627 
1628 	pm_runtime_put(dev);
1629 
1630 	return 0;
1631 }
1632 
1633 static int omap_gpio_remove(struct platform_device *pdev)
1634 {
1635 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1636 
1637 	cpu_pm_unregister_notifier(&bank->nb);
1638 	list_del(&bank->node);
1639 	gpiochip_remove(&bank->chip);
1640 	pm_runtime_disable(&pdev->dev);
1641 	if (bank->dbck_flag)
1642 		clk_unprepare(bank->dbck);
1643 
1644 	return 0;
1645 }
1646 
1647 static int __maybe_unused omap_gpio_runtime_suspend(struct device *dev)
1648 {
1649 	struct gpio_bank *bank = dev_get_drvdata(dev);
1650 	unsigned long flags;
1651 
1652 	raw_spin_lock_irqsave(&bank->lock, flags);
1653 	omap_gpio_idle(bank, true);
1654 	bank->is_suspended = true;
1655 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1656 
1657 	return 0;
1658 }
1659 
1660 static int __maybe_unused omap_gpio_runtime_resume(struct device *dev)
1661 {
1662 	struct gpio_bank *bank = dev_get_drvdata(dev);
1663 	unsigned long flags;
1664 
1665 	raw_spin_lock_irqsave(&bank->lock, flags);
1666 	omap_gpio_unidle(bank);
1667 	bank->is_suspended = false;
1668 	raw_spin_unlock_irqrestore(&bank->lock, flags);
1669 
1670 	return 0;
1671 }
1672 
1673 static const struct dev_pm_ops gpio_pm_ops = {
1674 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1675 									NULL)
1676 };
1677 
1678 static struct platform_driver omap_gpio_driver = {
1679 	.probe		= omap_gpio_probe,
1680 	.remove		= omap_gpio_remove,
1681 	.driver		= {
1682 		.name	= "omap_gpio",
1683 		.pm	= &gpio_pm_ops,
1684 		.of_match_table = omap_gpio_match,
1685 	},
1686 };
1687 
1688 /*
1689  * gpio driver register needs to be done before
1690  * machine_init functions access gpio APIs.
1691  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1692  */
1693 static int __init omap_gpio_drv_reg(void)
1694 {
1695 	return platform_driver_register(&omap_gpio_driver);
1696 }
1697 postcore_initcall(omap_gpio_drv_reg);
1698 
1699 static void __exit omap_gpio_exit(void)
1700 {
1701 	platform_driver_unregister(&omap_gpio_driver);
1702 }
1703 module_exit(omap_gpio_exit);
1704 
1705 MODULE_DESCRIPTION("omap gpio driver");
1706 MODULE_ALIAS("platform:gpio-omap");
1707 MODULE_LICENSE("GPL v2");
1708