1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support functions for OMAP GPIO 4 * 5 * Copyright (C) 2003-2005 Nokia Corporation 6 * Written by Juha Yrjölä <juha.yrjola@nokia.com> 7 * 8 * Copyright (C) 2009 Texas Instruments 9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 10 */ 11 12 #include <linux/init.h> 13 #include <linux/module.h> 14 #include <linux/interrupt.h> 15 #include <linux/seq_file.h> 16 #include <linux/syscore_ops.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/io.h> 20 #include <linux/cpu_pm.h> 21 #include <linux/device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/pm.h> 24 #include <linux/of.h> 25 #include <linux/gpio/driver.h> 26 #include <linux/bitops.h> 27 #include <linux/platform_data/gpio-omap.h> 28 29 #define OMAP4_GPIO_DEBOUNCINGTIME_MASK 0xFF 30 31 struct gpio_regs { 32 u32 sysconfig; 33 u32 irqenable1; 34 u32 irqenable2; 35 u32 wake_en; 36 u32 ctrl; 37 u32 oe; 38 u32 leveldetect0; 39 u32 leveldetect1; 40 u32 risingdetect; 41 u32 fallingdetect; 42 u32 dataout; 43 u32 debounce; 44 u32 debounce_en; 45 }; 46 47 struct gpio_bank { 48 void __iomem *base; 49 const struct omap_gpio_reg_offs *regs; 50 struct device *dev; 51 52 int irq; 53 u32 non_wakeup_gpios; 54 u32 enabled_non_wakeup_gpios; 55 struct gpio_regs context; 56 u32 saved_datain; 57 u32 level_mask; 58 u32 toggle_mask; 59 raw_spinlock_t lock; 60 raw_spinlock_t wa_lock; 61 struct gpio_chip chip; 62 struct clk *dbck; 63 struct notifier_block nb; 64 unsigned int is_suspended:1; 65 unsigned int needs_resume:1; 66 u32 mod_usage; 67 u32 irq_usage; 68 u32 dbck_enable_mask; 69 bool dbck_enabled; 70 bool is_mpuio; 71 bool dbck_flag; 72 bool loses_context; 73 bool context_valid; 74 int stride; 75 u32 width; 76 int context_loss_count; 77 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 79 int (*get_context_loss_count)(struct device *dev); 80 }; 81 82 #define GPIO_MOD_CTRL_BIT BIT(0) 83 84 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 85 #define LINE_USED(line, offset) (line & (BIT(offset))) 86 87 static void omap_gpio_unmask_irq(struct irq_data *d); 88 89 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 90 { 91 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 92 return gpiochip_get_data(chip); 93 } 94 95 static inline u32 omap_gpio_rmw(void __iomem *reg, u32 mask, bool set) 96 { 97 u32 val = readl_relaxed(reg); 98 99 if (set) 100 val |= mask; 101 else 102 val &= ~mask; 103 104 writel_relaxed(val, reg); 105 106 return val; 107 } 108 109 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, 110 int is_input) 111 { 112 bank->context.oe = omap_gpio_rmw(bank->base + bank->regs->direction, 113 BIT(gpio), is_input); 114 } 115 116 117 /* set data out value using dedicate set/clear register */ 118 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, 119 int enable) 120 { 121 void __iomem *reg = bank->base; 122 u32 l = BIT(offset); 123 124 if (enable) { 125 reg += bank->regs->set_dataout; 126 bank->context.dataout |= l; 127 } else { 128 reg += bank->regs->clr_dataout; 129 bank->context.dataout &= ~l; 130 } 131 132 writel_relaxed(l, reg); 133 } 134 135 /* set data out value using mask register */ 136 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, 137 int enable) 138 { 139 bank->context.dataout = omap_gpio_rmw(bank->base + bank->regs->dataout, 140 BIT(offset), enable); 141 } 142 143 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) 144 { 145 if (bank->dbck_enable_mask && !bank->dbck_enabled) { 146 clk_enable(bank->dbck); 147 bank->dbck_enabled = true; 148 149 writel_relaxed(bank->dbck_enable_mask, 150 bank->base + bank->regs->debounce_en); 151 } 152 } 153 154 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) 155 { 156 if (bank->dbck_enable_mask && bank->dbck_enabled) { 157 /* 158 * Disable debounce before cutting it's clock. If debounce is 159 * enabled but the clock is not, GPIO module seems to be unable 160 * to detect events and generate interrupts at least on OMAP3. 161 */ 162 writel_relaxed(0, bank->base + bank->regs->debounce_en); 163 164 clk_disable(bank->dbck); 165 bank->dbck_enabled = false; 166 } 167 } 168 169 /** 170 * omap2_set_gpio_debounce - low level gpio debounce time 171 * @bank: the gpio bank we're acting upon 172 * @offset: the gpio number on this @bank 173 * @debounce: debounce time to use 174 * 175 * OMAP's debounce time is in 31us steps 176 * <debounce time> = (GPIO_DEBOUNCINGTIME[7:0].DEBOUNCETIME + 1) x 31 177 * so we need to convert and round up to the closest unit. 178 * 179 * Return: 0 on success, negative error otherwise. 180 */ 181 static int omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, 182 unsigned debounce) 183 { 184 u32 val; 185 u32 l; 186 bool enable = !!debounce; 187 188 if (!bank->dbck_flag) 189 return -ENOTSUPP; 190 191 if (enable) { 192 debounce = DIV_ROUND_UP(debounce, 31) - 1; 193 if ((debounce & OMAP4_GPIO_DEBOUNCINGTIME_MASK) != debounce) 194 return -EINVAL; 195 } 196 197 l = BIT(offset); 198 199 clk_enable(bank->dbck); 200 writel_relaxed(debounce, bank->base + bank->regs->debounce); 201 202 val = omap_gpio_rmw(bank->base + bank->regs->debounce_en, l, enable); 203 bank->dbck_enable_mask = val; 204 205 clk_disable(bank->dbck); 206 /* 207 * Enable debounce clock per module. 208 * This call is mandatory because in omap_gpio_request() when 209 * *_runtime_get_sync() is called, _gpio_dbck_enable() within 210 * runtime callbck fails to turn on dbck because dbck_enable_mask 211 * used within _gpio_dbck_enable() is still not initialized at 212 * that point. Therefore we have to enable dbck here. 213 */ 214 omap_gpio_dbck_enable(bank); 215 if (bank->dbck_enable_mask) { 216 bank->context.debounce = debounce; 217 bank->context.debounce_en = val; 218 } 219 220 return 0; 221 } 222 223 /** 224 * omap_clear_gpio_debounce - clear debounce settings for a gpio 225 * @bank: the gpio bank we're acting upon 226 * @offset: the gpio number on this @bank 227 * 228 * If a gpio is using debounce, then clear the debounce enable bit and if 229 * this is the only gpio in this bank using debounce, then clear the debounce 230 * time too. The debounce clock will also be disabled when calling this function 231 * if this is the only gpio in the bank using debounce. 232 */ 233 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) 234 { 235 u32 gpio_bit = BIT(offset); 236 237 if (!bank->dbck_flag) 238 return; 239 240 if (!(bank->dbck_enable_mask & gpio_bit)) 241 return; 242 243 bank->dbck_enable_mask &= ~gpio_bit; 244 bank->context.debounce_en &= ~gpio_bit; 245 writel_relaxed(bank->context.debounce_en, 246 bank->base + bank->regs->debounce_en); 247 248 if (!bank->dbck_enable_mask) { 249 bank->context.debounce = 0; 250 writel_relaxed(bank->context.debounce, bank->base + 251 bank->regs->debounce); 252 clk_disable(bank->dbck); 253 bank->dbck_enabled = false; 254 } 255 } 256 257 /* 258 * Off mode wake-up capable GPIOs in bank(s) that are in the wakeup domain. 259 * See TRM section for GPIO for "Wake-Up Generation" for the list of GPIOs 260 * in wakeup domain. If bank->non_wakeup_gpios is not configured, assume none 261 * are capable waking up the system from off mode. 262 */ 263 static bool omap_gpio_is_off_wakeup_capable(struct gpio_bank *bank, u32 gpio_mask) 264 { 265 u32 no_wake = bank->non_wakeup_gpios; 266 267 if (no_wake) 268 return !!(~no_wake & gpio_mask); 269 270 return false; 271 } 272 273 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, 274 unsigned trigger) 275 { 276 void __iomem *base = bank->base; 277 u32 gpio_bit = BIT(gpio); 278 279 omap_gpio_rmw(base + bank->regs->leveldetect0, gpio_bit, 280 trigger & IRQ_TYPE_LEVEL_LOW); 281 omap_gpio_rmw(base + bank->regs->leveldetect1, gpio_bit, 282 trigger & IRQ_TYPE_LEVEL_HIGH); 283 284 /* 285 * We need the edge detection enabled for to allow the GPIO block 286 * to be woken from idle state. Set the appropriate edge detection 287 * in addition to the level detection. 288 */ 289 omap_gpio_rmw(base + bank->regs->risingdetect, gpio_bit, 290 trigger & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)); 291 omap_gpio_rmw(base + bank->regs->fallingdetect, gpio_bit, 292 trigger & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)); 293 294 bank->context.leveldetect0 = 295 readl_relaxed(bank->base + bank->regs->leveldetect0); 296 bank->context.leveldetect1 = 297 readl_relaxed(bank->base + bank->regs->leveldetect1); 298 bank->context.risingdetect = 299 readl_relaxed(bank->base + bank->regs->risingdetect); 300 bank->context.fallingdetect = 301 readl_relaxed(bank->base + bank->regs->fallingdetect); 302 303 bank->level_mask = bank->context.leveldetect0 | 304 bank->context.leveldetect1; 305 306 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 307 if (!bank->regs->irqctrl && !omap_gpio_is_off_wakeup_capable(bank, gpio)) { 308 /* 309 * Log the edge gpio and manually trigger the IRQ 310 * after resume if the input level changes 311 * to avoid irq lost during PER RET/OFF mode 312 * Applies for omap2 non-wakeup gpio and all omap3 gpios 313 */ 314 if (trigger & IRQ_TYPE_EDGE_BOTH) 315 bank->enabled_non_wakeup_gpios |= gpio_bit; 316 else 317 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 318 } 319 } 320 321 /* 322 * This only applies to chips that can't do both rising and falling edge 323 * detection at once. For all other chips, this function is a noop. 324 */ 325 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 326 { 327 if (IS_ENABLED(CONFIG_ARCH_OMAP1) && bank->regs->irqctrl) { 328 void __iomem *reg = bank->base + bank->regs->irqctrl; 329 330 writel_relaxed(readl_relaxed(reg) ^ BIT(gpio), reg); 331 } 332 } 333 334 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, 335 unsigned trigger) 336 { 337 void __iomem *reg = bank->base; 338 u32 l = 0; 339 340 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 341 omap_set_gpio_trigger(bank, gpio, trigger); 342 } else if (bank->regs->irqctrl) { 343 reg += bank->regs->irqctrl; 344 345 l = readl_relaxed(reg); 346 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 347 bank->toggle_mask |= BIT(gpio); 348 if (trigger & IRQ_TYPE_EDGE_RISING) 349 l |= BIT(gpio); 350 else if (trigger & IRQ_TYPE_EDGE_FALLING) 351 l &= ~(BIT(gpio)); 352 else 353 return -EINVAL; 354 355 writel_relaxed(l, reg); 356 } else if (bank->regs->edgectrl1) { 357 if (gpio & 0x08) 358 reg += bank->regs->edgectrl2; 359 else 360 reg += bank->regs->edgectrl1; 361 362 gpio &= 0x07; 363 l = readl_relaxed(reg); 364 l &= ~(3 << (gpio << 1)); 365 if (trigger & IRQ_TYPE_EDGE_RISING) 366 l |= 2 << (gpio << 1); 367 if (trigger & IRQ_TYPE_EDGE_FALLING) 368 l |= BIT(gpio << 1); 369 writel_relaxed(l, reg); 370 } 371 return 0; 372 } 373 374 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) 375 { 376 if (bank->regs->pinctrl) { 377 void __iomem *reg = bank->base + bank->regs->pinctrl; 378 379 /* Claim the pin for MPU */ 380 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); 381 } 382 383 if (bank->regs->ctrl && !BANK_USED(bank)) { 384 void __iomem *reg = bank->base + bank->regs->ctrl; 385 u32 ctrl; 386 387 ctrl = readl_relaxed(reg); 388 /* Module is enabled, clocks are not gated */ 389 ctrl &= ~GPIO_MOD_CTRL_BIT; 390 writel_relaxed(ctrl, reg); 391 bank->context.ctrl = ctrl; 392 } 393 } 394 395 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) 396 { 397 if (bank->regs->ctrl && !BANK_USED(bank)) { 398 void __iomem *reg = bank->base + bank->regs->ctrl; 399 u32 ctrl; 400 401 ctrl = readl_relaxed(reg); 402 /* Module is disabled, clocks are gated */ 403 ctrl |= GPIO_MOD_CTRL_BIT; 404 writel_relaxed(ctrl, reg); 405 bank->context.ctrl = ctrl; 406 } 407 } 408 409 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) 410 { 411 void __iomem *reg = bank->base + bank->regs->direction; 412 413 return readl_relaxed(reg) & BIT(offset); 414 } 415 416 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) 417 { 418 if (!LINE_USED(bank->mod_usage, offset)) { 419 omap_enable_gpio_module(bank, offset); 420 omap_set_gpio_direction(bank, offset, 1); 421 } 422 bank->irq_usage |= BIT(offset); 423 } 424 425 static int omap_gpio_irq_type(struct irq_data *d, unsigned type) 426 { 427 struct gpio_bank *bank = omap_irq_data_get_bank(d); 428 int retval; 429 unsigned long flags; 430 unsigned offset = d->hwirq; 431 432 if (type & ~IRQ_TYPE_SENSE_MASK) 433 return -EINVAL; 434 435 if (!bank->regs->leveldetect0 && (type & IRQ_TYPE_LEVEL_MASK)) 436 return -EINVAL; 437 438 raw_spin_lock_irqsave(&bank->lock, flags); 439 retval = omap_set_gpio_triggering(bank, offset, type); 440 if (retval) { 441 raw_spin_unlock_irqrestore(&bank->lock, flags); 442 goto error; 443 } 444 omap_gpio_init_irq(bank, offset); 445 if (!omap_gpio_is_input(bank, offset)) { 446 raw_spin_unlock_irqrestore(&bank->lock, flags); 447 retval = -EINVAL; 448 goto error; 449 } 450 raw_spin_unlock_irqrestore(&bank->lock, flags); 451 452 if (type & IRQ_TYPE_LEVEL_MASK) 453 irq_set_handler_locked(d, handle_level_irq); 454 else if (type & IRQ_TYPE_EDGE_BOTH) 455 /* 456 * Edge IRQs are already cleared/acked in irq_handler and 457 * not need to be masked, as result handle_edge_irq() 458 * logic is excessed here and may cause lose of interrupts. 459 * So just use handle_simple_irq. 460 */ 461 irq_set_handler_locked(d, handle_simple_irq); 462 463 return 0; 464 465 error: 466 return retval; 467 } 468 469 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 470 { 471 void __iomem *reg = bank->base; 472 473 reg += bank->regs->irqstatus; 474 writel_relaxed(gpio_mask, reg); 475 476 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 477 if (bank->regs->irqstatus2) { 478 reg = bank->base + bank->regs->irqstatus2; 479 writel_relaxed(gpio_mask, reg); 480 } 481 482 /* Flush posted write for the irq status to avoid spurious interrupts */ 483 readl_relaxed(reg); 484 } 485 486 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, 487 unsigned offset) 488 { 489 omap_clear_gpio_irqbank(bank, BIT(offset)); 490 } 491 492 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 493 { 494 void __iomem *reg = bank->base; 495 u32 l; 496 u32 mask = (BIT(bank->width)) - 1; 497 498 reg += bank->regs->irqenable; 499 l = readl_relaxed(reg); 500 if (bank->regs->irqenable_inv) 501 l = ~l; 502 l &= mask; 503 return l; 504 } 505 506 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, 507 unsigned offset, int enable) 508 { 509 void __iomem *reg = bank->base; 510 u32 gpio_mask = BIT(offset); 511 512 if (bank->regs->set_irqenable && bank->regs->clr_irqenable) { 513 if (enable) { 514 reg += bank->regs->set_irqenable; 515 bank->context.irqenable1 |= gpio_mask; 516 } else { 517 reg += bank->regs->clr_irqenable; 518 bank->context.irqenable1 &= ~gpio_mask; 519 } 520 writel_relaxed(gpio_mask, reg); 521 } else { 522 bank->context.irqenable1 = 523 omap_gpio_rmw(reg + bank->regs->irqenable, gpio_mask, 524 enable ^ bank->regs->irqenable_inv); 525 } 526 527 /* 528 * Program GPIO wakeup along with IRQ enable to satisfy OMAP4430 TRM 529 * note requiring correlation between the IRQ enable registers and 530 * the wakeup registers. In any case, we want wakeup from idle 531 * enabled for the GPIOs which support this feature. 532 */ 533 if (bank->regs->wkup_en && 534 (bank->regs->edgectrl1 || !(bank->non_wakeup_gpios & gpio_mask))) { 535 bank->context.wake_en = 536 omap_gpio_rmw(bank->base + bank->regs->wkup_en, 537 gpio_mask, enable); 538 } 539 } 540 541 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 542 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) 543 { 544 struct gpio_bank *bank = omap_irq_data_get_bank(d); 545 546 return irq_set_irq_wake(bank->irq, enable); 547 } 548 549 /* 550 * We need to unmask the GPIO bank interrupt as soon as possible to 551 * avoid missing GPIO interrupts for other lines in the bank. 552 * Then we need to mask-read-clear-unmask the triggered GPIO lines 553 * in the bank to avoid missing nested interrupts for a GPIO line. 554 * If we wait to unmask individual GPIO lines in the bank after the 555 * line's interrupt handler has been run, we may miss some nested 556 * interrupts. 557 */ 558 static irqreturn_t omap_gpio_irq_handler(int irq, void *gpiobank) 559 { 560 void __iomem *isr_reg = NULL; 561 u32 enabled, isr, edge; 562 unsigned int bit; 563 struct gpio_bank *bank = gpiobank; 564 unsigned long wa_lock_flags; 565 unsigned long lock_flags; 566 567 isr_reg = bank->base + bank->regs->irqstatus; 568 if (WARN_ON(!isr_reg)) 569 goto exit; 570 571 if (WARN_ONCE(!pm_runtime_active(bank->chip.parent), 572 "gpio irq%i while runtime suspended?\n", irq)) 573 return IRQ_NONE; 574 575 while (1) { 576 raw_spin_lock_irqsave(&bank->lock, lock_flags); 577 578 enabled = omap_get_gpio_irqbank_mask(bank); 579 isr = readl_relaxed(isr_reg) & enabled; 580 581 /* 582 * Clear edge sensitive interrupts before calling handler(s) 583 * so subsequent edge transitions are not missed while the 584 * handlers are running. 585 */ 586 edge = isr & ~bank->level_mask; 587 if (edge) 588 omap_clear_gpio_irqbank(bank, edge); 589 590 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 591 592 if (!isr) 593 break; 594 595 while (isr) { 596 bit = __ffs(isr); 597 isr &= ~(BIT(bit)); 598 599 raw_spin_lock_irqsave(&bank->lock, lock_flags); 600 /* 601 * Some chips can't respond to both rising and falling 602 * at the same time. If this irq was requested with 603 * both flags, we need to flip the ICR data for the IRQ 604 * to respond to the IRQ for the opposite direction. 605 * This will be indicated in the bank toggle_mask. 606 */ 607 if (bank->toggle_mask & (BIT(bit))) 608 omap_toggle_gpio_edge_triggering(bank, bit); 609 610 raw_spin_unlock_irqrestore(&bank->lock, lock_flags); 611 612 raw_spin_lock_irqsave(&bank->wa_lock, wa_lock_flags); 613 614 generic_handle_domain_irq(bank->chip.irq.domain, bit); 615 616 raw_spin_unlock_irqrestore(&bank->wa_lock, 617 wa_lock_flags); 618 } 619 } 620 exit: 621 return IRQ_HANDLED; 622 } 623 624 static unsigned int omap_gpio_irq_startup(struct irq_data *d) 625 { 626 struct gpio_bank *bank = omap_irq_data_get_bank(d); 627 unsigned long flags; 628 unsigned offset = d->hwirq; 629 630 raw_spin_lock_irqsave(&bank->lock, flags); 631 632 if (!LINE_USED(bank->mod_usage, offset)) 633 omap_set_gpio_direction(bank, offset, 1); 634 omap_enable_gpio_module(bank, offset); 635 bank->irq_usage |= BIT(offset); 636 637 raw_spin_unlock_irqrestore(&bank->lock, flags); 638 omap_gpio_unmask_irq(d); 639 640 return 0; 641 } 642 643 static void omap_gpio_irq_shutdown(struct irq_data *d) 644 { 645 struct gpio_bank *bank = omap_irq_data_get_bank(d); 646 unsigned long flags; 647 unsigned offset = d->hwirq; 648 649 raw_spin_lock_irqsave(&bank->lock, flags); 650 bank->irq_usage &= ~(BIT(offset)); 651 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 652 omap_clear_gpio_irqstatus(bank, offset); 653 omap_set_gpio_irqenable(bank, offset, 0); 654 if (!LINE_USED(bank->mod_usage, offset)) 655 omap_clear_gpio_debounce(bank, offset); 656 omap_disable_gpio_module(bank, offset); 657 raw_spin_unlock_irqrestore(&bank->lock, flags); 658 } 659 660 static void omap_gpio_irq_bus_lock(struct irq_data *data) 661 { 662 struct gpio_bank *bank = omap_irq_data_get_bank(data); 663 664 pm_runtime_get_sync(bank->chip.parent); 665 } 666 667 static void gpio_irq_bus_sync_unlock(struct irq_data *data) 668 { 669 struct gpio_bank *bank = omap_irq_data_get_bank(data); 670 671 pm_runtime_put(bank->chip.parent); 672 } 673 674 static void omap_gpio_mask_irq(struct irq_data *d) 675 { 676 struct gpio_bank *bank = omap_irq_data_get_bank(d); 677 unsigned offset = d->hwirq; 678 unsigned long flags; 679 680 raw_spin_lock_irqsave(&bank->lock, flags); 681 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 682 omap_set_gpio_irqenable(bank, offset, 0); 683 raw_spin_unlock_irqrestore(&bank->lock, flags); 684 gpiochip_disable_irq(&bank->chip, offset); 685 } 686 687 static void omap_gpio_unmask_irq(struct irq_data *d) 688 { 689 struct gpio_bank *bank = omap_irq_data_get_bank(d); 690 unsigned offset = d->hwirq; 691 u32 trigger = irqd_get_trigger_type(d); 692 unsigned long flags; 693 694 gpiochip_enable_irq(&bank->chip, offset); 695 raw_spin_lock_irqsave(&bank->lock, flags); 696 omap_set_gpio_irqenable(bank, offset, 1); 697 698 /* 699 * For level-triggered GPIOs, clearing must be done after the source 700 * is cleared, thus after the handler has run. OMAP4 needs this done 701 * after enabing the interrupt to clear the wakeup status. 702 */ 703 if (bank->regs->leveldetect0 && bank->regs->wkup_en && 704 trigger & IRQ_TYPE_LEVEL_MASK) 705 omap_clear_gpio_irqstatus(bank, offset); 706 707 if (trigger) 708 omap_set_gpio_triggering(bank, offset, trigger); 709 710 raw_spin_unlock_irqrestore(&bank->lock, flags); 711 } 712 713 static void omap_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 714 { 715 struct gpio_bank *bank = omap_irq_data_get_bank(d); 716 717 seq_puts(p, dev_name(bank->dev)); 718 } 719 720 static const struct irq_chip omap_gpio_irq_chip = { 721 .irq_startup = omap_gpio_irq_startup, 722 .irq_shutdown = omap_gpio_irq_shutdown, 723 .irq_mask = omap_gpio_mask_irq, 724 .irq_unmask = omap_gpio_unmask_irq, 725 .irq_set_type = omap_gpio_irq_type, 726 .irq_set_wake = omap_gpio_wake_enable, 727 .irq_bus_lock = omap_gpio_irq_bus_lock, 728 .irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, 729 .irq_print_chip = omap_gpio_irq_print_chip, 730 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 731 GPIOCHIP_IRQ_RESOURCE_HELPERS, 732 }; 733 734 static const struct irq_chip omap_gpio_irq_chip_nowake = { 735 .irq_startup = omap_gpio_irq_startup, 736 .irq_shutdown = omap_gpio_irq_shutdown, 737 .irq_mask = omap_gpio_mask_irq, 738 .irq_unmask = omap_gpio_unmask_irq, 739 .irq_set_type = omap_gpio_irq_type, 740 .irq_bus_lock = omap_gpio_irq_bus_lock, 741 .irq_bus_sync_unlock = gpio_irq_bus_sync_unlock, 742 .irq_print_chip = omap_gpio_irq_print_chip, 743 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 744 GPIOCHIP_IRQ_RESOURCE_HELPERS, 745 }; 746 747 /*---------------------------------------------------------------------*/ 748 749 static int omap_mpuio_suspend_noirq(struct device *dev) 750 { 751 struct gpio_bank *bank = dev_get_drvdata(dev); 752 void __iomem *mask_reg = bank->base + 753 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 754 unsigned long flags; 755 756 raw_spin_lock_irqsave(&bank->lock, flags); 757 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); 758 raw_spin_unlock_irqrestore(&bank->lock, flags); 759 760 return 0; 761 } 762 763 static int omap_mpuio_resume_noirq(struct device *dev) 764 { 765 struct gpio_bank *bank = dev_get_drvdata(dev); 766 void __iomem *mask_reg = bank->base + 767 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 768 unsigned long flags; 769 770 raw_spin_lock_irqsave(&bank->lock, flags); 771 writel_relaxed(bank->context.wake_en, mask_reg); 772 raw_spin_unlock_irqrestore(&bank->lock, flags); 773 774 return 0; 775 } 776 777 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 778 .suspend_noirq = omap_mpuio_suspend_noirq, 779 .resume_noirq = omap_mpuio_resume_noirq, 780 }; 781 782 /* use platform_driver for this. */ 783 static struct platform_driver omap_mpuio_driver = { 784 .driver = { 785 .name = "mpuio", 786 .pm = &omap_mpuio_dev_pm_ops, 787 }, 788 }; 789 790 static struct platform_device omap_mpuio_device = { 791 .name = "mpuio", 792 .id = -1, 793 .dev = { 794 .driver = &omap_mpuio_driver.driver, 795 } 796 /* could list the /proc/iomem resources */ 797 }; 798 799 static inline void omap_mpuio_init(struct gpio_bank *bank) 800 { 801 static bool registered; 802 803 platform_set_drvdata(&omap_mpuio_device, bank); 804 if (!registered) { 805 (void)platform_device_register(&omap_mpuio_device); 806 registered = true; 807 } 808 } 809 810 /*---------------------------------------------------------------------*/ 811 812 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 813 { 814 struct gpio_bank *bank = gpiochip_get_data(chip); 815 unsigned long flags; 816 817 pm_runtime_get_sync(chip->parent); 818 819 raw_spin_lock_irqsave(&bank->lock, flags); 820 omap_enable_gpio_module(bank, offset); 821 bank->mod_usage |= BIT(offset); 822 raw_spin_unlock_irqrestore(&bank->lock, flags); 823 824 return 0; 825 } 826 827 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 828 { 829 struct gpio_bank *bank = gpiochip_get_data(chip); 830 unsigned long flags; 831 832 raw_spin_lock_irqsave(&bank->lock, flags); 833 bank->mod_usage &= ~(BIT(offset)); 834 if (!LINE_USED(bank->irq_usage, offset)) { 835 omap_set_gpio_direction(bank, offset, 1); 836 omap_clear_gpio_debounce(bank, offset); 837 } 838 omap_disable_gpio_module(bank, offset); 839 raw_spin_unlock_irqrestore(&bank->lock, flags); 840 841 pm_runtime_put(chip->parent); 842 } 843 844 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 845 { 846 struct gpio_bank *bank = gpiochip_get_data(chip); 847 848 if (readl_relaxed(bank->base + bank->regs->direction) & BIT(offset)) 849 return GPIO_LINE_DIRECTION_IN; 850 851 return GPIO_LINE_DIRECTION_OUT; 852 } 853 854 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) 855 { 856 struct gpio_bank *bank; 857 unsigned long flags; 858 859 bank = gpiochip_get_data(chip); 860 raw_spin_lock_irqsave(&bank->lock, flags); 861 omap_set_gpio_direction(bank, offset, 1); 862 raw_spin_unlock_irqrestore(&bank->lock, flags); 863 return 0; 864 } 865 866 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 867 { 868 struct gpio_bank *bank = gpiochip_get_data(chip); 869 void __iomem *reg; 870 871 if (omap_gpio_is_input(bank, offset)) 872 reg = bank->base + bank->regs->datain; 873 else 874 reg = bank->base + bank->regs->dataout; 875 876 return (readl_relaxed(reg) & BIT(offset)) != 0; 877 } 878 879 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) 880 { 881 struct gpio_bank *bank; 882 unsigned long flags; 883 884 bank = gpiochip_get_data(chip); 885 raw_spin_lock_irqsave(&bank->lock, flags); 886 bank->set_dataout(bank, offset, value); 887 omap_set_gpio_direction(bank, offset, 0); 888 raw_spin_unlock_irqrestore(&bank->lock, flags); 889 return 0; 890 } 891 892 static int omap_gpio_get_multiple(struct gpio_chip *chip, unsigned long *mask, 893 unsigned long *bits) 894 { 895 struct gpio_bank *bank = gpiochip_get_data(chip); 896 void __iomem *base = bank->base; 897 u32 direction, m, val = 0; 898 899 direction = readl_relaxed(base + bank->regs->direction); 900 901 m = direction & *mask; 902 if (m) 903 val |= readl_relaxed(base + bank->regs->datain) & m; 904 905 m = ~direction & *mask; 906 if (m) 907 val |= readl_relaxed(base + bank->regs->dataout) & m; 908 909 *bits = val; 910 911 return 0; 912 } 913 914 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, 915 unsigned debounce) 916 { 917 struct gpio_bank *bank; 918 unsigned long flags; 919 int ret; 920 921 bank = gpiochip_get_data(chip); 922 923 raw_spin_lock_irqsave(&bank->lock, flags); 924 ret = omap2_set_gpio_debounce(bank, offset, debounce); 925 raw_spin_unlock_irqrestore(&bank->lock, flags); 926 927 if (ret) 928 dev_info(chip->parent, 929 "Could not set line %u debounce to %u microseconds (%d)", 930 offset, debounce, ret); 931 932 return ret; 933 } 934 935 static int omap_gpio_set_config(struct gpio_chip *chip, unsigned offset, 936 unsigned long config) 937 { 938 u32 debounce; 939 int ret = -ENOTSUPP; 940 941 switch (pinconf_to_config_param(config)) { 942 case PIN_CONFIG_BIAS_DISABLE: 943 case PIN_CONFIG_BIAS_PULL_UP: 944 case PIN_CONFIG_BIAS_PULL_DOWN: 945 ret = gpiochip_generic_config(chip, offset, config); 946 break; 947 case PIN_CONFIG_INPUT_DEBOUNCE: 948 debounce = pinconf_to_config_argument(config); 949 ret = omap_gpio_debounce(chip, offset, debounce); 950 break; 951 default: 952 break; 953 } 954 955 return ret; 956 } 957 958 static int omap_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) 959 { 960 struct gpio_bank *bank; 961 unsigned long flags; 962 963 bank = gpiochip_get_data(chip); 964 raw_spin_lock_irqsave(&bank->lock, flags); 965 bank->set_dataout(bank, offset, value); 966 raw_spin_unlock_irqrestore(&bank->lock, flags); 967 968 return 0; 969 } 970 971 static int omap_gpio_set_multiple(struct gpio_chip *chip, unsigned long *mask, 972 unsigned long *bits) 973 { 974 struct gpio_bank *bank = gpiochip_get_data(chip); 975 void __iomem *reg = bank->base + bank->regs->dataout; 976 unsigned long flags; 977 u32 l; 978 979 raw_spin_lock_irqsave(&bank->lock, flags); 980 l = (readl_relaxed(reg) & ~*mask) | (*bits & *mask); 981 writel_relaxed(l, reg); 982 bank->context.dataout = l; 983 raw_spin_unlock_irqrestore(&bank->lock, flags); 984 985 return 0; 986 } 987 988 /*---------------------------------------------------------------------*/ 989 990 static void omap_gpio_show_rev(struct gpio_bank *bank) 991 { 992 static bool called; 993 u32 rev; 994 995 if (called || bank->regs->revision == USHRT_MAX) 996 return; 997 998 rev = readw_relaxed(bank->base + bank->regs->revision); 999 pr_info("OMAP GPIO hardware version %d.%d\n", 1000 (rev >> 4) & 0x0f, rev & 0x0f); 1001 1002 called = true; 1003 } 1004 1005 static void omap_gpio_mod_init(struct gpio_bank *bank) 1006 { 1007 void __iomem *base = bank->base; 1008 u32 l = 0xffffffff; 1009 1010 if (bank->width == 16) 1011 l = 0xffff; 1012 1013 if (bank->is_mpuio) { 1014 writel_relaxed(l, bank->base + bank->regs->irqenable); 1015 return; 1016 } 1017 1018 omap_gpio_rmw(base + bank->regs->irqenable, l, 1019 bank->regs->irqenable_inv); 1020 omap_gpio_rmw(base + bank->regs->irqstatus, l, 1021 !bank->regs->irqenable_inv); 1022 if (bank->regs->debounce_en) 1023 writel_relaxed(0, base + bank->regs->debounce_en); 1024 1025 /* Save OE default value (0xffffffff) in the context */ 1026 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); 1027 /* Initialize interface clk ungated, module enabled */ 1028 if (bank->regs->ctrl) 1029 writel_relaxed(0, base + bank->regs->ctrl); 1030 } 1031 1032 static int omap_gpio_chip_init(struct gpio_bank *bank, struct device *pm_dev) 1033 { 1034 struct gpio_irq_chip *irq; 1035 static int gpio; 1036 const char *label; 1037 int ret; 1038 1039 /* 1040 * REVISIT eventually switch from OMAP-specific gpio structs 1041 * over to the generic ones 1042 */ 1043 bank->chip.request = omap_gpio_request; 1044 bank->chip.free = omap_gpio_free; 1045 bank->chip.get_direction = omap_gpio_get_direction; 1046 bank->chip.direction_input = omap_gpio_input; 1047 bank->chip.get = omap_gpio_get; 1048 bank->chip.get_multiple = omap_gpio_get_multiple; 1049 bank->chip.direction_output = omap_gpio_output; 1050 bank->chip.set_config = omap_gpio_set_config; 1051 bank->chip.set = omap_gpio_set; 1052 bank->chip.set_multiple = omap_gpio_set_multiple; 1053 if (bank->is_mpuio) { 1054 bank->chip.label = "mpuio"; 1055 if (bank->regs->wkup_en) 1056 bank->chip.parent = &omap_mpuio_device.dev; 1057 } else { 1058 label = devm_kasprintf(bank->chip.parent, GFP_KERNEL, "gpio-%d-%d", 1059 gpio, gpio + bank->width - 1); 1060 if (!label) 1061 return -ENOMEM; 1062 bank->chip.label = label; 1063 } 1064 bank->chip.base = -1; 1065 bank->chip.ngpio = bank->width; 1066 1067 irq = &bank->chip.irq; 1068 /* MPUIO is a bit different, reading IRQ status clears it */ 1069 if (bank->is_mpuio && !bank->regs->wkup_en) 1070 gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip_nowake); 1071 else 1072 gpio_irq_chip_set_chip(irq, &omap_gpio_irq_chip); 1073 irq->handler = handle_bad_irq; 1074 irq->default_type = IRQ_TYPE_NONE; 1075 irq->num_parents = 1; 1076 irq->parents = &bank->irq; 1077 1078 ret = gpiochip_add_data(&bank->chip, bank); 1079 if (ret) 1080 return dev_err_probe(bank->chip.parent, ret, "Could not register gpio chip\n"); 1081 1082 irq_domain_set_pm_device(bank->chip.irq.domain, pm_dev); 1083 ret = devm_request_irq(bank->chip.parent, bank->irq, 1084 omap_gpio_irq_handler, 1085 0, dev_name(bank->chip.parent), bank); 1086 if (ret) 1087 gpiochip_remove(&bank->chip); 1088 1089 if (!bank->is_mpuio) 1090 gpio += bank->width; 1091 1092 return ret; 1093 } 1094 1095 static void omap_gpio_init_context(struct gpio_bank *p) 1096 { 1097 const struct omap_gpio_reg_offs *regs = p->regs; 1098 void __iomem *base = p->base; 1099 1100 p->context.sysconfig = readl_relaxed(base + regs->sysconfig); 1101 p->context.ctrl = readl_relaxed(base + regs->ctrl); 1102 p->context.oe = readl_relaxed(base + regs->direction); 1103 p->context.wake_en = readl_relaxed(base + regs->wkup_en); 1104 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); 1105 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); 1106 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); 1107 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); 1108 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); 1109 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); 1110 p->context.dataout = readl_relaxed(base + regs->dataout); 1111 1112 p->context_valid = true; 1113 } 1114 1115 static void omap_gpio_restore_context(struct gpio_bank *bank) 1116 { 1117 const struct omap_gpio_reg_offs *regs = bank->regs; 1118 void __iomem *base = bank->base; 1119 1120 writel_relaxed(bank->context.sysconfig, base + regs->sysconfig); 1121 writel_relaxed(bank->context.wake_en, base + regs->wkup_en); 1122 writel_relaxed(bank->context.ctrl, base + regs->ctrl); 1123 writel_relaxed(bank->context.leveldetect0, base + regs->leveldetect0); 1124 writel_relaxed(bank->context.leveldetect1, base + regs->leveldetect1); 1125 writel_relaxed(bank->context.risingdetect, base + regs->risingdetect); 1126 writel_relaxed(bank->context.fallingdetect, base + regs->fallingdetect); 1127 writel_relaxed(bank->context.dataout, base + regs->dataout); 1128 writel_relaxed(bank->context.oe, base + regs->direction); 1129 1130 if (bank->dbck_enable_mask) { 1131 writel_relaxed(bank->context.debounce, base + regs->debounce); 1132 writel_relaxed(bank->context.debounce_en, 1133 base + regs->debounce_en); 1134 } 1135 1136 writel_relaxed(bank->context.irqenable1, base + regs->irqenable); 1137 writel_relaxed(bank->context.irqenable2, base + regs->irqenable2); 1138 } 1139 1140 static void omap_gpio_idle(struct gpio_bank *bank, bool may_lose_context) 1141 { 1142 struct device *dev = bank->chip.parent; 1143 void __iomem *base = bank->base; 1144 u32 mask, nowake; 1145 1146 bank->saved_datain = readl_relaxed(base + bank->regs->datain); 1147 1148 /* Save syconfig, it's runtime value can be different from init value */ 1149 if (bank->loses_context) 1150 bank->context.sysconfig = readl_relaxed(base + bank->regs->sysconfig); 1151 1152 if (!bank->enabled_non_wakeup_gpios) 1153 goto update_gpio_context_count; 1154 1155 /* Check for pending EDGE_FALLING, ignore EDGE_BOTH */ 1156 mask = bank->enabled_non_wakeup_gpios & bank->context.fallingdetect; 1157 mask &= ~bank->context.risingdetect; 1158 bank->saved_datain |= mask; 1159 1160 /* Check for pending EDGE_RISING, ignore EDGE_BOTH */ 1161 mask = bank->enabled_non_wakeup_gpios & bank->context.risingdetect; 1162 mask &= ~bank->context.fallingdetect; 1163 bank->saved_datain &= ~mask; 1164 1165 if (!may_lose_context) 1166 goto update_gpio_context_count; 1167 1168 /* 1169 * If going to OFF, remove triggering for all wkup domain 1170 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1171 * generated. See OMAP2420 Errata item 1.101. 1172 */ 1173 if (!bank->loses_context && bank->enabled_non_wakeup_gpios) { 1174 nowake = bank->enabled_non_wakeup_gpios; 1175 omap_gpio_rmw(base + bank->regs->fallingdetect, nowake, ~nowake); 1176 omap_gpio_rmw(base + bank->regs->risingdetect, nowake, ~nowake); 1177 } 1178 1179 update_gpio_context_count: 1180 if (bank->get_context_loss_count) 1181 bank->context_loss_count = 1182 bank->get_context_loss_count(dev); 1183 1184 omap_gpio_dbck_disable(bank); 1185 } 1186 1187 static void omap_gpio_unidle(struct gpio_bank *bank) 1188 { 1189 struct device *dev = bank->chip.parent; 1190 u32 l = 0, gen, gen0, gen1; 1191 int c; 1192 1193 /* 1194 * On the first resume during the probe, the context has not 1195 * been initialised and so initialise it now. Also initialise 1196 * the context loss count. 1197 */ 1198 if (bank->loses_context && !bank->context_valid) { 1199 omap_gpio_init_context(bank); 1200 1201 if (bank->get_context_loss_count) 1202 bank->context_loss_count = 1203 bank->get_context_loss_count(dev); 1204 } 1205 1206 omap_gpio_dbck_enable(bank); 1207 1208 if (bank->loses_context) { 1209 if (!bank->get_context_loss_count) { 1210 omap_gpio_restore_context(bank); 1211 } else { 1212 c = bank->get_context_loss_count(dev); 1213 if (c != bank->context_loss_count) { 1214 omap_gpio_restore_context(bank); 1215 } else { 1216 return; 1217 } 1218 } 1219 } else { 1220 /* Restore changes done for OMAP2420 errata 1.101 */ 1221 writel_relaxed(bank->context.fallingdetect, 1222 bank->base + bank->regs->fallingdetect); 1223 writel_relaxed(bank->context.risingdetect, 1224 bank->base + bank->regs->risingdetect); 1225 } 1226 1227 l = readl_relaxed(bank->base + bank->regs->datain); 1228 1229 /* 1230 * Check if any of the non-wakeup interrupt GPIOs have changed 1231 * state. If so, generate an IRQ by software. This is 1232 * horribly racy, but it's the best we can do to work around 1233 * this silicon bug. 1234 */ 1235 l ^= bank->saved_datain; 1236 l &= bank->enabled_non_wakeup_gpios; 1237 1238 /* 1239 * No need to generate IRQs for the rising edge for gpio IRQs 1240 * configured with falling edge only; and vice versa. 1241 */ 1242 gen0 = l & bank->context.fallingdetect; 1243 gen0 &= bank->saved_datain; 1244 1245 gen1 = l & bank->context.risingdetect; 1246 gen1 &= ~(bank->saved_datain); 1247 1248 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1249 gen = l & (~(bank->context.fallingdetect) & 1250 ~(bank->context.risingdetect)); 1251 /* Consider all GPIO IRQs needed to be updated */ 1252 gen |= gen0 | gen1; 1253 1254 if (gen) { 1255 u32 old0, old1; 1256 1257 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); 1258 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); 1259 1260 if (!bank->regs->irqstatus_raw0) { 1261 writel_relaxed(old0 | gen, bank->base + 1262 bank->regs->leveldetect0); 1263 writel_relaxed(old1 | gen, bank->base + 1264 bank->regs->leveldetect1); 1265 } 1266 1267 if (bank->regs->irqstatus_raw0) { 1268 writel_relaxed(old0 | l, bank->base + 1269 bank->regs->leveldetect0); 1270 writel_relaxed(old1 | l, bank->base + 1271 bank->regs->leveldetect1); 1272 } 1273 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); 1274 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); 1275 } 1276 } 1277 1278 static int gpio_omap_cpu_notifier(struct notifier_block *nb, 1279 unsigned long cmd, void *v) 1280 { 1281 struct gpio_bank *bank; 1282 unsigned long flags; 1283 int ret = NOTIFY_OK; 1284 u32 isr, mask; 1285 1286 bank = container_of(nb, struct gpio_bank, nb); 1287 1288 raw_spin_lock_irqsave(&bank->lock, flags); 1289 if (bank->is_suspended) 1290 goto out_unlock; 1291 1292 switch (cmd) { 1293 case CPU_CLUSTER_PM_ENTER: 1294 mask = omap_get_gpio_irqbank_mask(bank); 1295 isr = readl_relaxed(bank->base + bank->regs->irqstatus) & mask; 1296 if (isr) { 1297 ret = NOTIFY_BAD; 1298 break; 1299 } 1300 omap_gpio_idle(bank, true); 1301 break; 1302 case CPU_CLUSTER_PM_ENTER_FAILED: 1303 case CPU_CLUSTER_PM_EXIT: 1304 omap_gpio_unidle(bank); 1305 break; 1306 } 1307 1308 out_unlock: 1309 raw_spin_unlock_irqrestore(&bank->lock, flags); 1310 1311 return ret; 1312 } 1313 1314 static const struct omap_gpio_reg_offs omap2_gpio_regs = { 1315 .revision = OMAP24XX_GPIO_REVISION, 1316 .sysconfig = OMAP24XX_GPIO_SYSCONFIG, 1317 .direction = OMAP24XX_GPIO_OE, 1318 .datain = OMAP24XX_GPIO_DATAIN, 1319 .dataout = OMAP24XX_GPIO_DATAOUT, 1320 .set_dataout = OMAP24XX_GPIO_SETDATAOUT, 1321 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, 1322 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, 1323 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, 1324 .irqenable = OMAP24XX_GPIO_IRQENABLE1, 1325 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, 1326 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, 1327 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, 1328 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, 1329 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, 1330 .ctrl = OMAP24XX_GPIO_CTRL, 1331 .wkup_en = OMAP24XX_GPIO_WAKE_EN, 1332 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, 1333 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, 1334 .risingdetect = OMAP24XX_GPIO_RISINGDETECT, 1335 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, 1336 }; 1337 1338 static const struct omap_gpio_reg_offs omap4_gpio_regs = { 1339 .revision = OMAP4_GPIO_REVISION, 1340 .sysconfig = OMAP4_GPIO_SYSCONFIG, 1341 .direction = OMAP4_GPIO_OE, 1342 .datain = OMAP4_GPIO_DATAIN, 1343 .dataout = OMAP4_GPIO_DATAOUT, 1344 .set_dataout = OMAP4_GPIO_SETDATAOUT, 1345 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, 1346 .irqstatus = OMAP4_GPIO_IRQSTATUS0, 1347 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, 1348 .irqstatus_raw0 = OMAP4_GPIO_IRQSTATUSRAW0, 1349 .irqstatus_raw1 = OMAP4_GPIO_IRQSTATUSRAW1, 1350 .irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1351 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, 1352 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1353 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, 1354 .debounce = OMAP4_GPIO_DEBOUNCINGTIME, 1355 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, 1356 .ctrl = OMAP4_GPIO_CTRL, 1357 .wkup_en = OMAP4_GPIO_IRQWAKEN0, 1358 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, 1359 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, 1360 .risingdetect = OMAP4_GPIO_RISINGDETECT, 1361 .fallingdetect = OMAP4_GPIO_FALLINGDETECT, 1362 }; 1363 1364 static const struct omap_gpio_platform_data omap2_pdata = { 1365 .regs = &omap2_gpio_regs, 1366 .bank_width = 32, 1367 .dbck_flag = false, 1368 }; 1369 1370 static const struct omap_gpio_platform_data omap3_pdata = { 1371 .regs = &omap2_gpio_regs, 1372 .bank_width = 32, 1373 .dbck_flag = true, 1374 }; 1375 1376 static const struct omap_gpio_platform_data omap4_pdata = { 1377 .regs = &omap4_gpio_regs, 1378 .bank_width = 32, 1379 .dbck_flag = true, 1380 }; 1381 1382 static const struct of_device_id omap_gpio_match[] = { 1383 { 1384 .compatible = "ti,omap4-gpio", 1385 .data = &omap4_pdata, 1386 }, 1387 { 1388 .compatible = "ti,omap3-gpio", 1389 .data = &omap3_pdata, 1390 }, 1391 { 1392 .compatible = "ti,omap2-gpio", 1393 .data = &omap2_pdata, 1394 }, 1395 { }, 1396 }; 1397 MODULE_DEVICE_TABLE(of, omap_gpio_match); 1398 1399 static int omap_gpio_probe(struct platform_device *pdev) 1400 { 1401 struct device *dev = &pdev->dev; 1402 struct device_node *node = dev->of_node; 1403 const struct omap_gpio_platform_data *pdata; 1404 struct gpio_bank *bank; 1405 int ret; 1406 1407 pdata = device_get_match_data(dev); 1408 1409 pdata = pdata ?: dev_get_platdata(dev); 1410 if (!pdata) 1411 return -EINVAL; 1412 1413 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL); 1414 if (!bank) 1415 return -ENOMEM; 1416 1417 bank->dev = dev; 1418 1419 bank->irq = platform_get_irq(pdev, 0); 1420 if (bank->irq < 0) 1421 return bank->irq; 1422 1423 bank->chip.parent = dev; 1424 bank->chip.owner = THIS_MODULE; 1425 bank->dbck_flag = pdata->dbck_flag; 1426 bank->stride = pdata->bank_stride; 1427 bank->width = pdata->bank_width; 1428 bank->is_mpuio = pdata->is_mpuio; 1429 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; 1430 bank->regs = pdata->regs; 1431 1432 if (node) { 1433 if (!of_property_read_bool(node, "ti,gpio-always-on")) 1434 bank->loses_context = true; 1435 } else { 1436 bank->loses_context = pdata->loses_context; 1437 1438 if (bank->loses_context) 1439 bank->get_context_loss_count = 1440 pdata->get_context_loss_count; 1441 } 1442 1443 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1444 bank->set_dataout = omap_set_gpio_dataout_reg; 1445 else 1446 bank->set_dataout = omap_set_gpio_dataout_mask; 1447 1448 raw_spin_lock_init(&bank->lock); 1449 raw_spin_lock_init(&bank->wa_lock); 1450 1451 /* Static mapping, never released */ 1452 bank->base = devm_platform_ioremap_resource(pdev, 0); 1453 if (IS_ERR(bank->base)) { 1454 return PTR_ERR(bank->base); 1455 } 1456 1457 if (bank->dbck_flag) { 1458 bank->dbck = devm_clk_get(dev, "dbclk"); 1459 if (IS_ERR(bank->dbck)) { 1460 dev_err(dev, 1461 "Could not get gpio dbck. Disable debounce\n"); 1462 bank->dbck_flag = false; 1463 } else { 1464 clk_prepare(bank->dbck); 1465 } 1466 } 1467 1468 platform_set_drvdata(pdev, bank); 1469 1470 pm_runtime_enable(dev); 1471 pm_runtime_get_sync(dev); 1472 1473 if (bank->is_mpuio) 1474 omap_mpuio_init(bank); 1475 1476 omap_gpio_mod_init(bank); 1477 1478 ret = omap_gpio_chip_init(bank, dev); 1479 if (ret) { 1480 pm_runtime_put_sync(dev); 1481 pm_runtime_disable(dev); 1482 if (bank->dbck_flag) 1483 clk_unprepare(bank->dbck); 1484 return ret; 1485 } 1486 1487 omap_gpio_show_rev(bank); 1488 1489 bank->nb.notifier_call = gpio_omap_cpu_notifier; 1490 cpu_pm_register_notifier(&bank->nb); 1491 1492 pm_runtime_put(dev); 1493 1494 return 0; 1495 } 1496 1497 static void omap_gpio_remove(struct platform_device *pdev) 1498 { 1499 struct gpio_bank *bank = platform_get_drvdata(pdev); 1500 1501 cpu_pm_unregister_notifier(&bank->nb); 1502 gpiochip_remove(&bank->chip); 1503 pm_runtime_disable(&pdev->dev); 1504 if (bank->dbck_flag) 1505 clk_unprepare(bank->dbck); 1506 } 1507 1508 static int omap_gpio_runtime_suspend(struct device *dev) 1509 { 1510 struct gpio_bank *bank = dev_get_drvdata(dev); 1511 unsigned long flags; 1512 1513 raw_spin_lock_irqsave(&bank->lock, flags); 1514 omap_gpio_idle(bank, true); 1515 bank->is_suspended = true; 1516 raw_spin_unlock_irqrestore(&bank->lock, flags); 1517 1518 return 0; 1519 } 1520 1521 static int omap_gpio_runtime_resume(struct device *dev) 1522 { 1523 struct gpio_bank *bank = dev_get_drvdata(dev); 1524 unsigned long flags; 1525 1526 raw_spin_lock_irqsave(&bank->lock, flags); 1527 omap_gpio_unidle(bank); 1528 bank->is_suspended = false; 1529 raw_spin_unlock_irqrestore(&bank->lock, flags); 1530 1531 return 0; 1532 } 1533 1534 static int omap_gpio_suspend(struct device *dev) 1535 { 1536 struct gpio_bank *bank = dev_get_drvdata(dev); 1537 1538 if (bank->is_suspended) 1539 return 0; 1540 1541 bank->needs_resume = 1; 1542 1543 return omap_gpio_runtime_suspend(dev); 1544 } 1545 1546 static int omap_gpio_resume(struct device *dev) 1547 { 1548 struct gpio_bank *bank = dev_get_drvdata(dev); 1549 1550 if (!bank->needs_resume) 1551 return 0; 1552 1553 bank->needs_resume = 0; 1554 1555 return omap_gpio_runtime_resume(dev); 1556 } 1557 1558 static const struct dev_pm_ops gpio_pm_ops = { 1559 RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, NULL) 1560 LATE_SYSTEM_SLEEP_PM_OPS(omap_gpio_suspend, omap_gpio_resume) 1561 }; 1562 1563 static struct platform_driver omap_gpio_driver = { 1564 .probe = omap_gpio_probe, 1565 .remove = omap_gpio_remove, 1566 .driver = { 1567 .name = "omap_gpio", 1568 .pm = pm_ptr(&gpio_pm_ops), 1569 .of_match_table = omap_gpio_match, 1570 }, 1571 }; 1572 1573 /* 1574 * gpio driver register needs to be done before 1575 * machine_init functions access gpio APIs. 1576 * Hence omap_gpio_drv_reg() is a postcore_initcall. 1577 */ 1578 static int __init omap_gpio_drv_reg(void) 1579 { 1580 int ret; 1581 1582 ret = platform_driver_register(&omap_mpuio_driver); 1583 if (ret) 1584 return ret; 1585 1586 ret = platform_driver_register(&omap_gpio_driver); 1587 if (ret) 1588 platform_driver_unregister(&omap_mpuio_driver); 1589 1590 return ret; 1591 } 1592 postcore_initcall(omap_gpio_drv_reg); 1593 1594 static void __exit omap_gpio_exit(void) 1595 { 1596 platform_driver_unregister(&omap_gpio_driver); 1597 platform_driver_unregister(&omap_mpuio_driver); 1598 } 1599 module_exit(omap_gpio_exit); 1600 1601 MODULE_DESCRIPTION("omap gpio driver"); 1602 MODULE_ALIAS("platform:gpio-omap"); 1603 MODULE_LICENSE("GPL v2"); 1604