xref: /linux/drivers/gpio/gpio-omap.c (revision 08ec212c0f92cbf30e3ecc7349f18151714041d6) 
1 /*
2  * Support functions for OMAP GPIO
3  *
4  * Copyright (C) 2003-2005 Nokia Corporation
5  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
6  *
7  * Copyright (C) 2009 Texas Instruments
8  * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
9  *
10  * This program is free software; you can redistribute it and/or modify
11  * it under the terms of the GNU General Public License version 2 as
12  * published by the Free Software Foundation.
13  */
14 
15 #include <linux/init.h>
16 #include <linux/module.h>
17 #include <linux/interrupt.h>
18 #include <linux/syscore_ops.h>
19 #include <linux/err.h>
20 #include <linux/clk.h>
21 #include <linux/io.h>
22 #include <linux/device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/pm.h>
25 #include <linux/of.h>
26 #include <linux/of_device.h>
27 #include <linux/irqdomain.h>
28 #include <linux/gpio.h>
29 #include <linux/platform_data/gpio-omap.h>
30 
31 #include <asm/mach/irq.h>
32 
33 #define OFF_MODE	1
34 
35 static LIST_HEAD(omap_gpio_list);
36 
37 struct gpio_regs {
38 	u32 irqenable1;
39 	u32 irqenable2;
40 	u32 wake_en;
41 	u32 ctrl;
42 	u32 oe;
43 	u32 leveldetect0;
44 	u32 leveldetect1;
45 	u32 risingdetect;
46 	u32 fallingdetect;
47 	u32 dataout;
48 	u32 debounce;
49 	u32 debounce_en;
50 };
51 
52 struct gpio_bank {
53 	struct list_head node;
54 	void __iomem *base;
55 	u16 irq;
56 	int irq_base;
57 	struct irq_domain *domain;
58 	u32 non_wakeup_gpios;
59 	u32 enabled_non_wakeup_gpios;
60 	struct gpio_regs context;
61 	u32 saved_datain;
62 	u32 level_mask;
63 	u32 toggle_mask;
64 	spinlock_t lock;
65 	struct gpio_chip chip;
66 	struct clk *dbck;
67 	u32 mod_usage;
68 	u32 dbck_enable_mask;
69 	bool dbck_enabled;
70 	struct device *dev;
71 	bool is_mpuio;
72 	bool dbck_flag;
73 	bool loses_context;
74 	int stride;
75 	u32 width;
76 	int context_loss_count;
77 	int power_mode;
78 	bool workaround_enabled;
79 
80 	void (*set_dataout)(struct gpio_bank *bank, int gpio, int enable);
81 	int (*get_context_loss_count)(struct device *dev);
82 
83 	struct omap_gpio_reg_offs *regs;
84 };
85 
86 #define GPIO_INDEX(bank, gpio) (gpio % bank->width)
87 #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio))
88 #define GPIO_MOD_CTRL_BIT	BIT(0)
89 
90 static int irq_to_gpio(struct gpio_bank *bank, unsigned int gpio_irq)
91 {
92 	return gpio_irq - bank->irq_base + bank->chip.base;
93 }
94 
95 static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
96 {
97 	void __iomem *reg = bank->base;
98 	u32 l;
99 
100 	reg += bank->regs->direction;
101 	l = __raw_readl(reg);
102 	if (is_input)
103 		l |= 1 << gpio;
104 	else
105 		l &= ~(1 << gpio);
106 	__raw_writel(l, reg);
107 	bank->context.oe = l;
108 }
109 
110 
111 /* set data out value using dedicate set/clear register */
112 static void _set_gpio_dataout_reg(struct gpio_bank *bank, int gpio, int enable)
113 {
114 	void __iomem *reg = bank->base;
115 	u32 l = GPIO_BIT(bank, gpio);
116 
117 	if (enable) {
118 		reg += bank->regs->set_dataout;
119 		bank->context.dataout |= l;
120 	} else {
121 		reg += bank->regs->clr_dataout;
122 		bank->context.dataout &= ~l;
123 	}
124 
125 	__raw_writel(l, reg);
126 }
127 
128 /* set data out value using mask register */
129 static void _set_gpio_dataout_mask(struct gpio_bank *bank, int gpio, int enable)
130 {
131 	void __iomem *reg = bank->base + bank->regs->dataout;
132 	u32 gpio_bit = GPIO_BIT(bank, gpio);
133 	u32 l;
134 
135 	l = __raw_readl(reg);
136 	if (enable)
137 		l |= gpio_bit;
138 	else
139 		l &= ~gpio_bit;
140 	__raw_writel(l, reg);
141 	bank->context.dataout = l;
142 }
143 
144 static int _get_gpio_datain(struct gpio_bank *bank, int offset)
145 {
146 	void __iomem *reg = bank->base + bank->regs->datain;
147 
148 	return (__raw_readl(reg) & (1 << offset)) != 0;
149 }
150 
151 static int _get_gpio_dataout(struct gpio_bank *bank, int offset)
152 {
153 	void __iomem *reg = bank->base + bank->regs->dataout;
154 
155 	return (__raw_readl(reg) & (1 << offset)) != 0;
156 }
157 
158 static inline void _gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set)
159 {
160 	int l = __raw_readl(base + reg);
161 
162 	if (set)
163 		l |= mask;
164 	else
165 		l &= ~mask;
166 
167 	__raw_writel(l, base + reg);
168 }
169 
170 static inline void _gpio_dbck_enable(struct gpio_bank *bank)
171 {
172 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {
173 		clk_enable(bank->dbck);
174 		bank->dbck_enabled = true;
175 
176 		__raw_writel(bank->dbck_enable_mask,
177 			     bank->base + bank->regs->debounce_en);
178 	}
179 }
180 
181 static inline void _gpio_dbck_disable(struct gpio_bank *bank)
182 {
183 	if (bank->dbck_enable_mask && bank->dbck_enabled) {
184 		/*
185 		 * Disable debounce before cutting it's clock. If debounce is
186 		 * enabled but the clock is not, GPIO module seems to be unable
187 		 * to detect events and generate interrupts at least on OMAP3.
188 		 */
189 		__raw_writel(0, bank->base + bank->regs->debounce_en);
190 
191 		clk_disable(bank->dbck);
192 		bank->dbck_enabled = false;
193 	}
194 }
195 
196 /**
197  * _set_gpio_debounce - low level gpio debounce time
198  * @bank: the gpio bank we're acting upon
199  * @gpio: the gpio number on this @gpio
200  * @debounce: debounce time to use
201  *
202  * OMAP's debounce time is in 31us steps so we need
203  * to convert and round up to the closest unit.
204  */
205 static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
206 		unsigned debounce)
207 {
208 	void __iomem		*reg;
209 	u32			val;
210 	u32			l;
211 
212 	if (!bank->dbck_flag)
213 		return;
214 
215 	if (debounce < 32)
216 		debounce = 0x01;
217 	else if (debounce > 7936)
218 		debounce = 0xff;
219 	else
220 		debounce = (debounce / 0x1f) - 1;
221 
222 	l = GPIO_BIT(bank, gpio);
223 
224 	clk_enable(bank->dbck);
225 	reg = bank->base + bank->regs->debounce;
226 	__raw_writel(debounce, reg);
227 
228 	reg = bank->base + bank->regs->debounce_en;
229 	val = __raw_readl(reg);
230 
231 	if (debounce)
232 		val |= l;
233 	else
234 		val &= ~l;
235 	bank->dbck_enable_mask = val;
236 
237 	__raw_writel(val, reg);
238 	clk_disable(bank->dbck);
239 	/*
240 	 * Enable debounce clock per module.
241 	 * This call is mandatory because in omap_gpio_request() when
242 	 * *_runtime_get_sync() is called,  _gpio_dbck_enable() within
243 	 * runtime callbck fails to turn on dbck because dbck_enable_mask
244 	 * used within _gpio_dbck_enable() is still not initialized at
245 	 * that point. Therefore we have to enable dbck here.
246 	 */
247 	_gpio_dbck_enable(bank);
248 	if (bank->dbck_enable_mask) {
249 		bank->context.debounce = debounce;
250 		bank->context.debounce_en = val;
251 	}
252 }
253 
254 static inline void set_gpio_trigger(struct gpio_bank *bank, int gpio,
255 						unsigned trigger)
256 {
257 	void __iomem *base = bank->base;
258 	u32 gpio_bit = 1 << gpio;
259 
260 	_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,
261 		  trigger & IRQ_TYPE_LEVEL_LOW);
262 	_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,
263 		  trigger & IRQ_TYPE_LEVEL_HIGH);
264 	_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,
265 		  trigger & IRQ_TYPE_EDGE_RISING);
266 	_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,
267 		  trigger & IRQ_TYPE_EDGE_FALLING);
268 
269 	bank->context.leveldetect0 =
270 			__raw_readl(bank->base + bank->regs->leveldetect0);
271 	bank->context.leveldetect1 =
272 			__raw_readl(bank->base + bank->regs->leveldetect1);
273 	bank->context.risingdetect =
274 			__raw_readl(bank->base + bank->regs->risingdetect);
275 	bank->context.fallingdetect =
276 			__raw_readl(bank->base + bank->regs->fallingdetect);
277 
278 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
279 		_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);
280 		bank->context.wake_en =
281 			__raw_readl(bank->base + bank->regs->wkup_en);
282 	}
283 
284 	/* This part needs to be executed always for OMAP{34xx, 44xx} */
285 	if (!bank->regs->irqctrl) {
286 		/* On omap24xx proceed only when valid GPIO bit is set */
287 		if (bank->non_wakeup_gpios) {
288 			if (!(bank->non_wakeup_gpios & gpio_bit))
289 				goto exit;
290 		}
291 
292 		/*
293 		 * Log the edge gpio and manually trigger the IRQ
294 		 * after resume if the input level changes
295 		 * to avoid irq lost during PER RET/OFF mode
296 		 * Applies for omap2 non-wakeup gpio and all omap3 gpios
297 		 */
298 		if (trigger & IRQ_TYPE_EDGE_BOTH)
299 			bank->enabled_non_wakeup_gpios |= gpio_bit;
300 		else
301 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;
302 	}
303 
304 exit:
305 	bank->level_mask =
306 		__raw_readl(bank->base + bank->regs->leveldetect0) |
307 		__raw_readl(bank->base + bank->regs->leveldetect1);
308 }
309 
310 #ifdef CONFIG_ARCH_OMAP1
311 /*
312  * This only applies to chips that can't do both rising and falling edge
313  * detection at once.  For all other chips, this function is a noop.
314  */
315 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
316 {
317 	void __iomem *reg = bank->base;
318 	u32 l = 0;
319 
320 	if (!bank->regs->irqctrl)
321 		return;
322 
323 	reg += bank->regs->irqctrl;
324 
325 	l = __raw_readl(reg);
326 	if ((l >> gpio) & 1)
327 		l &= ~(1 << gpio);
328 	else
329 		l |= 1 << gpio;
330 
331 	__raw_writel(l, reg);
332 }
333 #else
334 static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}
335 #endif
336 
337 static int _set_gpio_triggering(struct gpio_bank *bank, int gpio,
338 							unsigned trigger)
339 {
340 	void __iomem *reg = bank->base;
341 	void __iomem *base = bank->base;
342 	u32 l = 0;
343 
344 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {
345 		set_gpio_trigger(bank, gpio, trigger);
346 	} else if (bank->regs->irqctrl) {
347 		reg += bank->regs->irqctrl;
348 
349 		l = __raw_readl(reg);
350 		if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
351 			bank->toggle_mask |= 1 << gpio;
352 		if (trigger & IRQ_TYPE_EDGE_RISING)
353 			l |= 1 << gpio;
354 		else if (trigger & IRQ_TYPE_EDGE_FALLING)
355 			l &= ~(1 << gpio);
356 		else
357 			return -EINVAL;
358 
359 		__raw_writel(l, reg);
360 	} else if (bank->regs->edgectrl1) {
361 		if (gpio & 0x08)
362 			reg += bank->regs->edgectrl2;
363 		else
364 			reg += bank->regs->edgectrl1;
365 
366 		gpio &= 0x07;
367 		l = __raw_readl(reg);
368 		l &= ~(3 << (gpio << 1));
369 		if (trigger & IRQ_TYPE_EDGE_RISING)
370 			l |= 2 << (gpio << 1);
371 		if (trigger & IRQ_TYPE_EDGE_FALLING)
372 			l |= 1 << (gpio << 1);
373 
374 		/* Enable wake-up during idle for dynamic tick */
375 		_gpio_rmw(base, bank->regs->wkup_en, 1 << gpio, trigger);
376 		bank->context.wake_en =
377 			__raw_readl(bank->base + bank->regs->wkup_en);
378 		__raw_writel(l, reg);
379 	}
380 	return 0;
381 }
382 
383 static int gpio_irq_type(struct irq_data *d, unsigned type)
384 {
385 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
386 	unsigned gpio = 0;
387 	int retval;
388 	unsigned long flags;
389 
390 #ifdef CONFIG_ARCH_OMAP1
391 	if (d->irq > IH_MPUIO_BASE)
392 		gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
393 #endif
394 
395 	if (!gpio)
396 		gpio = irq_to_gpio(bank, d->irq);
397 
398 	if (type & ~IRQ_TYPE_SENSE_MASK)
399 		return -EINVAL;
400 
401 	if (!bank->regs->leveldetect0 &&
402 		(type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
403 		return -EINVAL;
404 
405 	spin_lock_irqsave(&bank->lock, flags);
406 	retval = _set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), type);
407 	spin_unlock_irqrestore(&bank->lock, flags);
408 
409 	if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
410 		__irq_set_handler_locked(d->irq, handle_level_irq);
411 	else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
412 		__irq_set_handler_locked(d->irq, handle_edge_irq);
413 
414 	return retval;
415 }
416 
417 static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
418 {
419 	void __iomem *reg = bank->base;
420 
421 	reg += bank->regs->irqstatus;
422 	__raw_writel(gpio_mask, reg);
423 
424 	/* Workaround for clearing DSP GPIO interrupts to allow retention */
425 	if (bank->regs->irqstatus2) {
426 		reg = bank->base + bank->regs->irqstatus2;
427 		__raw_writel(gpio_mask, reg);
428 	}
429 
430 	/* Flush posted write for the irq status to avoid spurious interrupts */
431 	__raw_readl(reg);
432 }
433 
434 static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
435 {
436 	_clear_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
437 }
438 
439 static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
440 {
441 	void __iomem *reg = bank->base;
442 	u32 l;
443 	u32 mask = (1 << bank->width) - 1;
444 
445 	reg += bank->regs->irqenable;
446 	l = __raw_readl(reg);
447 	if (bank->regs->irqenable_inv)
448 		l = ~l;
449 	l &= mask;
450 	return l;
451 }
452 
453 static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
454 {
455 	void __iomem *reg = bank->base;
456 	u32 l;
457 
458 	if (bank->regs->set_irqenable) {
459 		reg += bank->regs->set_irqenable;
460 		l = gpio_mask;
461 		bank->context.irqenable1 |= gpio_mask;
462 	} else {
463 		reg += bank->regs->irqenable;
464 		l = __raw_readl(reg);
465 		if (bank->regs->irqenable_inv)
466 			l &= ~gpio_mask;
467 		else
468 			l |= gpio_mask;
469 		bank->context.irqenable1 = l;
470 	}
471 
472 	__raw_writel(l, reg);
473 }
474 
475 static void _disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
476 {
477 	void __iomem *reg = bank->base;
478 	u32 l;
479 
480 	if (bank->regs->clr_irqenable) {
481 		reg += bank->regs->clr_irqenable;
482 		l = gpio_mask;
483 		bank->context.irqenable1 &= ~gpio_mask;
484 	} else {
485 		reg += bank->regs->irqenable;
486 		l = __raw_readl(reg);
487 		if (bank->regs->irqenable_inv)
488 			l |= gpio_mask;
489 		else
490 			l &= ~gpio_mask;
491 		bank->context.irqenable1 = l;
492 	}
493 
494 	__raw_writel(l, reg);
495 }
496 
497 static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
498 {
499 	if (enable)
500 		_enable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
501 	else
502 		_disable_gpio_irqbank(bank, GPIO_BIT(bank, gpio));
503 }
504 
505 /*
506  * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
507  * 1510 does not seem to have a wake-up register. If JTAG is connected
508  * to the target, system will wake up always on GPIO events. While
509  * system is running all registered GPIO interrupts need to have wake-up
510  * enabled. When system is suspended, only selected GPIO interrupts need
511  * to have wake-up enabled.
512  */
513 static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
514 {
515 	u32 gpio_bit = GPIO_BIT(bank, gpio);
516 	unsigned long flags;
517 
518 	if (bank->non_wakeup_gpios & gpio_bit) {
519 		dev_err(bank->dev,
520 			"Unable to modify wakeup on non-wakeup GPIO%d\n", gpio);
521 		return -EINVAL;
522 	}
523 
524 	spin_lock_irqsave(&bank->lock, flags);
525 	if (enable)
526 		bank->context.wake_en |= gpio_bit;
527 	else
528 		bank->context.wake_en &= ~gpio_bit;
529 
530 	__raw_writel(bank->context.wake_en, bank->base + bank->regs->wkup_en);
531 	spin_unlock_irqrestore(&bank->lock, flags);
532 
533 	return 0;
534 }
535 
536 static void _reset_gpio(struct gpio_bank *bank, int gpio)
537 {
538 	_set_gpio_direction(bank, GPIO_INDEX(bank, gpio), 1);
539 	_set_gpio_irqenable(bank, gpio, 0);
540 	_clear_gpio_irqstatus(bank, gpio);
541 	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
542 }
543 
544 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
545 static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
546 {
547 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
548 	unsigned int gpio = irq_to_gpio(bank, d->irq);
549 
550 	return _set_gpio_wakeup(bank, gpio, enable);
551 }
552 
553 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
554 {
555 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
556 	unsigned long flags;
557 
558 	/*
559 	 * If this is the first gpio_request for the bank,
560 	 * enable the bank module.
561 	 */
562 	if (!bank->mod_usage)
563 		pm_runtime_get_sync(bank->dev);
564 
565 	spin_lock_irqsave(&bank->lock, flags);
566 	/* Set trigger to none. You need to enable the desired trigger with
567 	 * request_irq() or set_irq_type().
568 	 */
569 	_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
570 
571 	if (bank->regs->pinctrl) {
572 		void __iomem *reg = bank->base + bank->regs->pinctrl;
573 
574 		/* Claim the pin for MPU */
575 		__raw_writel(__raw_readl(reg) | (1 << offset), reg);
576 	}
577 
578 	if (bank->regs->ctrl && !bank->mod_usage) {
579 		void __iomem *reg = bank->base + bank->regs->ctrl;
580 		u32 ctrl;
581 
582 		ctrl = __raw_readl(reg);
583 		/* Module is enabled, clocks are not gated */
584 		ctrl &= ~GPIO_MOD_CTRL_BIT;
585 		__raw_writel(ctrl, reg);
586 		bank->context.ctrl = ctrl;
587 	}
588 
589 	bank->mod_usage |= 1 << offset;
590 
591 	spin_unlock_irqrestore(&bank->lock, flags);
592 
593 	return 0;
594 }
595 
596 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
597 {
598 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
599 	void __iomem *base = bank->base;
600 	unsigned long flags;
601 
602 	spin_lock_irqsave(&bank->lock, flags);
603 
604 	if (bank->regs->wkup_en) {
605 		/* Disable wake-up during idle for dynamic tick */
606 		_gpio_rmw(base, bank->regs->wkup_en, 1 << offset, 0);
607 		bank->context.wake_en =
608 			__raw_readl(bank->base + bank->regs->wkup_en);
609 	}
610 
611 	bank->mod_usage &= ~(1 << offset);
612 
613 	if (bank->regs->ctrl && !bank->mod_usage) {
614 		void __iomem *reg = bank->base + bank->regs->ctrl;
615 		u32 ctrl;
616 
617 		ctrl = __raw_readl(reg);
618 		/* Module is disabled, clocks are gated */
619 		ctrl |= GPIO_MOD_CTRL_BIT;
620 		__raw_writel(ctrl, reg);
621 		bank->context.ctrl = ctrl;
622 	}
623 
624 	_reset_gpio(bank, bank->chip.base + offset);
625 	spin_unlock_irqrestore(&bank->lock, flags);
626 
627 	/*
628 	 * If this is the last gpio to be freed in the bank,
629 	 * disable the bank module.
630 	 */
631 	if (!bank->mod_usage)
632 		pm_runtime_put(bank->dev);
633 }
634 
635 /*
636  * We need to unmask the GPIO bank interrupt as soon as possible to
637  * avoid missing GPIO interrupts for other lines in the bank.
638  * Then we need to mask-read-clear-unmask the triggered GPIO lines
639  * in the bank to avoid missing nested interrupts for a GPIO line.
640  * If we wait to unmask individual GPIO lines in the bank after the
641  * line's interrupt handler has been run, we may miss some nested
642  * interrupts.
643  */
644 static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
645 {
646 	void __iomem *isr_reg = NULL;
647 	u32 isr;
648 	unsigned int gpio_irq, gpio_index;
649 	struct gpio_bank *bank;
650 	int unmasked = 0;
651 	struct irq_chip *chip = irq_desc_get_chip(desc);
652 
653 	chained_irq_enter(chip, desc);
654 
655 	bank = irq_get_handler_data(irq);
656 	isr_reg = bank->base + bank->regs->irqstatus;
657 	pm_runtime_get_sync(bank->dev);
658 
659 	if (WARN_ON(!isr_reg))
660 		goto exit;
661 
662 	while(1) {
663 		u32 isr_saved, level_mask = 0;
664 		u32 enabled;
665 
666 		enabled = _get_gpio_irqbank_mask(bank);
667 		isr_saved = isr = __raw_readl(isr_reg) & enabled;
668 
669 		if (bank->level_mask)
670 			level_mask = bank->level_mask & enabled;
671 
672 		/* clear edge sensitive interrupts before handler(s) are
673 		called so that we don't miss any interrupt occurred while
674 		executing them */
675 		_disable_gpio_irqbank(bank, isr_saved & ~level_mask);
676 		_clear_gpio_irqbank(bank, isr_saved & ~level_mask);
677 		_enable_gpio_irqbank(bank, isr_saved & ~level_mask);
678 
679 		/* if there is only edge sensitive GPIO pin interrupts
680 		configured, we could unmask GPIO bank interrupt immediately */
681 		if (!level_mask && !unmasked) {
682 			unmasked = 1;
683 			chained_irq_exit(chip, desc);
684 		}
685 
686 		if (!isr)
687 			break;
688 
689 		gpio_irq = bank->irq_base;
690 		for (; isr != 0; isr >>= 1, gpio_irq++) {
691 			int gpio = irq_to_gpio(bank, gpio_irq);
692 
693 			if (!(isr & 1))
694 				continue;
695 
696 			gpio_index = GPIO_INDEX(bank, gpio);
697 
698 			/*
699 			 * Some chips can't respond to both rising and falling
700 			 * at the same time.  If this irq was requested with
701 			 * both flags, we need to flip the ICR data for the IRQ
702 			 * to respond to the IRQ for the opposite direction.
703 			 * This will be indicated in the bank toggle_mask.
704 			 */
705 			if (bank->toggle_mask & (1 << gpio_index))
706 				_toggle_gpio_edge_triggering(bank, gpio_index);
707 
708 			generic_handle_irq(gpio_irq);
709 		}
710 	}
711 	/* if bank has any level sensitive GPIO pin interrupt
712 	configured, we must unmask the bank interrupt only after
713 	handler(s) are executed in order to avoid spurious bank
714 	interrupt */
715 exit:
716 	if (!unmasked)
717 		chained_irq_exit(chip, desc);
718 	pm_runtime_put(bank->dev);
719 }
720 
721 static void gpio_irq_shutdown(struct irq_data *d)
722 {
723 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
724 	unsigned int gpio = irq_to_gpio(bank, d->irq);
725 	unsigned long flags;
726 
727 	spin_lock_irqsave(&bank->lock, flags);
728 	_reset_gpio(bank, gpio);
729 	spin_unlock_irqrestore(&bank->lock, flags);
730 }
731 
732 static void gpio_ack_irq(struct irq_data *d)
733 {
734 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
735 	unsigned int gpio = irq_to_gpio(bank, d->irq);
736 
737 	_clear_gpio_irqstatus(bank, gpio);
738 }
739 
740 static void gpio_mask_irq(struct irq_data *d)
741 {
742 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
743 	unsigned int gpio = irq_to_gpio(bank, d->irq);
744 	unsigned long flags;
745 
746 	spin_lock_irqsave(&bank->lock, flags);
747 	_set_gpio_irqenable(bank, gpio, 0);
748 	_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), IRQ_TYPE_NONE);
749 	spin_unlock_irqrestore(&bank->lock, flags);
750 }
751 
752 static void gpio_unmask_irq(struct irq_data *d)
753 {
754 	struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
755 	unsigned int gpio = irq_to_gpio(bank, d->irq);
756 	unsigned int irq_mask = GPIO_BIT(bank, gpio);
757 	u32 trigger = irqd_get_trigger_type(d);
758 	unsigned long flags;
759 
760 	spin_lock_irqsave(&bank->lock, flags);
761 	if (trigger)
762 		_set_gpio_triggering(bank, GPIO_INDEX(bank, gpio), trigger);
763 
764 	/* For level-triggered GPIOs, the clearing must be done after
765 	 * the HW source is cleared, thus after the handler has run */
766 	if (bank->level_mask & irq_mask) {
767 		_set_gpio_irqenable(bank, gpio, 0);
768 		_clear_gpio_irqstatus(bank, gpio);
769 	}
770 
771 	_set_gpio_irqenable(bank, gpio, 1);
772 	spin_unlock_irqrestore(&bank->lock, flags);
773 }
774 
775 static struct irq_chip gpio_irq_chip = {
776 	.name		= "GPIO",
777 	.irq_shutdown	= gpio_irq_shutdown,
778 	.irq_ack	= gpio_ack_irq,
779 	.irq_mask	= gpio_mask_irq,
780 	.irq_unmask	= gpio_unmask_irq,
781 	.irq_set_type	= gpio_irq_type,
782 	.irq_set_wake	= gpio_wake_enable,
783 };
784 
785 /*---------------------------------------------------------------------*/
786 
787 static int omap_mpuio_suspend_noirq(struct device *dev)
788 {
789 	struct platform_device *pdev = to_platform_device(dev);
790 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
791 	void __iomem		*mask_reg = bank->base +
792 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
793 	unsigned long		flags;
794 
795 	spin_lock_irqsave(&bank->lock, flags);
796 	__raw_writel(0xffff & ~bank->context.wake_en, mask_reg);
797 	spin_unlock_irqrestore(&bank->lock, flags);
798 
799 	return 0;
800 }
801 
802 static int omap_mpuio_resume_noirq(struct device *dev)
803 {
804 	struct platform_device *pdev = to_platform_device(dev);
805 	struct gpio_bank	*bank = platform_get_drvdata(pdev);
806 	void __iomem		*mask_reg = bank->base +
807 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;
808 	unsigned long		flags;
809 
810 	spin_lock_irqsave(&bank->lock, flags);
811 	__raw_writel(bank->context.wake_en, mask_reg);
812 	spin_unlock_irqrestore(&bank->lock, flags);
813 
814 	return 0;
815 }
816 
817 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
818 	.suspend_noirq = omap_mpuio_suspend_noirq,
819 	.resume_noirq = omap_mpuio_resume_noirq,
820 };
821 
822 /* use platform_driver for this. */
823 static struct platform_driver omap_mpuio_driver = {
824 	.driver		= {
825 		.name	= "mpuio",
826 		.pm	= &omap_mpuio_dev_pm_ops,
827 	},
828 };
829 
830 static struct platform_device omap_mpuio_device = {
831 	.name		= "mpuio",
832 	.id		= -1,
833 	.dev = {
834 		.driver = &omap_mpuio_driver.driver,
835 	}
836 	/* could list the /proc/iomem resources */
837 };
838 
839 static inline void mpuio_init(struct gpio_bank *bank)
840 {
841 	platform_set_drvdata(&omap_mpuio_device, bank);
842 
843 	if (platform_driver_register(&omap_mpuio_driver) == 0)
844 		(void) platform_device_register(&omap_mpuio_device);
845 }
846 
847 /*---------------------------------------------------------------------*/
848 
849 static int gpio_input(struct gpio_chip *chip, unsigned offset)
850 {
851 	struct gpio_bank *bank;
852 	unsigned long flags;
853 
854 	bank = container_of(chip, struct gpio_bank, chip);
855 	spin_lock_irqsave(&bank->lock, flags);
856 	_set_gpio_direction(bank, offset, 1);
857 	spin_unlock_irqrestore(&bank->lock, flags);
858 	return 0;
859 }
860 
861 static int gpio_is_input(struct gpio_bank *bank, int mask)
862 {
863 	void __iomem *reg = bank->base + bank->regs->direction;
864 
865 	return __raw_readl(reg) & mask;
866 }
867 
868 static int gpio_get(struct gpio_chip *chip, unsigned offset)
869 {
870 	struct gpio_bank *bank;
871 	u32 mask;
872 
873 	bank = container_of(chip, struct gpio_bank, chip);
874 	mask = (1 << offset);
875 
876 	if (gpio_is_input(bank, mask))
877 		return _get_gpio_datain(bank, offset);
878 	else
879 		return _get_gpio_dataout(bank, offset);
880 }
881 
882 static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
883 {
884 	struct gpio_bank *bank;
885 	unsigned long flags;
886 
887 	bank = container_of(chip, struct gpio_bank, chip);
888 	spin_lock_irqsave(&bank->lock, flags);
889 	bank->set_dataout(bank, offset, value);
890 	_set_gpio_direction(bank, offset, 0);
891 	spin_unlock_irqrestore(&bank->lock, flags);
892 	return 0;
893 }
894 
895 static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
896 		unsigned debounce)
897 {
898 	struct gpio_bank *bank;
899 	unsigned long flags;
900 
901 	bank = container_of(chip, struct gpio_bank, chip);
902 
903 	spin_lock_irqsave(&bank->lock, flags);
904 	_set_gpio_debounce(bank, offset, debounce);
905 	spin_unlock_irqrestore(&bank->lock, flags);
906 
907 	return 0;
908 }
909 
910 static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
911 {
912 	struct gpio_bank *bank;
913 	unsigned long flags;
914 
915 	bank = container_of(chip, struct gpio_bank, chip);
916 	spin_lock_irqsave(&bank->lock, flags);
917 	bank->set_dataout(bank, offset, value);
918 	spin_unlock_irqrestore(&bank->lock, flags);
919 }
920 
921 static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
922 {
923 	struct gpio_bank *bank;
924 
925 	bank = container_of(chip, struct gpio_bank, chip);
926 	return bank->irq_base + offset;
927 }
928 
929 /*---------------------------------------------------------------------*/
930 
931 static void __init omap_gpio_show_rev(struct gpio_bank *bank)
932 {
933 	static bool called;
934 	u32 rev;
935 
936 	if (called || bank->regs->revision == USHRT_MAX)
937 		return;
938 
939 	rev = __raw_readw(bank->base + bank->regs->revision);
940 	pr_info("OMAP GPIO hardware version %d.%d\n",
941 		(rev >> 4) & 0x0f, rev & 0x0f);
942 
943 	called = true;
944 }
945 
946 /* This lock class tells lockdep that GPIO irqs are in a different
947  * category than their parents, so it won't report false recursion.
948  */
949 static struct lock_class_key gpio_lock_class;
950 
951 static void omap_gpio_mod_init(struct gpio_bank *bank)
952 {
953 	void __iomem *base = bank->base;
954 	u32 l = 0xffffffff;
955 
956 	if (bank->width == 16)
957 		l = 0xffff;
958 
959 	if (bank->is_mpuio) {
960 		__raw_writel(l, bank->base + bank->regs->irqenable);
961 		return;
962 	}
963 
964 	_gpio_rmw(base, bank->regs->irqenable, l, bank->regs->irqenable_inv);
965 	_gpio_rmw(base, bank->regs->irqstatus, l, !bank->regs->irqenable_inv);
966 	if (bank->regs->debounce_en)
967 		__raw_writel(0, base + bank->regs->debounce_en);
968 
969 	/* Save OE default value (0xffffffff) in the context */
970 	bank->context.oe = __raw_readl(bank->base + bank->regs->direction);
971 	 /* Initialize interface clk ungated, module enabled */
972 	if (bank->regs->ctrl)
973 		__raw_writel(0, base + bank->regs->ctrl);
974 
975 	bank->dbck = clk_get(bank->dev, "dbclk");
976 	if (IS_ERR(bank->dbck))
977 		dev_err(bank->dev, "Could not get gpio dbck\n");
978 }
979 
980 static __devinit void
981 omap_mpuio_alloc_gc(struct gpio_bank *bank, unsigned int irq_start,
982 		    unsigned int num)
983 {
984 	struct irq_chip_generic *gc;
985 	struct irq_chip_type *ct;
986 
987 	gc = irq_alloc_generic_chip("MPUIO", 1, irq_start, bank->base,
988 				    handle_simple_irq);
989 	if (!gc) {
990 		dev_err(bank->dev, "Memory alloc failed for gc\n");
991 		return;
992 	}
993 
994 	ct = gc->chip_types;
995 
996 	/* NOTE: No ack required, reading IRQ status clears it. */
997 	ct->chip.irq_mask = irq_gc_mask_set_bit;
998 	ct->chip.irq_unmask = irq_gc_mask_clr_bit;
999 	ct->chip.irq_set_type = gpio_irq_type;
1000 
1001 	if (bank->regs->wkup_en)
1002 		ct->chip.irq_set_wake = gpio_wake_enable,
1003 
1004 	ct->regs.mask = OMAP_MPUIO_GPIO_INT / bank->stride;
1005 	irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
1006 			       IRQ_NOREQUEST | IRQ_NOPROBE, 0);
1007 }
1008 
1009 static void __devinit omap_gpio_chip_init(struct gpio_bank *bank)
1010 {
1011 	int j;
1012 	static int gpio;
1013 
1014 	/*
1015 	 * REVISIT eventually switch from OMAP-specific gpio structs
1016 	 * over to the generic ones
1017 	 */
1018 	bank->chip.request = omap_gpio_request;
1019 	bank->chip.free = omap_gpio_free;
1020 	bank->chip.direction_input = gpio_input;
1021 	bank->chip.get = gpio_get;
1022 	bank->chip.direction_output = gpio_output;
1023 	bank->chip.set_debounce = gpio_debounce;
1024 	bank->chip.set = gpio_set;
1025 	bank->chip.to_irq = gpio_2irq;
1026 	if (bank->is_mpuio) {
1027 		bank->chip.label = "mpuio";
1028 		if (bank->regs->wkup_en)
1029 			bank->chip.dev = &omap_mpuio_device.dev;
1030 		bank->chip.base = OMAP_MPUIO(0);
1031 	} else {
1032 		bank->chip.label = "gpio";
1033 		bank->chip.base = gpio;
1034 		gpio += bank->width;
1035 	}
1036 	bank->chip.ngpio = bank->width;
1037 
1038 	gpiochip_add(&bank->chip);
1039 
1040 	for (j = bank->irq_base; j < bank->irq_base + bank->width; j++) {
1041 		irq_set_lockdep_class(j, &gpio_lock_class);
1042 		irq_set_chip_data(j, bank);
1043 		if (bank->is_mpuio) {
1044 			omap_mpuio_alloc_gc(bank, j, bank->width);
1045 		} else {
1046 			irq_set_chip(j, &gpio_irq_chip);
1047 			irq_set_handler(j, handle_simple_irq);
1048 			set_irq_flags(j, IRQF_VALID);
1049 		}
1050 	}
1051 	irq_set_chained_handler(bank->irq, gpio_irq_handler);
1052 	irq_set_handler_data(bank->irq, bank);
1053 }
1054 
1055 static const struct of_device_id omap_gpio_match[];
1056 
1057 static int __devinit omap_gpio_probe(struct platform_device *pdev)
1058 {
1059 	struct device *dev = &pdev->dev;
1060 	struct device_node *node = dev->of_node;
1061 	const struct of_device_id *match;
1062 	const struct omap_gpio_platform_data *pdata;
1063 	struct resource *res;
1064 	struct gpio_bank *bank;
1065 	int ret = 0;
1066 
1067 	match = of_match_device(of_match_ptr(omap_gpio_match), dev);
1068 
1069 	pdata = match ? match->data : dev->platform_data;
1070 	if (!pdata)
1071 		return -EINVAL;
1072 
1073 	bank = devm_kzalloc(&pdev->dev, sizeof(struct gpio_bank), GFP_KERNEL);
1074 	if (!bank) {
1075 		dev_err(dev, "Memory alloc failed\n");
1076 		return -ENOMEM;
1077 	}
1078 
1079 	res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1080 	if (unlikely(!res)) {
1081 		dev_err(dev, "Invalid IRQ resource\n");
1082 		return -ENODEV;
1083 	}
1084 
1085 	bank->irq = res->start;
1086 	bank->dev = dev;
1087 	bank->dbck_flag = pdata->dbck_flag;
1088 	bank->stride = pdata->bank_stride;
1089 	bank->width = pdata->bank_width;
1090 	bank->is_mpuio = pdata->is_mpuio;
1091 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;
1092 	bank->loses_context = pdata->loses_context;
1093 	bank->regs = pdata->regs;
1094 #ifdef CONFIG_OF_GPIO
1095 	bank->chip.of_node = of_node_get(node);
1096 #endif
1097 
1098 	bank->irq_base = irq_alloc_descs(-1, 0, bank->width, 0);
1099 	if (bank->irq_base < 0) {
1100 		dev_err(dev, "Couldn't allocate IRQ numbers\n");
1101 		return -ENODEV;
1102 	}
1103 
1104 	bank->domain = irq_domain_add_legacy(node, bank->width, bank->irq_base,
1105 					     0, &irq_domain_simple_ops, NULL);
1106 
1107 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1108 		bank->set_dataout = _set_gpio_dataout_reg;
1109 	else
1110 		bank->set_dataout = _set_gpio_dataout_mask;
1111 
1112 	spin_lock_init(&bank->lock);
1113 
1114 	/* Static mapping, never released */
1115 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1116 	if (unlikely(!res)) {
1117 		dev_err(dev, "Invalid mem resource\n");
1118 		return -ENODEV;
1119 	}
1120 
1121 	if (!devm_request_mem_region(dev, res->start, resource_size(res),
1122 				     pdev->name)) {
1123 		dev_err(dev, "Region already claimed\n");
1124 		return -EBUSY;
1125 	}
1126 
1127 	bank->base = devm_ioremap(dev, res->start, resource_size(res));
1128 	if (!bank->base) {
1129 		dev_err(dev, "Could not ioremap\n");
1130 		return -ENOMEM;
1131 	}
1132 
1133 	platform_set_drvdata(pdev, bank);
1134 
1135 	pm_runtime_enable(bank->dev);
1136 	pm_runtime_irq_safe(bank->dev);
1137 	pm_runtime_get_sync(bank->dev);
1138 
1139 	if (bank->is_mpuio)
1140 		mpuio_init(bank);
1141 
1142 	omap_gpio_mod_init(bank);
1143 	omap_gpio_chip_init(bank);
1144 	omap_gpio_show_rev(bank);
1145 
1146 	if (bank->loses_context)
1147 		bank->get_context_loss_count = pdata->get_context_loss_count;
1148 
1149 	pm_runtime_put(bank->dev);
1150 
1151 	list_add_tail(&bank->node, &omap_gpio_list);
1152 
1153 	return ret;
1154 }
1155 
1156 #ifdef CONFIG_ARCH_OMAP2PLUS
1157 
1158 #if defined(CONFIG_PM_RUNTIME)
1159 static void omap_gpio_restore_context(struct gpio_bank *bank);
1160 
1161 static int omap_gpio_runtime_suspend(struct device *dev)
1162 {
1163 	struct platform_device *pdev = to_platform_device(dev);
1164 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1165 	u32 l1 = 0, l2 = 0;
1166 	unsigned long flags;
1167 	u32 wake_low, wake_hi;
1168 
1169 	spin_lock_irqsave(&bank->lock, flags);
1170 
1171 	/*
1172 	 * Only edges can generate a wakeup event to the PRCM.
1173 	 *
1174 	 * Therefore, ensure any wake-up capable GPIOs have
1175 	 * edge-detection enabled before going idle to ensure a wakeup
1176 	 * to the PRCM is generated on a GPIO transition. (c.f. 34xx
1177 	 * NDA TRM 25.5.3.1)
1178 	 *
1179 	 * The normal values will be restored upon ->runtime_resume()
1180 	 * by writing back the values saved in bank->context.
1181 	 */
1182 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;
1183 	if (wake_low)
1184 		__raw_writel(wake_low | bank->context.fallingdetect,
1185 			     bank->base + bank->regs->fallingdetect);
1186 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;
1187 	if (wake_hi)
1188 		__raw_writel(wake_hi | bank->context.risingdetect,
1189 			     bank->base + bank->regs->risingdetect);
1190 
1191 	if (!bank->enabled_non_wakeup_gpios)
1192 		goto update_gpio_context_count;
1193 
1194 	if (bank->power_mode != OFF_MODE) {
1195 		bank->power_mode = 0;
1196 		goto update_gpio_context_count;
1197 	}
1198 	/*
1199 	 * If going to OFF, remove triggering for all
1200 	 * non-wakeup GPIOs.  Otherwise spurious IRQs will be
1201 	 * generated.  See OMAP2420 Errata item 1.101.
1202 	 */
1203 	bank->saved_datain = __raw_readl(bank->base +
1204 						bank->regs->datain);
1205 	l1 = bank->context.fallingdetect;
1206 	l2 = bank->context.risingdetect;
1207 
1208 	l1 &= ~bank->enabled_non_wakeup_gpios;
1209 	l2 &= ~bank->enabled_non_wakeup_gpios;
1210 
1211 	__raw_writel(l1, bank->base + bank->regs->fallingdetect);
1212 	__raw_writel(l2, bank->base + bank->regs->risingdetect);
1213 
1214 	bank->workaround_enabled = true;
1215 
1216 update_gpio_context_count:
1217 	if (bank->get_context_loss_count)
1218 		bank->context_loss_count =
1219 				bank->get_context_loss_count(bank->dev);
1220 
1221 	_gpio_dbck_disable(bank);
1222 	spin_unlock_irqrestore(&bank->lock, flags);
1223 
1224 	return 0;
1225 }
1226 
1227 static int omap_gpio_runtime_resume(struct device *dev)
1228 {
1229 	struct platform_device *pdev = to_platform_device(dev);
1230 	struct gpio_bank *bank = platform_get_drvdata(pdev);
1231 	int context_lost_cnt_after;
1232 	u32 l = 0, gen, gen0, gen1;
1233 	unsigned long flags;
1234 
1235 	spin_lock_irqsave(&bank->lock, flags);
1236 	_gpio_dbck_enable(bank);
1237 
1238 	/*
1239 	 * In ->runtime_suspend(), level-triggered, wakeup-enabled
1240 	 * GPIOs were set to edge trigger also in order to be able to
1241 	 * generate a PRCM wakeup.  Here we restore the
1242 	 * pre-runtime_suspend() values for edge triggering.
1243 	 */
1244 	__raw_writel(bank->context.fallingdetect,
1245 		     bank->base + bank->regs->fallingdetect);
1246 	__raw_writel(bank->context.risingdetect,
1247 		     bank->base + bank->regs->risingdetect);
1248 
1249 	if (bank->get_context_loss_count) {
1250 		context_lost_cnt_after =
1251 			bank->get_context_loss_count(bank->dev);
1252 		if (context_lost_cnt_after != bank->context_loss_count) {
1253 			omap_gpio_restore_context(bank);
1254 		} else {
1255 			spin_unlock_irqrestore(&bank->lock, flags);
1256 			return 0;
1257 		}
1258 	}
1259 
1260 	if (!bank->workaround_enabled) {
1261 		spin_unlock_irqrestore(&bank->lock, flags);
1262 		return 0;
1263 	}
1264 
1265 	__raw_writel(bank->context.fallingdetect,
1266 			bank->base + bank->regs->fallingdetect);
1267 	__raw_writel(bank->context.risingdetect,
1268 			bank->base + bank->regs->risingdetect);
1269 	l = __raw_readl(bank->base + bank->regs->datain);
1270 
1271 	/*
1272 	 * Check if any of the non-wakeup interrupt GPIOs have changed
1273 	 * state.  If so, generate an IRQ by software.  This is
1274 	 * horribly racy, but it's the best we can do to work around
1275 	 * this silicon bug.
1276 	 */
1277 	l ^= bank->saved_datain;
1278 	l &= bank->enabled_non_wakeup_gpios;
1279 
1280 	/*
1281 	 * No need to generate IRQs for the rising edge for gpio IRQs
1282 	 * configured with falling edge only; and vice versa.
1283 	 */
1284 	gen0 = l & bank->context.fallingdetect;
1285 	gen0 &= bank->saved_datain;
1286 
1287 	gen1 = l & bank->context.risingdetect;
1288 	gen1 &= ~(bank->saved_datain);
1289 
1290 	/* FIXME: Consider GPIO IRQs with level detections properly! */
1291 	gen = l & (~(bank->context.fallingdetect) &
1292 					 ~(bank->context.risingdetect));
1293 	/* Consider all GPIO IRQs needed to be updated */
1294 	gen |= gen0 | gen1;
1295 
1296 	if (gen) {
1297 		u32 old0, old1;
1298 
1299 		old0 = __raw_readl(bank->base + bank->regs->leveldetect0);
1300 		old1 = __raw_readl(bank->base + bank->regs->leveldetect1);
1301 
1302 		if (!bank->regs->irqstatus_raw0) {
1303 			__raw_writel(old0 | gen, bank->base +
1304 						bank->regs->leveldetect0);
1305 			__raw_writel(old1 | gen, bank->base +
1306 						bank->regs->leveldetect1);
1307 		}
1308 
1309 		if (bank->regs->irqstatus_raw0) {
1310 			__raw_writel(old0 | l, bank->base +
1311 						bank->regs->leveldetect0);
1312 			__raw_writel(old1 | l, bank->base +
1313 						bank->regs->leveldetect1);
1314 		}
1315 		__raw_writel(old0, bank->base + bank->regs->leveldetect0);
1316 		__raw_writel(old1, bank->base + bank->regs->leveldetect1);
1317 	}
1318 
1319 	bank->workaround_enabled = false;
1320 	spin_unlock_irqrestore(&bank->lock, flags);
1321 
1322 	return 0;
1323 }
1324 #endif /* CONFIG_PM_RUNTIME */
1325 
1326 void omap2_gpio_prepare_for_idle(int pwr_mode)
1327 {
1328 	struct gpio_bank *bank;
1329 
1330 	list_for_each_entry(bank, &omap_gpio_list, node) {
1331 		if (!bank->mod_usage || !bank->loses_context)
1332 			continue;
1333 
1334 		bank->power_mode = pwr_mode;
1335 
1336 		pm_runtime_put_sync_suspend(bank->dev);
1337 	}
1338 }
1339 
1340 void omap2_gpio_resume_after_idle(void)
1341 {
1342 	struct gpio_bank *bank;
1343 
1344 	list_for_each_entry(bank, &omap_gpio_list, node) {
1345 		if (!bank->mod_usage || !bank->loses_context)
1346 			continue;
1347 
1348 		pm_runtime_get_sync(bank->dev);
1349 	}
1350 }
1351 
1352 #if defined(CONFIG_PM_RUNTIME)
1353 static void omap_gpio_restore_context(struct gpio_bank *bank)
1354 {
1355 	__raw_writel(bank->context.wake_en,
1356 				bank->base + bank->regs->wkup_en);
1357 	__raw_writel(bank->context.ctrl, bank->base + bank->regs->ctrl);
1358 	__raw_writel(bank->context.leveldetect0,
1359 				bank->base + bank->regs->leveldetect0);
1360 	__raw_writel(bank->context.leveldetect1,
1361 				bank->base + bank->regs->leveldetect1);
1362 	__raw_writel(bank->context.risingdetect,
1363 				bank->base + bank->regs->risingdetect);
1364 	__raw_writel(bank->context.fallingdetect,
1365 				bank->base + bank->regs->fallingdetect);
1366 	if (bank->regs->set_dataout && bank->regs->clr_dataout)
1367 		__raw_writel(bank->context.dataout,
1368 				bank->base + bank->regs->set_dataout);
1369 	else
1370 		__raw_writel(bank->context.dataout,
1371 				bank->base + bank->regs->dataout);
1372 	__raw_writel(bank->context.oe, bank->base + bank->regs->direction);
1373 
1374 	if (bank->dbck_enable_mask) {
1375 		__raw_writel(bank->context.debounce, bank->base +
1376 					bank->regs->debounce);
1377 		__raw_writel(bank->context.debounce_en,
1378 					bank->base + bank->regs->debounce_en);
1379 	}
1380 
1381 	__raw_writel(bank->context.irqenable1,
1382 				bank->base + bank->regs->irqenable);
1383 	__raw_writel(bank->context.irqenable2,
1384 				bank->base + bank->regs->irqenable2);
1385 }
1386 #endif /* CONFIG_PM_RUNTIME */
1387 #else
1388 #define omap_gpio_runtime_suspend NULL
1389 #define omap_gpio_runtime_resume NULL
1390 #endif
1391 
1392 static const struct dev_pm_ops gpio_pm_ops = {
1393 	SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume,
1394 									NULL)
1395 };
1396 
1397 #if defined(CONFIG_OF)
1398 static struct omap_gpio_reg_offs omap2_gpio_regs = {
1399 	.revision =		OMAP24XX_GPIO_REVISION,
1400 	.direction =		OMAP24XX_GPIO_OE,
1401 	.datain =		OMAP24XX_GPIO_DATAIN,
1402 	.dataout =		OMAP24XX_GPIO_DATAOUT,
1403 	.set_dataout =		OMAP24XX_GPIO_SETDATAOUT,
1404 	.clr_dataout =		OMAP24XX_GPIO_CLEARDATAOUT,
1405 	.irqstatus =		OMAP24XX_GPIO_IRQSTATUS1,
1406 	.irqstatus2 =		OMAP24XX_GPIO_IRQSTATUS2,
1407 	.irqenable =		OMAP24XX_GPIO_IRQENABLE1,
1408 	.irqenable2 =		OMAP24XX_GPIO_IRQENABLE2,
1409 	.set_irqenable =	OMAP24XX_GPIO_SETIRQENABLE1,
1410 	.clr_irqenable =	OMAP24XX_GPIO_CLEARIRQENABLE1,
1411 	.debounce =		OMAP24XX_GPIO_DEBOUNCE_VAL,
1412 	.debounce_en =		OMAP24XX_GPIO_DEBOUNCE_EN,
1413 	.ctrl =			OMAP24XX_GPIO_CTRL,
1414 	.wkup_en =		OMAP24XX_GPIO_WAKE_EN,
1415 	.leveldetect0 =		OMAP24XX_GPIO_LEVELDETECT0,
1416 	.leveldetect1 =		OMAP24XX_GPIO_LEVELDETECT1,
1417 	.risingdetect =		OMAP24XX_GPIO_RISINGDETECT,
1418 	.fallingdetect =	OMAP24XX_GPIO_FALLINGDETECT,
1419 };
1420 
1421 static struct omap_gpio_reg_offs omap4_gpio_regs = {
1422 	.revision =		OMAP4_GPIO_REVISION,
1423 	.direction =		OMAP4_GPIO_OE,
1424 	.datain =		OMAP4_GPIO_DATAIN,
1425 	.dataout =		OMAP4_GPIO_DATAOUT,
1426 	.set_dataout =		OMAP4_GPIO_SETDATAOUT,
1427 	.clr_dataout =		OMAP4_GPIO_CLEARDATAOUT,
1428 	.irqstatus =		OMAP4_GPIO_IRQSTATUS0,
1429 	.irqstatus2 =		OMAP4_GPIO_IRQSTATUS1,
1430 	.irqenable =		OMAP4_GPIO_IRQSTATUSSET0,
1431 	.irqenable2 =		OMAP4_GPIO_IRQSTATUSSET1,
1432 	.set_irqenable =	OMAP4_GPIO_IRQSTATUSSET0,
1433 	.clr_irqenable =	OMAP4_GPIO_IRQSTATUSCLR0,
1434 	.debounce =		OMAP4_GPIO_DEBOUNCINGTIME,
1435 	.debounce_en =		OMAP4_GPIO_DEBOUNCENABLE,
1436 	.ctrl =			OMAP4_GPIO_CTRL,
1437 	.wkup_en =		OMAP4_GPIO_IRQWAKEN0,
1438 	.leveldetect0 =		OMAP4_GPIO_LEVELDETECT0,
1439 	.leveldetect1 =		OMAP4_GPIO_LEVELDETECT1,
1440 	.risingdetect =		OMAP4_GPIO_RISINGDETECT,
1441 	.fallingdetect =	OMAP4_GPIO_FALLINGDETECT,
1442 };
1443 
1444 const static struct omap_gpio_platform_data omap2_pdata = {
1445 	.regs = &omap2_gpio_regs,
1446 	.bank_width = 32,
1447 	.dbck_flag = false,
1448 };
1449 
1450 const static struct omap_gpio_platform_data omap3_pdata = {
1451 	.regs = &omap2_gpio_regs,
1452 	.bank_width = 32,
1453 	.dbck_flag = true,
1454 };
1455 
1456 const static struct omap_gpio_platform_data omap4_pdata = {
1457 	.regs = &omap4_gpio_regs,
1458 	.bank_width = 32,
1459 	.dbck_flag = true,
1460 };
1461 
1462 static const struct of_device_id omap_gpio_match[] = {
1463 	{
1464 		.compatible = "ti,omap4-gpio",
1465 		.data = &omap4_pdata,
1466 	},
1467 	{
1468 		.compatible = "ti,omap3-gpio",
1469 		.data = &omap3_pdata,
1470 	},
1471 	{
1472 		.compatible = "ti,omap2-gpio",
1473 		.data = &omap2_pdata,
1474 	},
1475 	{ },
1476 };
1477 MODULE_DEVICE_TABLE(of, omap_gpio_match);
1478 #endif
1479 
1480 static struct platform_driver omap_gpio_driver = {
1481 	.probe		= omap_gpio_probe,
1482 	.driver		= {
1483 		.name	= "omap_gpio",
1484 		.pm	= &gpio_pm_ops,
1485 		.of_match_table = of_match_ptr(omap_gpio_match),
1486 	},
1487 };
1488 
1489 /*
1490  * gpio driver register needs to be done before
1491  * machine_init functions access gpio APIs.
1492  * Hence omap_gpio_drv_reg() is a postcore_initcall.
1493  */
1494 static int __init omap_gpio_drv_reg(void)
1495 {
1496 	return platform_driver_register(&omap_gpio_driver);
1497 }
1498 postcore_initcall(omap_gpio_drv_reg);
1499