1 /* 2 * Support functions for OMAP GPIO 3 * 4 * Copyright (C) 2003-2005 Nokia Corporation 5 * Written by Juha Yrjölä <juha.yrjola@nokia.com> 6 * 7 * Copyright (C) 2009 Texas Instruments 8 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com> 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License version 2 as 12 * published by the Free Software Foundation. 13 */ 14 15 #include <linux/init.h> 16 #include <linux/module.h> 17 #include <linux/interrupt.h> 18 #include <linux/syscore_ops.h> 19 #include <linux/err.h> 20 #include <linux/clk.h> 21 #include <linux/io.h> 22 #include <linux/device.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pm.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/gpio.h> 28 #include <linux/bitops.h> 29 #include <linux/platform_data/gpio-omap.h> 30 31 #define OFF_MODE 1 32 33 static LIST_HEAD(omap_gpio_list); 34 35 struct gpio_regs { 36 u32 irqenable1; 37 u32 irqenable2; 38 u32 wake_en; 39 u32 ctrl; 40 u32 oe; 41 u32 leveldetect0; 42 u32 leveldetect1; 43 u32 risingdetect; 44 u32 fallingdetect; 45 u32 dataout; 46 u32 debounce; 47 u32 debounce_en; 48 }; 49 50 struct gpio_bank { 51 struct list_head node; 52 void __iomem *base; 53 u16 irq; 54 u32 non_wakeup_gpios; 55 u32 enabled_non_wakeup_gpios; 56 struct gpio_regs context; 57 u32 saved_datain; 58 u32 level_mask; 59 u32 toggle_mask; 60 spinlock_t lock; 61 struct gpio_chip chip; 62 struct clk *dbck; 63 u32 mod_usage; 64 u32 irq_usage; 65 u32 dbck_enable_mask; 66 bool dbck_enabled; 67 struct device *dev; 68 bool is_mpuio; 69 bool dbck_flag; 70 bool loses_context; 71 bool context_valid; 72 int stride; 73 u32 width; 74 int context_loss_count; 75 int power_mode; 76 bool workaround_enabled; 77 78 void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable); 79 int (*get_context_loss_count)(struct device *dev); 80 81 struct omap_gpio_reg_offs *regs; 82 }; 83 84 #define GPIO_MOD_CTRL_BIT BIT(0) 85 86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage) 87 #define LINE_USED(line, offset) (line & (BIT(offset))) 88 89 static void omap_gpio_unmask_irq(struct irq_data *d); 90 91 static inline struct gpio_bank *omap_irq_data_get_bank(struct irq_data *d) 92 { 93 struct gpio_chip *chip = irq_data_get_irq_chip_data(d); 94 return container_of(chip, struct gpio_bank, chip); 95 } 96 97 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio, 98 int is_input) 99 { 100 void __iomem *reg = bank->base; 101 u32 l; 102 103 reg += bank->regs->direction; 104 l = readl_relaxed(reg); 105 if (is_input) 106 l |= BIT(gpio); 107 else 108 l &= ~(BIT(gpio)); 109 writel_relaxed(l, reg); 110 bank->context.oe = l; 111 } 112 113 114 /* set data out value using dedicate set/clear register */ 115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset, 116 int enable) 117 { 118 void __iomem *reg = bank->base; 119 u32 l = BIT(offset); 120 121 if (enable) { 122 reg += bank->regs->set_dataout; 123 bank->context.dataout |= l; 124 } else { 125 reg += bank->regs->clr_dataout; 126 bank->context.dataout &= ~l; 127 } 128 129 writel_relaxed(l, reg); 130 } 131 132 /* set data out value using mask register */ 133 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset, 134 int enable) 135 { 136 void __iomem *reg = bank->base + bank->regs->dataout; 137 u32 gpio_bit = BIT(offset); 138 u32 l; 139 140 l = readl_relaxed(reg); 141 if (enable) 142 l |= gpio_bit; 143 else 144 l &= ~gpio_bit; 145 writel_relaxed(l, reg); 146 bank->context.dataout = l; 147 } 148 149 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset) 150 { 151 void __iomem *reg = bank->base + bank->regs->datain; 152 153 return (readl_relaxed(reg) & (BIT(offset))) != 0; 154 } 155 156 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset) 157 { 158 void __iomem *reg = bank->base + bank->regs->dataout; 159 160 return (readl_relaxed(reg) & (BIT(offset))) != 0; 161 } 162 163 static inline void omap_gpio_rmw(void __iomem *base, u32 reg, u32 mask, bool set) 164 { 165 int l = readl_relaxed(base + reg); 166 167 if (set) 168 l |= mask; 169 else 170 l &= ~mask; 171 172 writel_relaxed(l, base + reg); 173 } 174 175 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank) 176 { 177 if (bank->dbck_enable_mask && !bank->dbck_enabled) { 178 clk_prepare_enable(bank->dbck); 179 bank->dbck_enabled = true; 180 181 writel_relaxed(bank->dbck_enable_mask, 182 bank->base + bank->regs->debounce_en); 183 } 184 } 185 186 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank) 187 { 188 if (bank->dbck_enable_mask && bank->dbck_enabled) { 189 /* 190 * Disable debounce before cutting it's clock. If debounce is 191 * enabled but the clock is not, GPIO module seems to be unable 192 * to detect events and generate interrupts at least on OMAP3. 193 */ 194 writel_relaxed(0, bank->base + bank->regs->debounce_en); 195 196 clk_disable_unprepare(bank->dbck); 197 bank->dbck_enabled = false; 198 } 199 } 200 201 /** 202 * omap2_set_gpio_debounce - low level gpio debounce time 203 * @bank: the gpio bank we're acting upon 204 * @offset: the gpio number on this @bank 205 * @debounce: debounce time to use 206 * 207 * OMAP's debounce time is in 31us steps so we need 208 * to convert and round up to the closest unit. 209 */ 210 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset, 211 unsigned debounce) 212 { 213 void __iomem *reg; 214 u32 val; 215 u32 l; 216 217 if (!bank->dbck_flag) 218 return; 219 220 if (debounce < 32) 221 debounce = 0x01; 222 else if (debounce > 7936) 223 debounce = 0xff; 224 else 225 debounce = (debounce / 0x1f) - 1; 226 227 l = BIT(offset); 228 229 clk_prepare_enable(bank->dbck); 230 reg = bank->base + bank->regs->debounce; 231 writel_relaxed(debounce, reg); 232 233 reg = bank->base + bank->regs->debounce_en; 234 val = readl_relaxed(reg); 235 236 if (debounce) 237 val |= l; 238 else 239 val &= ~l; 240 bank->dbck_enable_mask = val; 241 242 writel_relaxed(val, reg); 243 clk_disable_unprepare(bank->dbck); 244 /* 245 * Enable debounce clock per module. 246 * This call is mandatory because in omap_gpio_request() when 247 * *_runtime_get_sync() is called, _gpio_dbck_enable() within 248 * runtime callbck fails to turn on dbck because dbck_enable_mask 249 * used within _gpio_dbck_enable() is still not initialized at 250 * that point. Therefore we have to enable dbck here. 251 */ 252 omap_gpio_dbck_enable(bank); 253 if (bank->dbck_enable_mask) { 254 bank->context.debounce = debounce; 255 bank->context.debounce_en = val; 256 } 257 } 258 259 /** 260 * omap_clear_gpio_debounce - clear debounce settings for a gpio 261 * @bank: the gpio bank we're acting upon 262 * @offset: the gpio number on this @bank 263 * 264 * If a gpio is using debounce, then clear the debounce enable bit and if 265 * this is the only gpio in this bank using debounce, then clear the debounce 266 * time too. The debounce clock will also be disabled when calling this function 267 * if this is the only gpio in the bank using debounce. 268 */ 269 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset) 270 { 271 u32 gpio_bit = BIT(offset); 272 273 if (!bank->dbck_flag) 274 return; 275 276 if (!(bank->dbck_enable_mask & gpio_bit)) 277 return; 278 279 bank->dbck_enable_mask &= ~gpio_bit; 280 bank->context.debounce_en &= ~gpio_bit; 281 writel_relaxed(bank->context.debounce_en, 282 bank->base + bank->regs->debounce_en); 283 284 if (!bank->dbck_enable_mask) { 285 bank->context.debounce = 0; 286 writel_relaxed(bank->context.debounce, bank->base + 287 bank->regs->debounce); 288 clk_disable_unprepare(bank->dbck); 289 bank->dbck_enabled = false; 290 } 291 } 292 293 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio, 294 unsigned trigger) 295 { 296 void __iomem *base = bank->base; 297 u32 gpio_bit = BIT(gpio); 298 299 omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit, 300 trigger & IRQ_TYPE_LEVEL_LOW); 301 omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit, 302 trigger & IRQ_TYPE_LEVEL_HIGH); 303 omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit, 304 trigger & IRQ_TYPE_EDGE_RISING); 305 omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit, 306 trigger & IRQ_TYPE_EDGE_FALLING); 307 308 bank->context.leveldetect0 = 309 readl_relaxed(bank->base + bank->regs->leveldetect0); 310 bank->context.leveldetect1 = 311 readl_relaxed(bank->base + bank->regs->leveldetect1); 312 bank->context.risingdetect = 313 readl_relaxed(bank->base + bank->regs->risingdetect); 314 bank->context.fallingdetect = 315 readl_relaxed(bank->base + bank->regs->fallingdetect); 316 317 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) { 318 omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0); 319 bank->context.wake_en = 320 readl_relaxed(bank->base + bank->regs->wkup_en); 321 } 322 323 /* This part needs to be executed always for OMAP{34xx, 44xx} */ 324 if (!bank->regs->irqctrl) { 325 /* On omap24xx proceed only when valid GPIO bit is set */ 326 if (bank->non_wakeup_gpios) { 327 if (!(bank->non_wakeup_gpios & gpio_bit)) 328 goto exit; 329 } 330 331 /* 332 * Log the edge gpio and manually trigger the IRQ 333 * after resume if the input level changes 334 * to avoid irq lost during PER RET/OFF mode 335 * Applies for omap2 non-wakeup gpio and all omap3 gpios 336 */ 337 if (trigger & IRQ_TYPE_EDGE_BOTH) 338 bank->enabled_non_wakeup_gpios |= gpio_bit; 339 else 340 bank->enabled_non_wakeup_gpios &= ~gpio_bit; 341 } 342 343 exit: 344 bank->level_mask = 345 readl_relaxed(bank->base + bank->regs->leveldetect0) | 346 readl_relaxed(bank->base + bank->regs->leveldetect1); 347 } 348 349 #ifdef CONFIG_ARCH_OMAP1 350 /* 351 * This only applies to chips that can't do both rising and falling edge 352 * detection at once. For all other chips, this function is a noop. 353 */ 354 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) 355 { 356 void __iomem *reg = bank->base; 357 u32 l = 0; 358 359 if (!bank->regs->irqctrl) 360 return; 361 362 reg += bank->regs->irqctrl; 363 364 l = readl_relaxed(reg); 365 if ((l >> gpio) & 1) 366 l &= ~(BIT(gpio)); 367 else 368 l |= BIT(gpio); 369 370 writel_relaxed(l, reg); 371 } 372 #else 373 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {} 374 #endif 375 376 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio, 377 unsigned trigger) 378 { 379 void __iomem *reg = bank->base; 380 void __iomem *base = bank->base; 381 u32 l = 0; 382 383 if (bank->regs->leveldetect0 && bank->regs->wkup_en) { 384 omap_set_gpio_trigger(bank, gpio, trigger); 385 } else if (bank->regs->irqctrl) { 386 reg += bank->regs->irqctrl; 387 388 l = readl_relaxed(reg); 389 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) 390 bank->toggle_mask |= BIT(gpio); 391 if (trigger & IRQ_TYPE_EDGE_RISING) 392 l |= BIT(gpio); 393 else if (trigger & IRQ_TYPE_EDGE_FALLING) 394 l &= ~(BIT(gpio)); 395 else 396 return -EINVAL; 397 398 writel_relaxed(l, reg); 399 } else if (bank->regs->edgectrl1) { 400 if (gpio & 0x08) 401 reg += bank->regs->edgectrl2; 402 else 403 reg += bank->regs->edgectrl1; 404 405 gpio &= 0x07; 406 l = readl_relaxed(reg); 407 l &= ~(3 << (gpio << 1)); 408 if (trigger & IRQ_TYPE_EDGE_RISING) 409 l |= 2 << (gpio << 1); 410 if (trigger & IRQ_TYPE_EDGE_FALLING) 411 l |= BIT(gpio << 1); 412 413 /* Enable wake-up during idle for dynamic tick */ 414 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger); 415 bank->context.wake_en = 416 readl_relaxed(bank->base + bank->regs->wkup_en); 417 writel_relaxed(l, reg); 418 } 419 return 0; 420 } 421 422 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset) 423 { 424 if (bank->regs->pinctrl) { 425 void __iomem *reg = bank->base + bank->regs->pinctrl; 426 427 /* Claim the pin for MPU */ 428 writel_relaxed(readl_relaxed(reg) | (BIT(offset)), reg); 429 } 430 431 if (bank->regs->ctrl && !BANK_USED(bank)) { 432 void __iomem *reg = bank->base + bank->regs->ctrl; 433 u32 ctrl; 434 435 ctrl = readl_relaxed(reg); 436 /* Module is enabled, clocks are not gated */ 437 ctrl &= ~GPIO_MOD_CTRL_BIT; 438 writel_relaxed(ctrl, reg); 439 bank->context.ctrl = ctrl; 440 } 441 } 442 443 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset) 444 { 445 void __iomem *base = bank->base; 446 447 if (bank->regs->wkup_en && 448 !LINE_USED(bank->mod_usage, offset) && 449 !LINE_USED(bank->irq_usage, offset)) { 450 /* Disable wake-up during idle for dynamic tick */ 451 omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0); 452 bank->context.wake_en = 453 readl_relaxed(bank->base + bank->regs->wkup_en); 454 } 455 456 if (bank->regs->ctrl && !BANK_USED(bank)) { 457 void __iomem *reg = bank->base + bank->regs->ctrl; 458 u32 ctrl; 459 460 ctrl = readl_relaxed(reg); 461 /* Module is disabled, clocks are gated */ 462 ctrl |= GPIO_MOD_CTRL_BIT; 463 writel_relaxed(ctrl, reg); 464 bank->context.ctrl = ctrl; 465 } 466 } 467 468 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset) 469 { 470 void __iomem *reg = bank->base + bank->regs->direction; 471 472 return readl_relaxed(reg) & BIT(offset); 473 } 474 475 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset) 476 { 477 if (!LINE_USED(bank->mod_usage, offset)) { 478 omap_enable_gpio_module(bank, offset); 479 omap_set_gpio_direction(bank, offset, 1); 480 } 481 bank->irq_usage |= BIT(offset); 482 } 483 484 static int omap_gpio_irq_type(struct irq_data *d, unsigned type) 485 { 486 struct gpio_bank *bank = omap_irq_data_get_bank(d); 487 int retval; 488 unsigned long flags; 489 unsigned offset = d->hwirq; 490 491 if (type & ~IRQ_TYPE_SENSE_MASK) 492 return -EINVAL; 493 494 if (!bank->regs->leveldetect0 && 495 (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH))) 496 return -EINVAL; 497 498 if (!BANK_USED(bank)) 499 pm_runtime_get_sync(bank->dev); 500 501 spin_lock_irqsave(&bank->lock, flags); 502 retval = omap_set_gpio_triggering(bank, offset, type); 503 if (retval) 504 goto error; 505 omap_gpio_init_irq(bank, offset); 506 if (!omap_gpio_is_input(bank, offset)) { 507 spin_unlock_irqrestore(&bank->lock, flags); 508 retval = -EINVAL; 509 goto error; 510 } 511 spin_unlock_irqrestore(&bank->lock, flags); 512 513 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) 514 __irq_set_handler_locked(d->irq, handle_level_irq); 515 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) 516 __irq_set_handler_locked(d->irq, handle_edge_irq); 517 518 return 0; 519 520 error: 521 if (!BANK_USED(bank)) 522 pm_runtime_put(bank->dev); 523 return retval; 524 } 525 526 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 527 { 528 void __iomem *reg = bank->base; 529 530 reg += bank->regs->irqstatus; 531 writel_relaxed(gpio_mask, reg); 532 533 /* Workaround for clearing DSP GPIO interrupts to allow retention */ 534 if (bank->regs->irqstatus2) { 535 reg = bank->base + bank->regs->irqstatus2; 536 writel_relaxed(gpio_mask, reg); 537 } 538 539 /* Flush posted write for the irq status to avoid spurious interrupts */ 540 readl_relaxed(reg); 541 } 542 543 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank, 544 unsigned offset) 545 { 546 omap_clear_gpio_irqbank(bank, BIT(offset)); 547 } 548 549 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank) 550 { 551 void __iomem *reg = bank->base; 552 u32 l; 553 u32 mask = (BIT(bank->width)) - 1; 554 555 reg += bank->regs->irqenable; 556 l = readl_relaxed(reg); 557 if (bank->regs->irqenable_inv) 558 l = ~l; 559 l &= mask; 560 return l; 561 } 562 563 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 564 { 565 void __iomem *reg = bank->base; 566 u32 l; 567 568 if (bank->regs->set_irqenable) { 569 reg += bank->regs->set_irqenable; 570 l = gpio_mask; 571 bank->context.irqenable1 |= gpio_mask; 572 } else { 573 reg += bank->regs->irqenable; 574 l = readl_relaxed(reg); 575 if (bank->regs->irqenable_inv) 576 l &= ~gpio_mask; 577 else 578 l |= gpio_mask; 579 bank->context.irqenable1 = l; 580 } 581 582 writel_relaxed(l, reg); 583 } 584 585 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask) 586 { 587 void __iomem *reg = bank->base; 588 u32 l; 589 590 if (bank->regs->clr_irqenable) { 591 reg += bank->regs->clr_irqenable; 592 l = gpio_mask; 593 bank->context.irqenable1 &= ~gpio_mask; 594 } else { 595 reg += bank->regs->irqenable; 596 l = readl_relaxed(reg); 597 if (bank->regs->irqenable_inv) 598 l |= gpio_mask; 599 else 600 l &= ~gpio_mask; 601 bank->context.irqenable1 = l; 602 } 603 604 writel_relaxed(l, reg); 605 } 606 607 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank, 608 unsigned offset, int enable) 609 { 610 if (enable) 611 omap_enable_gpio_irqbank(bank, BIT(offset)); 612 else 613 omap_disable_gpio_irqbank(bank, BIT(offset)); 614 } 615 616 /* 617 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register. 618 * 1510 does not seem to have a wake-up register. If JTAG is connected 619 * to the target, system will wake up always on GPIO events. While 620 * system is running all registered GPIO interrupts need to have wake-up 621 * enabled. When system is suspended, only selected GPIO interrupts need 622 * to have wake-up enabled. 623 */ 624 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset, 625 int enable) 626 { 627 u32 gpio_bit = BIT(offset); 628 unsigned long flags; 629 630 if (bank->non_wakeup_gpios & gpio_bit) { 631 dev_err(bank->dev, 632 "Unable to modify wakeup on non-wakeup GPIO%d\n", 633 offset); 634 return -EINVAL; 635 } 636 637 spin_lock_irqsave(&bank->lock, flags); 638 if (enable) 639 bank->context.wake_en |= gpio_bit; 640 else 641 bank->context.wake_en &= ~gpio_bit; 642 643 writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en); 644 spin_unlock_irqrestore(&bank->lock, flags); 645 646 return 0; 647 } 648 649 /* Use disable_irq_wake() and enable_irq_wake() functions from drivers */ 650 static int omap_gpio_wake_enable(struct irq_data *d, unsigned int enable) 651 { 652 struct gpio_bank *bank = omap_irq_data_get_bank(d); 653 unsigned offset = d->hwirq; 654 655 return omap_set_gpio_wakeup(bank, offset, enable); 656 } 657 658 static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) 659 { 660 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 661 unsigned long flags; 662 663 /* 664 * If this is the first gpio_request for the bank, 665 * enable the bank module. 666 */ 667 if (!BANK_USED(bank)) 668 pm_runtime_get_sync(bank->dev); 669 670 spin_lock_irqsave(&bank->lock, flags); 671 omap_enable_gpio_module(bank, offset); 672 bank->mod_usage |= BIT(offset); 673 spin_unlock_irqrestore(&bank->lock, flags); 674 675 return 0; 676 } 677 678 static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) 679 { 680 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip); 681 unsigned long flags; 682 683 spin_lock_irqsave(&bank->lock, flags); 684 bank->mod_usage &= ~(BIT(offset)); 685 if (!LINE_USED(bank->irq_usage, offset)) { 686 omap_set_gpio_direction(bank, offset, 1); 687 omap_clear_gpio_debounce(bank, offset); 688 } 689 omap_disable_gpio_module(bank, offset); 690 spin_unlock_irqrestore(&bank->lock, flags); 691 692 /* 693 * If this is the last gpio to be freed in the bank, 694 * disable the bank module. 695 */ 696 if (!BANK_USED(bank)) 697 pm_runtime_put(bank->dev); 698 } 699 700 /* 701 * We need to unmask the GPIO bank interrupt as soon as possible to 702 * avoid missing GPIO interrupts for other lines in the bank. 703 * Then we need to mask-read-clear-unmask the triggered GPIO lines 704 * in the bank to avoid missing nested interrupts for a GPIO line. 705 * If we wait to unmask individual GPIO lines in the bank after the 706 * line's interrupt handler has been run, we may miss some nested 707 * interrupts. 708 */ 709 static void omap_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 710 { 711 void __iomem *isr_reg = NULL; 712 u32 isr; 713 unsigned int bit; 714 struct gpio_bank *bank; 715 int unmasked = 0; 716 struct irq_chip *irqchip = irq_desc_get_chip(desc); 717 struct gpio_chip *chip = irq_get_handler_data(irq); 718 719 chained_irq_enter(irqchip, desc); 720 721 bank = container_of(chip, struct gpio_bank, chip); 722 isr_reg = bank->base + bank->regs->irqstatus; 723 pm_runtime_get_sync(bank->dev); 724 725 if (WARN_ON(!isr_reg)) 726 goto exit; 727 728 while (1) { 729 u32 isr_saved, level_mask = 0; 730 u32 enabled; 731 732 enabled = omap_get_gpio_irqbank_mask(bank); 733 isr_saved = isr = readl_relaxed(isr_reg) & enabled; 734 735 if (bank->level_mask) 736 level_mask = bank->level_mask & enabled; 737 738 /* clear edge sensitive interrupts before handler(s) are 739 called so that we don't miss any interrupt occurred while 740 executing them */ 741 omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask); 742 omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask); 743 omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask); 744 745 /* if there is only edge sensitive GPIO pin interrupts 746 configured, we could unmask GPIO bank interrupt immediately */ 747 if (!level_mask && !unmasked) { 748 unmasked = 1; 749 chained_irq_exit(irqchip, desc); 750 } 751 752 if (!isr) 753 break; 754 755 while (isr) { 756 bit = __ffs(isr); 757 isr &= ~(BIT(bit)); 758 759 /* 760 * Some chips can't respond to both rising and falling 761 * at the same time. If this irq was requested with 762 * both flags, we need to flip the ICR data for the IRQ 763 * to respond to the IRQ for the opposite direction. 764 * This will be indicated in the bank toggle_mask. 765 */ 766 if (bank->toggle_mask & (BIT(bit))) 767 omap_toggle_gpio_edge_triggering(bank, bit); 768 769 generic_handle_irq(irq_find_mapping(bank->chip.irqdomain, 770 bit)); 771 } 772 } 773 /* if bank has any level sensitive GPIO pin interrupt 774 configured, we must unmask the bank interrupt only after 775 handler(s) are executed in order to avoid spurious bank 776 interrupt */ 777 exit: 778 if (!unmasked) 779 chained_irq_exit(irqchip, desc); 780 pm_runtime_put(bank->dev); 781 } 782 783 static unsigned int omap_gpio_irq_startup(struct irq_data *d) 784 { 785 struct gpio_bank *bank = omap_irq_data_get_bank(d); 786 unsigned long flags; 787 unsigned offset = d->hwirq; 788 789 if (!BANK_USED(bank)) 790 pm_runtime_get_sync(bank->dev); 791 792 spin_lock_irqsave(&bank->lock, flags); 793 794 if (!LINE_USED(bank->mod_usage, offset)) 795 omap_set_gpio_direction(bank, offset, 1); 796 else if (!omap_gpio_is_input(bank, offset)) 797 goto err; 798 omap_enable_gpio_module(bank, offset); 799 bank->irq_usage |= BIT(offset); 800 801 spin_unlock_irqrestore(&bank->lock, flags); 802 omap_gpio_unmask_irq(d); 803 804 return 0; 805 err: 806 spin_unlock_irqrestore(&bank->lock, flags); 807 if (!BANK_USED(bank)) 808 pm_runtime_put(bank->dev); 809 return -EINVAL; 810 } 811 812 static void omap_gpio_irq_shutdown(struct irq_data *d) 813 { 814 struct gpio_bank *bank = omap_irq_data_get_bank(d); 815 unsigned long flags; 816 unsigned offset = d->hwirq; 817 818 spin_lock_irqsave(&bank->lock, flags); 819 bank->irq_usage &= ~(BIT(offset)); 820 omap_set_gpio_irqenable(bank, offset, 0); 821 omap_clear_gpio_irqstatus(bank, offset); 822 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 823 if (!LINE_USED(bank->mod_usage, offset)) 824 omap_clear_gpio_debounce(bank, offset); 825 omap_disable_gpio_module(bank, offset); 826 spin_unlock_irqrestore(&bank->lock, flags); 827 828 /* 829 * If this is the last IRQ to be freed in the bank, 830 * disable the bank module. 831 */ 832 if (!BANK_USED(bank)) 833 pm_runtime_put(bank->dev); 834 } 835 836 static void omap_gpio_ack_irq(struct irq_data *d) 837 { 838 struct gpio_bank *bank = omap_irq_data_get_bank(d); 839 unsigned offset = d->hwirq; 840 841 omap_clear_gpio_irqstatus(bank, offset); 842 } 843 844 static void omap_gpio_mask_irq(struct irq_data *d) 845 { 846 struct gpio_bank *bank = omap_irq_data_get_bank(d); 847 unsigned offset = d->hwirq; 848 unsigned long flags; 849 850 spin_lock_irqsave(&bank->lock, flags); 851 omap_set_gpio_irqenable(bank, offset, 0); 852 omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE); 853 spin_unlock_irqrestore(&bank->lock, flags); 854 } 855 856 static void omap_gpio_unmask_irq(struct irq_data *d) 857 { 858 struct gpio_bank *bank = omap_irq_data_get_bank(d); 859 unsigned offset = d->hwirq; 860 u32 trigger = irqd_get_trigger_type(d); 861 unsigned long flags; 862 863 spin_lock_irqsave(&bank->lock, flags); 864 if (trigger) 865 omap_set_gpio_triggering(bank, offset, trigger); 866 867 /* For level-triggered GPIOs, the clearing must be done after 868 * the HW source is cleared, thus after the handler has run */ 869 if (bank->level_mask & BIT(offset)) { 870 omap_set_gpio_irqenable(bank, offset, 0); 871 omap_clear_gpio_irqstatus(bank, offset); 872 } 873 874 omap_set_gpio_irqenable(bank, offset, 1); 875 spin_unlock_irqrestore(&bank->lock, flags); 876 } 877 878 /*---------------------------------------------------------------------*/ 879 880 static int omap_mpuio_suspend_noirq(struct device *dev) 881 { 882 struct platform_device *pdev = to_platform_device(dev); 883 struct gpio_bank *bank = platform_get_drvdata(pdev); 884 void __iomem *mask_reg = bank->base + 885 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 886 unsigned long flags; 887 888 spin_lock_irqsave(&bank->lock, flags); 889 writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg); 890 spin_unlock_irqrestore(&bank->lock, flags); 891 892 return 0; 893 } 894 895 static int omap_mpuio_resume_noirq(struct device *dev) 896 { 897 struct platform_device *pdev = to_platform_device(dev); 898 struct gpio_bank *bank = platform_get_drvdata(pdev); 899 void __iomem *mask_reg = bank->base + 900 OMAP_MPUIO_GPIO_MASKIT / bank->stride; 901 unsigned long flags; 902 903 spin_lock_irqsave(&bank->lock, flags); 904 writel_relaxed(bank->context.wake_en, mask_reg); 905 spin_unlock_irqrestore(&bank->lock, flags); 906 907 return 0; 908 } 909 910 static const struct dev_pm_ops omap_mpuio_dev_pm_ops = { 911 .suspend_noirq = omap_mpuio_suspend_noirq, 912 .resume_noirq = omap_mpuio_resume_noirq, 913 }; 914 915 /* use platform_driver for this. */ 916 static struct platform_driver omap_mpuio_driver = { 917 .driver = { 918 .name = "mpuio", 919 .pm = &omap_mpuio_dev_pm_ops, 920 }, 921 }; 922 923 static struct platform_device omap_mpuio_device = { 924 .name = "mpuio", 925 .id = -1, 926 .dev = { 927 .driver = &omap_mpuio_driver.driver, 928 } 929 /* could list the /proc/iomem resources */ 930 }; 931 932 static inline void omap_mpuio_init(struct gpio_bank *bank) 933 { 934 platform_set_drvdata(&omap_mpuio_device, bank); 935 936 if (platform_driver_register(&omap_mpuio_driver) == 0) 937 (void) platform_device_register(&omap_mpuio_device); 938 } 939 940 /*---------------------------------------------------------------------*/ 941 942 static int omap_gpio_get_direction(struct gpio_chip *chip, unsigned offset) 943 { 944 struct gpio_bank *bank; 945 unsigned long flags; 946 void __iomem *reg; 947 int dir; 948 949 bank = container_of(chip, struct gpio_bank, chip); 950 reg = bank->base + bank->regs->direction; 951 spin_lock_irqsave(&bank->lock, flags); 952 dir = !!(readl_relaxed(reg) & BIT(offset)); 953 spin_unlock_irqrestore(&bank->lock, flags); 954 return dir; 955 } 956 957 static int omap_gpio_input(struct gpio_chip *chip, unsigned offset) 958 { 959 struct gpio_bank *bank; 960 unsigned long flags; 961 962 bank = container_of(chip, struct gpio_bank, chip); 963 spin_lock_irqsave(&bank->lock, flags); 964 omap_set_gpio_direction(bank, offset, 1); 965 spin_unlock_irqrestore(&bank->lock, flags); 966 return 0; 967 } 968 969 static int omap_gpio_get(struct gpio_chip *chip, unsigned offset) 970 { 971 struct gpio_bank *bank; 972 973 bank = container_of(chip, struct gpio_bank, chip); 974 975 if (omap_gpio_is_input(bank, offset)) 976 return omap_get_gpio_datain(bank, offset); 977 else 978 return omap_get_gpio_dataout(bank, offset); 979 } 980 981 static int omap_gpio_output(struct gpio_chip *chip, unsigned offset, int value) 982 { 983 struct gpio_bank *bank; 984 unsigned long flags; 985 986 bank = container_of(chip, struct gpio_bank, chip); 987 spin_lock_irqsave(&bank->lock, flags); 988 bank->set_dataout(bank, offset, value); 989 omap_set_gpio_direction(bank, offset, 0); 990 spin_unlock_irqrestore(&bank->lock, flags); 991 return 0; 992 } 993 994 static int omap_gpio_debounce(struct gpio_chip *chip, unsigned offset, 995 unsigned debounce) 996 { 997 struct gpio_bank *bank; 998 unsigned long flags; 999 1000 bank = container_of(chip, struct gpio_bank, chip); 1001 1002 spin_lock_irqsave(&bank->lock, flags); 1003 omap2_set_gpio_debounce(bank, offset, debounce); 1004 spin_unlock_irqrestore(&bank->lock, flags); 1005 1006 return 0; 1007 } 1008 1009 static void omap_gpio_set(struct gpio_chip *chip, unsigned offset, int value) 1010 { 1011 struct gpio_bank *bank; 1012 unsigned long flags; 1013 1014 bank = container_of(chip, struct gpio_bank, chip); 1015 spin_lock_irqsave(&bank->lock, flags); 1016 bank->set_dataout(bank, offset, value); 1017 spin_unlock_irqrestore(&bank->lock, flags); 1018 } 1019 1020 /*---------------------------------------------------------------------*/ 1021 1022 static void __init omap_gpio_show_rev(struct gpio_bank *bank) 1023 { 1024 static bool called; 1025 u32 rev; 1026 1027 if (called || bank->regs->revision == USHRT_MAX) 1028 return; 1029 1030 rev = readw_relaxed(bank->base + bank->regs->revision); 1031 pr_info("OMAP GPIO hardware version %d.%d\n", 1032 (rev >> 4) & 0x0f, rev & 0x0f); 1033 1034 called = true; 1035 } 1036 1037 static void omap_gpio_mod_init(struct gpio_bank *bank) 1038 { 1039 void __iomem *base = bank->base; 1040 u32 l = 0xffffffff; 1041 1042 if (bank->width == 16) 1043 l = 0xffff; 1044 1045 if (bank->is_mpuio) { 1046 writel_relaxed(l, bank->base + bank->regs->irqenable); 1047 return; 1048 } 1049 1050 omap_gpio_rmw(base, bank->regs->irqenable, l, 1051 bank->regs->irqenable_inv); 1052 omap_gpio_rmw(base, bank->regs->irqstatus, l, 1053 !bank->regs->irqenable_inv); 1054 if (bank->regs->debounce_en) 1055 writel_relaxed(0, base + bank->regs->debounce_en); 1056 1057 /* Save OE default value (0xffffffff) in the context */ 1058 bank->context.oe = readl_relaxed(bank->base + bank->regs->direction); 1059 /* Initialize interface clk ungated, module enabled */ 1060 if (bank->regs->ctrl) 1061 writel_relaxed(0, base + bank->regs->ctrl); 1062 1063 bank->dbck = clk_get(bank->dev, "dbclk"); 1064 if (IS_ERR(bank->dbck)) 1065 dev_err(bank->dev, "Could not get gpio dbck\n"); 1066 } 1067 1068 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc) 1069 { 1070 static int gpio; 1071 int irq_base = 0; 1072 int ret; 1073 1074 /* 1075 * REVISIT eventually switch from OMAP-specific gpio structs 1076 * over to the generic ones 1077 */ 1078 bank->chip.request = omap_gpio_request; 1079 bank->chip.free = omap_gpio_free; 1080 bank->chip.get_direction = omap_gpio_get_direction; 1081 bank->chip.direction_input = omap_gpio_input; 1082 bank->chip.get = omap_gpio_get; 1083 bank->chip.direction_output = omap_gpio_output; 1084 bank->chip.set_debounce = omap_gpio_debounce; 1085 bank->chip.set = omap_gpio_set; 1086 if (bank->is_mpuio) { 1087 bank->chip.label = "mpuio"; 1088 if (bank->regs->wkup_en) 1089 bank->chip.dev = &omap_mpuio_device.dev; 1090 bank->chip.base = OMAP_MPUIO(0); 1091 } else { 1092 bank->chip.label = "gpio"; 1093 bank->chip.base = gpio; 1094 gpio += bank->width; 1095 } 1096 bank->chip.ngpio = bank->width; 1097 1098 ret = gpiochip_add(&bank->chip); 1099 if (ret) { 1100 dev_err(bank->dev, "Could not register gpio chip %d\n", ret); 1101 return ret; 1102 } 1103 1104 #ifdef CONFIG_ARCH_OMAP1 1105 /* 1106 * REVISIT: Once we have OMAP1 supporting SPARSE_IRQ, we can drop 1107 * irq_alloc_descs() since a base IRQ offset will no longer be needed. 1108 */ 1109 irq_base = irq_alloc_descs(-1, 0, bank->width, 0); 1110 if (irq_base < 0) { 1111 dev_err(bank->dev, "Couldn't allocate IRQ numbers\n"); 1112 return -ENODEV; 1113 } 1114 #endif 1115 1116 /* MPUIO is a bit different, reading IRQ status clears it */ 1117 if (bank->is_mpuio) { 1118 irqc->irq_ack = dummy_irq_chip.irq_ack; 1119 irqc->irq_mask = irq_gc_mask_set_bit; 1120 irqc->irq_unmask = irq_gc_mask_clr_bit; 1121 if (!bank->regs->wkup_en) 1122 irqc->irq_set_wake = NULL; 1123 } 1124 1125 ret = gpiochip_irqchip_add(&bank->chip, irqc, 1126 irq_base, omap_gpio_irq_handler, 1127 IRQ_TYPE_NONE); 1128 1129 if (ret) { 1130 dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret); 1131 gpiochip_remove(&bank->chip); 1132 return -ENODEV; 1133 } 1134 1135 gpiochip_set_chained_irqchip(&bank->chip, irqc, 1136 bank->irq, omap_gpio_irq_handler); 1137 1138 return 0; 1139 } 1140 1141 static const struct of_device_id omap_gpio_match[]; 1142 1143 static int omap_gpio_probe(struct platform_device *pdev) 1144 { 1145 struct device *dev = &pdev->dev; 1146 struct device_node *node = dev->of_node; 1147 const struct of_device_id *match; 1148 const struct omap_gpio_platform_data *pdata; 1149 struct resource *res; 1150 struct gpio_bank *bank; 1151 struct irq_chip *irqc; 1152 int ret; 1153 1154 match = of_match_device(of_match_ptr(omap_gpio_match), dev); 1155 1156 pdata = match ? match->data : dev_get_platdata(dev); 1157 if (!pdata) 1158 return -EINVAL; 1159 1160 bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL); 1161 if (!bank) { 1162 dev_err(dev, "Memory alloc failed\n"); 1163 return -ENOMEM; 1164 } 1165 1166 irqc = devm_kzalloc(dev, sizeof(*irqc), GFP_KERNEL); 1167 if (!irqc) 1168 return -ENOMEM; 1169 1170 irqc->irq_startup = omap_gpio_irq_startup, 1171 irqc->irq_shutdown = omap_gpio_irq_shutdown, 1172 irqc->irq_ack = omap_gpio_ack_irq, 1173 irqc->irq_mask = omap_gpio_mask_irq, 1174 irqc->irq_unmask = omap_gpio_unmask_irq, 1175 irqc->irq_set_type = omap_gpio_irq_type, 1176 irqc->irq_set_wake = omap_gpio_wake_enable, 1177 irqc->name = dev_name(&pdev->dev); 1178 1179 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1180 if (unlikely(!res)) { 1181 dev_err(dev, "Invalid IRQ resource\n"); 1182 return -ENODEV; 1183 } 1184 1185 bank->irq = res->start; 1186 bank->dev = dev; 1187 bank->chip.dev = dev; 1188 bank->dbck_flag = pdata->dbck_flag; 1189 bank->stride = pdata->bank_stride; 1190 bank->width = pdata->bank_width; 1191 bank->is_mpuio = pdata->is_mpuio; 1192 bank->non_wakeup_gpios = pdata->non_wakeup_gpios; 1193 bank->regs = pdata->regs; 1194 #ifdef CONFIG_OF_GPIO 1195 bank->chip.of_node = of_node_get(node); 1196 #endif 1197 if (node) { 1198 if (!of_property_read_bool(node, "ti,gpio-always-on")) 1199 bank->loses_context = true; 1200 } else { 1201 bank->loses_context = pdata->loses_context; 1202 1203 if (bank->loses_context) 1204 bank->get_context_loss_count = 1205 pdata->get_context_loss_count; 1206 } 1207 1208 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1209 bank->set_dataout = omap_set_gpio_dataout_reg; 1210 else 1211 bank->set_dataout = omap_set_gpio_dataout_mask; 1212 1213 spin_lock_init(&bank->lock); 1214 1215 /* Static mapping, never released */ 1216 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1217 bank->base = devm_ioremap_resource(dev, res); 1218 if (IS_ERR(bank->base)) { 1219 irq_domain_remove(bank->chip.irqdomain); 1220 return PTR_ERR(bank->base); 1221 } 1222 1223 platform_set_drvdata(pdev, bank); 1224 1225 pm_runtime_enable(bank->dev); 1226 pm_runtime_irq_safe(bank->dev); 1227 pm_runtime_get_sync(bank->dev); 1228 1229 if (bank->is_mpuio) 1230 omap_mpuio_init(bank); 1231 1232 omap_gpio_mod_init(bank); 1233 1234 ret = omap_gpio_chip_init(bank, irqc); 1235 if (ret) 1236 return ret; 1237 1238 omap_gpio_show_rev(bank); 1239 1240 pm_runtime_put(bank->dev); 1241 1242 list_add_tail(&bank->node, &omap_gpio_list); 1243 1244 return 0; 1245 } 1246 1247 static int omap_gpio_remove(struct platform_device *pdev) 1248 { 1249 struct gpio_bank *bank = platform_get_drvdata(pdev); 1250 1251 list_del(&bank->node); 1252 gpiochip_remove(&bank->chip); 1253 pm_runtime_disable(bank->dev); 1254 1255 return 0; 1256 } 1257 1258 #ifdef CONFIG_ARCH_OMAP2PLUS 1259 1260 #if defined(CONFIG_PM) 1261 static void omap_gpio_restore_context(struct gpio_bank *bank); 1262 1263 static int omap_gpio_runtime_suspend(struct device *dev) 1264 { 1265 struct platform_device *pdev = to_platform_device(dev); 1266 struct gpio_bank *bank = platform_get_drvdata(pdev); 1267 u32 l1 = 0, l2 = 0; 1268 unsigned long flags; 1269 u32 wake_low, wake_hi; 1270 1271 spin_lock_irqsave(&bank->lock, flags); 1272 1273 /* 1274 * Only edges can generate a wakeup event to the PRCM. 1275 * 1276 * Therefore, ensure any wake-up capable GPIOs have 1277 * edge-detection enabled before going idle to ensure a wakeup 1278 * to the PRCM is generated on a GPIO transition. (c.f. 34xx 1279 * NDA TRM 25.5.3.1) 1280 * 1281 * The normal values will be restored upon ->runtime_resume() 1282 * by writing back the values saved in bank->context. 1283 */ 1284 wake_low = bank->context.leveldetect0 & bank->context.wake_en; 1285 if (wake_low) 1286 writel_relaxed(wake_low | bank->context.fallingdetect, 1287 bank->base + bank->regs->fallingdetect); 1288 wake_hi = bank->context.leveldetect1 & bank->context.wake_en; 1289 if (wake_hi) 1290 writel_relaxed(wake_hi | bank->context.risingdetect, 1291 bank->base + bank->regs->risingdetect); 1292 1293 if (!bank->enabled_non_wakeup_gpios) 1294 goto update_gpio_context_count; 1295 1296 if (bank->power_mode != OFF_MODE) { 1297 bank->power_mode = 0; 1298 goto update_gpio_context_count; 1299 } 1300 /* 1301 * If going to OFF, remove triggering for all 1302 * non-wakeup GPIOs. Otherwise spurious IRQs will be 1303 * generated. See OMAP2420 Errata item 1.101. 1304 */ 1305 bank->saved_datain = readl_relaxed(bank->base + 1306 bank->regs->datain); 1307 l1 = bank->context.fallingdetect; 1308 l2 = bank->context.risingdetect; 1309 1310 l1 &= ~bank->enabled_non_wakeup_gpios; 1311 l2 &= ~bank->enabled_non_wakeup_gpios; 1312 1313 writel_relaxed(l1, bank->base + bank->regs->fallingdetect); 1314 writel_relaxed(l2, bank->base + bank->regs->risingdetect); 1315 1316 bank->workaround_enabled = true; 1317 1318 update_gpio_context_count: 1319 if (bank->get_context_loss_count) 1320 bank->context_loss_count = 1321 bank->get_context_loss_count(bank->dev); 1322 1323 omap_gpio_dbck_disable(bank); 1324 spin_unlock_irqrestore(&bank->lock, flags); 1325 1326 return 0; 1327 } 1328 1329 static void omap_gpio_init_context(struct gpio_bank *p); 1330 1331 static int omap_gpio_runtime_resume(struct device *dev) 1332 { 1333 struct platform_device *pdev = to_platform_device(dev); 1334 struct gpio_bank *bank = platform_get_drvdata(pdev); 1335 u32 l = 0, gen, gen0, gen1; 1336 unsigned long flags; 1337 int c; 1338 1339 spin_lock_irqsave(&bank->lock, flags); 1340 1341 /* 1342 * On the first resume during the probe, the context has not 1343 * been initialised and so initialise it now. Also initialise 1344 * the context loss count. 1345 */ 1346 if (bank->loses_context && !bank->context_valid) { 1347 omap_gpio_init_context(bank); 1348 1349 if (bank->get_context_loss_count) 1350 bank->context_loss_count = 1351 bank->get_context_loss_count(bank->dev); 1352 } 1353 1354 omap_gpio_dbck_enable(bank); 1355 1356 /* 1357 * In ->runtime_suspend(), level-triggered, wakeup-enabled 1358 * GPIOs were set to edge trigger also in order to be able to 1359 * generate a PRCM wakeup. Here we restore the 1360 * pre-runtime_suspend() values for edge triggering. 1361 */ 1362 writel_relaxed(bank->context.fallingdetect, 1363 bank->base + bank->regs->fallingdetect); 1364 writel_relaxed(bank->context.risingdetect, 1365 bank->base + bank->regs->risingdetect); 1366 1367 if (bank->loses_context) { 1368 if (!bank->get_context_loss_count) { 1369 omap_gpio_restore_context(bank); 1370 } else { 1371 c = bank->get_context_loss_count(bank->dev); 1372 if (c != bank->context_loss_count) { 1373 omap_gpio_restore_context(bank); 1374 } else { 1375 spin_unlock_irqrestore(&bank->lock, flags); 1376 return 0; 1377 } 1378 } 1379 } 1380 1381 if (!bank->workaround_enabled) { 1382 spin_unlock_irqrestore(&bank->lock, flags); 1383 return 0; 1384 } 1385 1386 l = readl_relaxed(bank->base + bank->regs->datain); 1387 1388 /* 1389 * Check if any of the non-wakeup interrupt GPIOs have changed 1390 * state. If so, generate an IRQ by software. This is 1391 * horribly racy, but it's the best we can do to work around 1392 * this silicon bug. 1393 */ 1394 l ^= bank->saved_datain; 1395 l &= bank->enabled_non_wakeup_gpios; 1396 1397 /* 1398 * No need to generate IRQs for the rising edge for gpio IRQs 1399 * configured with falling edge only; and vice versa. 1400 */ 1401 gen0 = l & bank->context.fallingdetect; 1402 gen0 &= bank->saved_datain; 1403 1404 gen1 = l & bank->context.risingdetect; 1405 gen1 &= ~(bank->saved_datain); 1406 1407 /* FIXME: Consider GPIO IRQs with level detections properly! */ 1408 gen = l & (~(bank->context.fallingdetect) & 1409 ~(bank->context.risingdetect)); 1410 /* Consider all GPIO IRQs needed to be updated */ 1411 gen |= gen0 | gen1; 1412 1413 if (gen) { 1414 u32 old0, old1; 1415 1416 old0 = readl_relaxed(bank->base + bank->regs->leveldetect0); 1417 old1 = readl_relaxed(bank->base + bank->regs->leveldetect1); 1418 1419 if (!bank->regs->irqstatus_raw0) { 1420 writel_relaxed(old0 | gen, bank->base + 1421 bank->regs->leveldetect0); 1422 writel_relaxed(old1 | gen, bank->base + 1423 bank->regs->leveldetect1); 1424 } 1425 1426 if (bank->regs->irqstatus_raw0) { 1427 writel_relaxed(old0 | l, bank->base + 1428 bank->regs->leveldetect0); 1429 writel_relaxed(old1 | l, bank->base + 1430 bank->regs->leveldetect1); 1431 } 1432 writel_relaxed(old0, bank->base + bank->regs->leveldetect0); 1433 writel_relaxed(old1, bank->base + bank->regs->leveldetect1); 1434 } 1435 1436 bank->workaround_enabled = false; 1437 spin_unlock_irqrestore(&bank->lock, flags); 1438 1439 return 0; 1440 } 1441 #endif /* CONFIG_PM */ 1442 1443 #if IS_BUILTIN(CONFIG_GPIO_OMAP) 1444 void omap2_gpio_prepare_for_idle(int pwr_mode) 1445 { 1446 struct gpio_bank *bank; 1447 1448 list_for_each_entry(bank, &omap_gpio_list, node) { 1449 if (!BANK_USED(bank) || !bank->loses_context) 1450 continue; 1451 1452 bank->power_mode = pwr_mode; 1453 1454 pm_runtime_put_sync_suspend(bank->dev); 1455 } 1456 } 1457 1458 void omap2_gpio_resume_after_idle(void) 1459 { 1460 struct gpio_bank *bank; 1461 1462 list_for_each_entry(bank, &omap_gpio_list, node) { 1463 if (!BANK_USED(bank) || !bank->loses_context) 1464 continue; 1465 1466 pm_runtime_get_sync(bank->dev); 1467 } 1468 } 1469 #endif 1470 1471 #if defined(CONFIG_PM) 1472 static void omap_gpio_init_context(struct gpio_bank *p) 1473 { 1474 struct omap_gpio_reg_offs *regs = p->regs; 1475 void __iomem *base = p->base; 1476 1477 p->context.ctrl = readl_relaxed(base + regs->ctrl); 1478 p->context.oe = readl_relaxed(base + regs->direction); 1479 p->context.wake_en = readl_relaxed(base + regs->wkup_en); 1480 p->context.leveldetect0 = readl_relaxed(base + regs->leveldetect0); 1481 p->context.leveldetect1 = readl_relaxed(base + regs->leveldetect1); 1482 p->context.risingdetect = readl_relaxed(base + regs->risingdetect); 1483 p->context.fallingdetect = readl_relaxed(base + regs->fallingdetect); 1484 p->context.irqenable1 = readl_relaxed(base + regs->irqenable); 1485 p->context.irqenable2 = readl_relaxed(base + regs->irqenable2); 1486 1487 if (regs->set_dataout && p->regs->clr_dataout) 1488 p->context.dataout = readl_relaxed(base + regs->set_dataout); 1489 else 1490 p->context.dataout = readl_relaxed(base + regs->dataout); 1491 1492 p->context_valid = true; 1493 } 1494 1495 static void omap_gpio_restore_context(struct gpio_bank *bank) 1496 { 1497 writel_relaxed(bank->context.wake_en, 1498 bank->base + bank->regs->wkup_en); 1499 writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl); 1500 writel_relaxed(bank->context.leveldetect0, 1501 bank->base + bank->regs->leveldetect0); 1502 writel_relaxed(bank->context.leveldetect1, 1503 bank->base + bank->regs->leveldetect1); 1504 writel_relaxed(bank->context.risingdetect, 1505 bank->base + bank->regs->risingdetect); 1506 writel_relaxed(bank->context.fallingdetect, 1507 bank->base + bank->regs->fallingdetect); 1508 if (bank->regs->set_dataout && bank->regs->clr_dataout) 1509 writel_relaxed(bank->context.dataout, 1510 bank->base + bank->regs->set_dataout); 1511 else 1512 writel_relaxed(bank->context.dataout, 1513 bank->base + bank->regs->dataout); 1514 writel_relaxed(bank->context.oe, bank->base + bank->regs->direction); 1515 1516 if (bank->dbck_enable_mask) { 1517 writel_relaxed(bank->context.debounce, bank->base + 1518 bank->regs->debounce); 1519 writel_relaxed(bank->context.debounce_en, 1520 bank->base + bank->regs->debounce_en); 1521 } 1522 1523 writel_relaxed(bank->context.irqenable1, 1524 bank->base + bank->regs->irqenable); 1525 writel_relaxed(bank->context.irqenable2, 1526 bank->base + bank->regs->irqenable2); 1527 } 1528 #endif /* CONFIG_PM */ 1529 #else 1530 #define omap_gpio_runtime_suspend NULL 1531 #define omap_gpio_runtime_resume NULL 1532 static inline void omap_gpio_init_context(struct gpio_bank *p) {} 1533 #endif 1534 1535 static const struct dev_pm_ops gpio_pm_ops = { 1536 SET_RUNTIME_PM_OPS(omap_gpio_runtime_suspend, omap_gpio_runtime_resume, 1537 NULL) 1538 }; 1539 1540 #if defined(CONFIG_OF) 1541 static struct omap_gpio_reg_offs omap2_gpio_regs = { 1542 .revision = OMAP24XX_GPIO_REVISION, 1543 .direction = OMAP24XX_GPIO_OE, 1544 .datain = OMAP24XX_GPIO_DATAIN, 1545 .dataout = OMAP24XX_GPIO_DATAOUT, 1546 .set_dataout = OMAP24XX_GPIO_SETDATAOUT, 1547 .clr_dataout = OMAP24XX_GPIO_CLEARDATAOUT, 1548 .irqstatus = OMAP24XX_GPIO_IRQSTATUS1, 1549 .irqstatus2 = OMAP24XX_GPIO_IRQSTATUS2, 1550 .irqenable = OMAP24XX_GPIO_IRQENABLE1, 1551 .irqenable2 = OMAP24XX_GPIO_IRQENABLE2, 1552 .set_irqenable = OMAP24XX_GPIO_SETIRQENABLE1, 1553 .clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1, 1554 .debounce = OMAP24XX_GPIO_DEBOUNCE_VAL, 1555 .debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN, 1556 .ctrl = OMAP24XX_GPIO_CTRL, 1557 .wkup_en = OMAP24XX_GPIO_WAKE_EN, 1558 .leveldetect0 = OMAP24XX_GPIO_LEVELDETECT0, 1559 .leveldetect1 = OMAP24XX_GPIO_LEVELDETECT1, 1560 .risingdetect = OMAP24XX_GPIO_RISINGDETECT, 1561 .fallingdetect = OMAP24XX_GPIO_FALLINGDETECT, 1562 }; 1563 1564 static struct omap_gpio_reg_offs omap4_gpio_regs = { 1565 .revision = OMAP4_GPIO_REVISION, 1566 .direction = OMAP4_GPIO_OE, 1567 .datain = OMAP4_GPIO_DATAIN, 1568 .dataout = OMAP4_GPIO_DATAOUT, 1569 .set_dataout = OMAP4_GPIO_SETDATAOUT, 1570 .clr_dataout = OMAP4_GPIO_CLEARDATAOUT, 1571 .irqstatus = OMAP4_GPIO_IRQSTATUS0, 1572 .irqstatus2 = OMAP4_GPIO_IRQSTATUS1, 1573 .irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1574 .irqenable2 = OMAP4_GPIO_IRQSTATUSSET1, 1575 .set_irqenable = OMAP4_GPIO_IRQSTATUSSET0, 1576 .clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0, 1577 .debounce = OMAP4_GPIO_DEBOUNCINGTIME, 1578 .debounce_en = OMAP4_GPIO_DEBOUNCENABLE, 1579 .ctrl = OMAP4_GPIO_CTRL, 1580 .wkup_en = OMAP4_GPIO_IRQWAKEN0, 1581 .leveldetect0 = OMAP4_GPIO_LEVELDETECT0, 1582 .leveldetect1 = OMAP4_GPIO_LEVELDETECT1, 1583 .risingdetect = OMAP4_GPIO_RISINGDETECT, 1584 .fallingdetect = OMAP4_GPIO_FALLINGDETECT, 1585 }; 1586 1587 static const struct omap_gpio_platform_data omap2_pdata = { 1588 .regs = &omap2_gpio_regs, 1589 .bank_width = 32, 1590 .dbck_flag = false, 1591 }; 1592 1593 static const struct omap_gpio_platform_data omap3_pdata = { 1594 .regs = &omap2_gpio_regs, 1595 .bank_width = 32, 1596 .dbck_flag = true, 1597 }; 1598 1599 static const struct omap_gpio_platform_data omap4_pdata = { 1600 .regs = &omap4_gpio_regs, 1601 .bank_width = 32, 1602 .dbck_flag = true, 1603 }; 1604 1605 static const struct of_device_id omap_gpio_match[] = { 1606 { 1607 .compatible = "ti,omap4-gpio", 1608 .data = &omap4_pdata, 1609 }, 1610 { 1611 .compatible = "ti,omap3-gpio", 1612 .data = &omap3_pdata, 1613 }, 1614 { 1615 .compatible = "ti,omap2-gpio", 1616 .data = &omap2_pdata, 1617 }, 1618 { }, 1619 }; 1620 MODULE_DEVICE_TABLE(of, omap_gpio_match); 1621 #endif 1622 1623 static struct platform_driver omap_gpio_driver = { 1624 .probe = omap_gpio_probe, 1625 .remove = omap_gpio_remove, 1626 .driver = { 1627 .name = "omap_gpio", 1628 .pm = &gpio_pm_ops, 1629 .of_match_table = of_match_ptr(omap_gpio_match), 1630 }, 1631 }; 1632 1633 /* 1634 * gpio driver register needs to be done before 1635 * machine_init functions access gpio APIs. 1636 * Hence omap_gpio_drv_reg() is a postcore_initcall. 1637 */ 1638 static int __init omap_gpio_drv_reg(void) 1639 { 1640 return platform_driver_register(&omap_gpio_driver); 1641 } 1642 postcore_initcall(omap_gpio_drv_reg); 1643 1644 static void __exit omap_gpio_exit(void) 1645 { 1646 platform_driver_unregister(&omap_gpio_driver); 1647 } 1648 module_exit(omap_gpio_exit); 1649 1650 MODULE_DESCRIPTION("omap gpio driver"); 1651 MODULE_ALIAS("platform:gpio-omap"); 1652 MODULE_LICENSE("GPL v2"); 1653