1 /* 2 * Generic GPIO driver for logic cells found in the Nomadik SoC 3 * 4 * Copyright (C) 2008,2009 STMicroelectronics 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 #include <linux/kernel.h> 14 #include <linux/module.h> 15 #include <linux/init.h> 16 #include <linux/device.h> 17 #include <linux/platform_device.h> 18 #include <linux/io.h> 19 #include <linux/clk.h> 20 #include <linux/err.h> 21 #include <linux/gpio.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/slab.h> 26 27 #include <asm/mach/irq.h> 28 29 #include <plat/pincfg.h> 30 #include <mach/hardware.h> 31 #include <mach/gpio.h> 32 33 /* 34 * The GPIO module in the Nomadik family of Systems-on-Chip is an 35 * AMBA device, managing 32 pins and alternate functions. The logic block 36 * is currently used in the Nomadik and ux500. 37 * 38 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 39 */ 40 41 #define NMK_GPIO_PER_CHIP 32 42 43 struct nmk_gpio_chip { 44 struct gpio_chip chip; 45 void __iomem *addr; 46 struct clk *clk; 47 unsigned int bank; 48 unsigned int parent_irq; 49 int secondary_parent_irq; 50 u32 (*get_secondary_status)(unsigned int bank); 51 void (*set_ioforce)(bool enable); 52 spinlock_t lock; 53 bool sleepmode; 54 /* Keep track of configured edges */ 55 u32 edge_rising; 56 u32 edge_falling; 57 u32 real_wake; 58 u32 rwimsc; 59 u32 fwimsc; 60 u32 slpm; 61 u32 enabled; 62 u32 pull_up; 63 }; 64 65 static struct nmk_gpio_chip * 66 nmk_gpio_chips[DIV_ROUND_UP(ARCH_NR_GPIOS, NMK_GPIO_PER_CHIP)]; 67 68 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 69 70 #define NUM_BANKS ARRAY_SIZE(nmk_gpio_chips) 71 72 static void __nmk_gpio_set_mode(struct nmk_gpio_chip *nmk_chip, 73 unsigned offset, int gpio_mode) 74 { 75 u32 bit = 1 << offset; 76 u32 afunc, bfunc; 77 78 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & ~bit; 79 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & ~bit; 80 if (gpio_mode & NMK_GPIO_ALT_A) 81 afunc |= bit; 82 if (gpio_mode & NMK_GPIO_ALT_B) 83 bfunc |= bit; 84 writel(afunc, nmk_chip->addr + NMK_GPIO_AFSLA); 85 writel(bfunc, nmk_chip->addr + NMK_GPIO_AFSLB); 86 } 87 88 static void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, 89 unsigned offset, enum nmk_gpio_slpm mode) 90 { 91 u32 bit = 1 << offset; 92 u32 slpm; 93 94 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 95 if (mode == NMK_GPIO_SLPM_NOCHANGE) 96 slpm |= bit; 97 else 98 slpm &= ~bit; 99 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 100 } 101 102 static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, 103 unsigned offset, enum nmk_gpio_pull pull) 104 { 105 u32 bit = 1 << offset; 106 u32 pdis; 107 108 pdis = readl(nmk_chip->addr + NMK_GPIO_PDIS); 109 if (pull == NMK_GPIO_PULL_NONE) { 110 pdis |= bit; 111 nmk_chip->pull_up &= ~bit; 112 } else { 113 pdis &= ~bit; 114 } 115 116 writel(pdis, nmk_chip->addr + NMK_GPIO_PDIS); 117 118 if (pull == NMK_GPIO_PULL_UP) { 119 nmk_chip->pull_up |= bit; 120 writel(bit, nmk_chip->addr + NMK_GPIO_DATS); 121 } else if (pull == NMK_GPIO_PULL_DOWN) { 122 nmk_chip->pull_up &= ~bit; 123 writel(bit, nmk_chip->addr + NMK_GPIO_DATC); 124 } 125 } 126 127 static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, 128 unsigned offset) 129 { 130 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 131 } 132 133 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 134 unsigned offset, int val) 135 { 136 if (val) 137 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATS); 138 else 139 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DATC); 140 } 141 142 static void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 143 unsigned offset, int val) 144 { 145 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRS); 146 __nmk_gpio_set_output(nmk_chip, offset, val); 147 } 148 149 static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, 150 unsigned offset, int gpio_mode, 151 bool glitch) 152 { 153 u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); 154 u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); 155 156 if (glitch && nmk_chip->set_ioforce) { 157 u32 bit = BIT(offset); 158 159 /* Prevent spurious wakeups */ 160 writel(rwimsc & ~bit, nmk_chip->addr + NMK_GPIO_RWIMSC); 161 writel(fwimsc & ~bit, nmk_chip->addr + NMK_GPIO_FWIMSC); 162 163 nmk_chip->set_ioforce(true); 164 } 165 166 __nmk_gpio_set_mode(nmk_chip, offset, gpio_mode); 167 168 if (glitch && nmk_chip->set_ioforce) { 169 nmk_chip->set_ioforce(false); 170 171 writel(rwimsc, nmk_chip->addr + NMK_GPIO_RWIMSC); 172 writel(fwimsc, nmk_chip->addr + NMK_GPIO_FWIMSC); 173 } 174 } 175 176 static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, 177 pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) 178 { 179 static const char *afnames[] = { 180 [NMK_GPIO_ALT_GPIO] = "GPIO", 181 [NMK_GPIO_ALT_A] = "A", 182 [NMK_GPIO_ALT_B] = "B", 183 [NMK_GPIO_ALT_C] = "C" 184 }; 185 static const char *pullnames[] = { 186 [NMK_GPIO_PULL_NONE] = "none", 187 [NMK_GPIO_PULL_UP] = "up", 188 [NMK_GPIO_PULL_DOWN] = "down", 189 [3] /* illegal */ = "??" 190 }; 191 static const char *slpmnames[] = { 192 [NMK_GPIO_SLPM_INPUT] = "input/wakeup", 193 [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", 194 }; 195 196 int pin = PIN_NUM(cfg); 197 int pull = PIN_PULL(cfg); 198 int af = PIN_ALT(cfg); 199 int slpm = PIN_SLPM(cfg); 200 int output = PIN_DIR(cfg); 201 int val = PIN_VAL(cfg); 202 bool glitch = af == NMK_GPIO_ALT_C; 203 204 dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: af %s, pull %s, slpm %s (%s%s)\n", 205 pin, cfg, afnames[af], pullnames[pull], slpmnames[slpm], 206 output ? "output " : "input", 207 output ? (val ? "high" : "low") : ""); 208 209 if (sleep) { 210 int slpm_pull = PIN_SLPM_PULL(cfg); 211 int slpm_output = PIN_SLPM_DIR(cfg); 212 int slpm_val = PIN_SLPM_VAL(cfg); 213 214 af = NMK_GPIO_ALT_GPIO; 215 216 /* 217 * The SLPM_* values are normal values + 1 to allow zero to 218 * mean "same as normal". 219 */ 220 if (slpm_pull) 221 pull = slpm_pull - 1; 222 if (slpm_output) 223 output = slpm_output - 1; 224 if (slpm_val) 225 val = slpm_val - 1; 226 227 dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", 228 pin, 229 slpm_pull ? pullnames[pull] : "same", 230 slpm_output ? (output ? "output" : "input") : "same", 231 slpm_val ? (val ? "high" : "low") : "same"); 232 } 233 234 if (output) 235 __nmk_gpio_make_output(nmk_chip, offset, val); 236 else { 237 __nmk_gpio_make_input(nmk_chip, offset); 238 __nmk_gpio_set_pull(nmk_chip, offset, pull); 239 } 240 241 /* 242 * If we've backed up the SLPM registers (glitch workaround), modify 243 * the backups since they will be restored. 244 */ 245 if (slpmregs) { 246 if (slpm == NMK_GPIO_SLPM_NOCHANGE) 247 slpmregs[nmk_chip->bank] |= BIT(offset); 248 else 249 slpmregs[nmk_chip->bank] &= ~BIT(offset); 250 } else 251 __nmk_gpio_set_slpm(nmk_chip, offset, slpm); 252 253 __nmk_gpio_set_mode_safe(nmk_chip, offset, af, glitch); 254 } 255 256 /* 257 * Safe sequence used to switch IOs between GPIO and Alternate-C mode: 258 * - Save SLPM registers 259 * - Set SLPM=0 for the IOs you want to switch and others to 1 260 * - Configure the GPIO registers for the IOs that are being switched 261 * - Set IOFORCE=1 262 * - Modify the AFLSA/B registers for the IOs that are being switched 263 * - Set IOFORCE=0 264 * - Restore SLPM registers 265 * - Any spurious wake up event during switch sequence to be ignored and 266 * cleared 267 */ 268 static void nmk_gpio_glitch_slpm_init(unsigned int *slpm) 269 { 270 int i; 271 272 for (i = 0; i < NUM_BANKS; i++) { 273 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 274 unsigned int temp = slpm[i]; 275 276 if (!chip) 277 break; 278 279 slpm[i] = readl(chip->addr + NMK_GPIO_SLPC); 280 writel(temp, chip->addr + NMK_GPIO_SLPC); 281 } 282 } 283 284 static void nmk_gpio_glitch_slpm_restore(unsigned int *slpm) 285 { 286 int i; 287 288 for (i = 0; i < NUM_BANKS; i++) { 289 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 290 291 if (!chip) 292 break; 293 294 writel(slpm[i], chip->addr + NMK_GPIO_SLPC); 295 } 296 } 297 298 static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) 299 { 300 static unsigned int slpm[NUM_BANKS]; 301 unsigned long flags; 302 bool glitch = false; 303 int ret = 0; 304 int i; 305 306 for (i = 0; i < num; i++) { 307 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) { 308 glitch = true; 309 break; 310 } 311 } 312 313 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 314 315 if (glitch) { 316 memset(slpm, 0xff, sizeof(slpm)); 317 318 for (i = 0; i < num; i++) { 319 int pin = PIN_NUM(cfgs[i]); 320 int offset = pin % NMK_GPIO_PER_CHIP; 321 322 if (PIN_ALT(cfgs[i]) == NMK_GPIO_ALT_C) 323 slpm[pin / NMK_GPIO_PER_CHIP] &= ~BIT(offset); 324 } 325 326 nmk_gpio_glitch_slpm_init(slpm); 327 } 328 329 for (i = 0; i < num; i++) { 330 struct nmk_gpio_chip *nmk_chip; 331 int pin = PIN_NUM(cfgs[i]); 332 333 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); 334 if (!nmk_chip) { 335 ret = -EINVAL; 336 break; 337 } 338 339 spin_lock(&nmk_chip->lock); 340 __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, 341 cfgs[i], sleep, glitch ? slpm : NULL); 342 spin_unlock(&nmk_chip->lock); 343 } 344 345 if (glitch) 346 nmk_gpio_glitch_slpm_restore(slpm); 347 348 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 349 350 return ret; 351 } 352 353 /** 354 * nmk_config_pin - configure a pin's mux attributes 355 * @cfg: pin confguration 356 * 357 * Configures a pin's mode (alternate function or GPIO), its pull up status, 358 * and its sleep mode based on the specified configuration. The @cfg is 359 * usually one of the SoC specific macros defined in mach/<soc>-pins.h. These 360 * are constructed using, and can be further enhanced with, the macros in 361 * plat/pincfg.h. 362 * 363 * If a pin's mode is set to GPIO, it is configured as an input to avoid 364 * side-effects. The gpio can be manipulated later using standard GPIO API 365 * calls. 366 */ 367 int nmk_config_pin(pin_cfg_t cfg, bool sleep) 368 { 369 return __nmk_config_pins(&cfg, 1, sleep); 370 } 371 EXPORT_SYMBOL(nmk_config_pin); 372 373 /** 374 * nmk_config_pins - configure several pins at once 375 * @cfgs: array of pin configurations 376 * @num: number of elments in the array 377 * 378 * Configures several pins using nmk_config_pin(). Refer to that function for 379 * further information. 380 */ 381 int nmk_config_pins(pin_cfg_t *cfgs, int num) 382 { 383 return __nmk_config_pins(cfgs, num, false); 384 } 385 EXPORT_SYMBOL(nmk_config_pins); 386 387 int nmk_config_pins_sleep(pin_cfg_t *cfgs, int num) 388 { 389 return __nmk_config_pins(cfgs, num, true); 390 } 391 EXPORT_SYMBOL(nmk_config_pins_sleep); 392 393 /** 394 * nmk_gpio_set_slpm() - configure the sleep mode of a pin 395 * @gpio: pin number 396 * @mode: NMK_GPIO_SLPM_INPUT or NMK_GPIO_SLPM_NOCHANGE, 397 * 398 * This register is actually in the pinmux layer, not the GPIO block itself. 399 * The GPIO1B_SLPM register defines the GPIO mode when SLEEP/DEEP-SLEEP 400 * mode is entered (i.e. when signal IOFORCE is HIGH by the platform code). 401 * Each GPIO can be configured to be forced into GPIO mode when IOFORCE is 402 * HIGH, overriding the normal setting defined by GPIO_AFSELx registers. 403 * When IOFORCE returns LOW (by software, after SLEEP/DEEP-SLEEP exit), 404 * the GPIOs return to the normal setting defined by GPIO_AFSELx registers. 405 * 406 * If @mode is NMK_GPIO_SLPM_INPUT, the corresponding GPIO is switched to GPIO 407 * mode when signal IOFORCE is HIGH (i.e. when SLEEP/DEEP-SLEEP mode is 408 * entered) regardless of the altfunction selected. Also wake-up detection is 409 * ENABLED. 410 * 411 * If @mode is NMK_GPIO_SLPM_NOCHANGE, the corresponding GPIO remains 412 * controlled by NMK_GPIO_DATC, NMK_GPIO_DATS, NMK_GPIO_DIR, NMK_GPIO_PDIS 413 * (for altfunction GPIO) or respective on-chip peripherals (for other 414 * altfuncs) when IOFORCE is HIGH. Also wake-up detection DISABLED. 415 * 416 * Note that enable_irq_wake() will automatically enable wakeup detection. 417 */ 418 int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) 419 { 420 struct nmk_gpio_chip *nmk_chip; 421 unsigned long flags; 422 423 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 424 if (!nmk_chip) 425 return -EINVAL; 426 427 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 428 spin_lock(&nmk_chip->lock); 429 430 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); 431 432 spin_unlock(&nmk_chip->lock); 433 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 434 435 return 0; 436 } 437 438 /** 439 * nmk_gpio_set_pull() - enable/disable pull up/down on a gpio 440 * @gpio: pin number 441 * @pull: one of NMK_GPIO_PULL_DOWN, NMK_GPIO_PULL_UP, and NMK_GPIO_PULL_NONE 442 * 443 * Enables/disables pull up/down on a specified pin. This only takes effect if 444 * the pin is configured as an input (either explicitly or by the alternate 445 * function). 446 * 447 * NOTE: If enabling the pull up/down, the caller must ensure that the GPIO is 448 * configured as an input. Otherwise, due to the way the controller registers 449 * work, this function will change the value output on the pin. 450 */ 451 int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) 452 { 453 struct nmk_gpio_chip *nmk_chip; 454 unsigned long flags; 455 456 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 457 if (!nmk_chip) 458 return -EINVAL; 459 460 spin_lock_irqsave(&nmk_chip->lock, flags); 461 __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); 462 spin_unlock_irqrestore(&nmk_chip->lock, flags); 463 464 return 0; 465 } 466 467 /* Mode functions */ 468 /** 469 * nmk_gpio_set_mode() - set the mux mode of a gpio pin 470 * @gpio: pin number 471 * @gpio_mode: one of NMK_GPIO_ALT_GPIO, NMK_GPIO_ALT_A, 472 * NMK_GPIO_ALT_B, and NMK_GPIO_ALT_C 473 * 474 * Sets the mode of the specified pin to one of the alternate functions or 475 * plain GPIO. 476 */ 477 int nmk_gpio_set_mode(int gpio, int gpio_mode) 478 { 479 struct nmk_gpio_chip *nmk_chip; 480 unsigned long flags; 481 482 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 483 if (!nmk_chip) 484 return -EINVAL; 485 486 spin_lock_irqsave(&nmk_chip->lock, flags); 487 __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); 488 spin_unlock_irqrestore(&nmk_chip->lock, flags); 489 490 return 0; 491 } 492 EXPORT_SYMBOL(nmk_gpio_set_mode); 493 494 int nmk_gpio_get_mode(int gpio) 495 { 496 struct nmk_gpio_chip *nmk_chip; 497 u32 afunc, bfunc, bit; 498 499 nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); 500 if (!nmk_chip) 501 return -EINVAL; 502 503 bit = 1 << (gpio - nmk_chip->chip.base); 504 505 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & bit; 506 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & bit; 507 508 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 509 } 510 EXPORT_SYMBOL(nmk_gpio_get_mode); 511 512 513 /* IRQ functions */ 514 static inline int nmk_gpio_get_bitmask(int gpio) 515 { 516 return 1 << (gpio % 32); 517 } 518 519 static void nmk_gpio_irq_ack(struct irq_data *d) 520 { 521 int gpio; 522 struct nmk_gpio_chip *nmk_chip; 523 524 gpio = NOMADIK_IRQ_TO_GPIO(d->irq); 525 nmk_chip = irq_data_get_irq_chip_data(d); 526 if (!nmk_chip) 527 return; 528 writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); 529 } 530 531 enum nmk_gpio_irq_type { 532 NORMAL, 533 WAKE, 534 }; 535 536 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 537 int gpio, enum nmk_gpio_irq_type which, 538 bool enable) 539 { 540 u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; 541 u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; 542 u32 bitmask = nmk_gpio_get_bitmask(gpio); 543 u32 reg; 544 545 /* we must individually set/clear the two edges */ 546 if (nmk_chip->edge_rising & bitmask) { 547 reg = readl(nmk_chip->addr + rimsc); 548 if (enable) 549 reg |= bitmask; 550 else 551 reg &= ~bitmask; 552 writel(reg, nmk_chip->addr + rimsc); 553 } 554 if (nmk_chip->edge_falling & bitmask) { 555 reg = readl(nmk_chip->addr + fimsc); 556 if (enable) 557 reg |= bitmask; 558 else 559 reg &= ~bitmask; 560 writel(reg, nmk_chip->addr + fimsc); 561 } 562 } 563 564 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 565 int gpio, bool on) 566 { 567 if (nmk_chip->sleepmode) { 568 __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, 569 on ? NMK_GPIO_SLPM_WAKEUP_ENABLE 570 : NMK_GPIO_SLPM_WAKEUP_DISABLE); 571 } 572 573 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); 574 } 575 576 static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) 577 { 578 int gpio; 579 struct nmk_gpio_chip *nmk_chip; 580 unsigned long flags; 581 u32 bitmask; 582 583 gpio = NOMADIK_IRQ_TO_GPIO(d->irq); 584 nmk_chip = irq_data_get_irq_chip_data(d); 585 bitmask = nmk_gpio_get_bitmask(gpio); 586 if (!nmk_chip) 587 return -EINVAL; 588 589 if (enable) 590 nmk_chip->enabled |= bitmask; 591 else 592 nmk_chip->enabled &= ~bitmask; 593 594 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 595 spin_lock(&nmk_chip->lock); 596 597 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); 598 599 if (!(nmk_chip->real_wake & bitmask)) 600 __nmk_gpio_set_wake(nmk_chip, gpio, enable); 601 602 spin_unlock(&nmk_chip->lock); 603 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 604 605 return 0; 606 } 607 608 static void nmk_gpio_irq_mask(struct irq_data *d) 609 { 610 nmk_gpio_irq_maskunmask(d, false); 611 } 612 613 static void nmk_gpio_irq_unmask(struct irq_data *d) 614 { 615 nmk_gpio_irq_maskunmask(d, true); 616 } 617 618 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 619 { 620 struct nmk_gpio_chip *nmk_chip; 621 unsigned long flags; 622 u32 bitmask; 623 int gpio; 624 625 gpio = NOMADIK_IRQ_TO_GPIO(d->irq); 626 nmk_chip = irq_data_get_irq_chip_data(d); 627 if (!nmk_chip) 628 return -EINVAL; 629 bitmask = nmk_gpio_get_bitmask(gpio); 630 631 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 632 spin_lock(&nmk_chip->lock); 633 634 if (!(nmk_chip->enabled & bitmask)) 635 __nmk_gpio_set_wake(nmk_chip, gpio, on); 636 637 if (on) 638 nmk_chip->real_wake |= bitmask; 639 else 640 nmk_chip->real_wake &= ~bitmask; 641 642 spin_unlock(&nmk_chip->lock); 643 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 644 645 return 0; 646 } 647 648 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 649 { 650 bool enabled, wake = irqd_is_wakeup_set(d); 651 int gpio; 652 struct nmk_gpio_chip *nmk_chip; 653 unsigned long flags; 654 u32 bitmask; 655 656 gpio = NOMADIK_IRQ_TO_GPIO(d->irq); 657 nmk_chip = irq_data_get_irq_chip_data(d); 658 bitmask = nmk_gpio_get_bitmask(gpio); 659 if (!nmk_chip) 660 return -EINVAL; 661 662 if (type & IRQ_TYPE_LEVEL_HIGH) 663 return -EINVAL; 664 if (type & IRQ_TYPE_LEVEL_LOW) 665 return -EINVAL; 666 667 enabled = nmk_chip->enabled & bitmask; 668 669 spin_lock_irqsave(&nmk_chip->lock, flags); 670 671 if (enabled) 672 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); 673 674 if (enabled || wake) 675 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); 676 677 nmk_chip->edge_rising &= ~bitmask; 678 if (type & IRQ_TYPE_EDGE_RISING) 679 nmk_chip->edge_rising |= bitmask; 680 681 nmk_chip->edge_falling &= ~bitmask; 682 if (type & IRQ_TYPE_EDGE_FALLING) 683 nmk_chip->edge_falling |= bitmask; 684 685 if (enabled) 686 __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); 687 688 if (enabled || wake) 689 __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); 690 691 spin_unlock_irqrestore(&nmk_chip->lock, flags); 692 693 return 0; 694 } 695 696 static struct irq_chip nmk_gpio_irq_chip = { 697 .name = "Nomadik-GPIO", 698 .irq_ack = nmk_gpio_irq_ack, 699 .irq_mask = nmk_gpio_irq_mask, 700 .irq_unmask = nmk_gpio_irq_unmask, 701 .irq_set_type = nmk_gpio_irq_set_type, 702 .irq_set_wake = nmk_gpio_irq_set_wake, 703 }; 704 705 static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, 706 u32 status) 707 { 708 struct nmk_gpio_chip *nmk_chip; 709 struct irq_chip *host_chip = irq_get_chip(irq); 710 unsigned int first_irq; 711 712 chained_irq_enter(host_chip, desc); 713 714 nmk_chip = irq_get_handler_data(irq); 715 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 716 while (status) { 717 int bit = __ffs(status); 718 719 generic_handle_irq(first_irq + bit); 720 status &= ~BIT(bit); 721 } 722 723 chained_irq_exit(host_chip, desc); 724 } 725 726 static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 727 { 728 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); 729 u32 status = readl(nmk_chip->addr + NMK_GPIO_IS); 730 731 __nmk_gpio_irq_handler(irq, desc, status); 732 } 733 734 static void nmk_gpio_secondary_irq_handler(unsigned int irq, 735 struct irq_desc *desc) 736 { 737 struct nmk_gpio_chip *nmk_chip = irq_get_handler_data(irq); 738 u32 status = nmk_chip->get_secondary_status(nmk_chip->bank); 739 740 __nmk_gpio_irq_handler(irq, desc, status); 741 } 742 743 static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) 744 { 745 unsigned int first_irq; 746 int i; 747 748 first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); 749 for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { 750 irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, 751 handle_edge_irq); 752 set_irq_flags(i, IRQF_VALID); 753 irq_set_chip_data(i, nmk_chip); 754 irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); 755 } 756 757 irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); 758 irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); 759 760 if (nmk_chip->secondary_parent_irq >= 0) { 761 irq_set_chained_handler(nmk_chip->secondary_parent_irq, 762 nmk_gpio_secondary_irq_handler); 763 irq_set_handler_data(nmk_chip->secondary_parent_irq, nmk_chip); 764 } 765 766 return 0; 767 } 768 769 /* I/O Functions */ 770 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) 771 { 772 struct nmk_gpio_chip *nmk_chip = 773 container_of(chip, struct nmk_gpio_chip, chip); 774 775 writel(1 << offset, nmk_chip->addr + NMK_GPIO_DIRC); 776 return 0; 777 } 778 779 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned offset) 780 { 781 struct nmk_gpio_chip *nmk_chip = 782 container_of(chip, struct nmk_gpio_chip, chip); 783 u32 bit = 1 << offset; 784 785 return (readl(nmk_chip->addr + NMK_GPIO_DAT) & bit) != 0; 786 } 787 788 static void nmk_gpio_set_output(struct gpio_chip *chip, unsigned offset, 789 int val) 790 { 791 struct nmk_gpio_chip *nmk_chip = 792 container_of(chip, struct nmk_gpio_chip, chip); 793 794 __nmk_gpio_set_output(nmk_chip, offset, val); 795 } 796 797 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned offset, 798 int val) 799 { 800 struct nmk_gpio_chip *nmk_chip = 801 container_of(chip, struct nmk_gpio_chip, chip); 802 803 __nmk_gpio_make_output(nmk_chip, offset, val); 804 805 return 0; 806 } 807 808 static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) 809 { 810 struct nmk_gpio_chip *nmk_chip = 811 container_of(chip, struct nmk_gpio_chip, chip); 812 813 return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; 814 } 815 816 #ifdef CONFIG_DEBUG_FS 817 818 #include <linux/seq_file.h> 819 820 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 821 { 822 int mode; 823 unsigned i; 824 unsigned gpio = chip->base; 825 int is_out; 826 struct nmk_gpio_chip *nmk_chip = 827 container_of(chip, struct nmk_gpio_chip, chip); 828 const char *modes[] = { 829 [NMK_GPIO_ALT_GPIO] = "gpio", 830 [NMK_GPIO_ALT_A] = "altA", 831 [NMK_GPIO_ALT_B] = "altB", 832 [NMK_GPIO_ALT_C] = "altC", 833 }; 834 835 for (i = 0; i < chip->ngpio; i++, gpio++) { 836 const char *label = gpiochip_is_requested(chip, i); 837 bool pull; 838 u32 bit = 1 << i; 839 840 is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; 841 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); 842 mode = nmk_gpio_get_mode(gpio); 843 seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", 844 gpio, label ?: "(none)", 845 is_out ? "out" : "in ", 846 chip->get 847 ? (chip->get(chip, i) ? "hi" : "lo") 848 : "? ", 849 (mode < 0) ? "unknown" : modes[mode], 850 pull ? "pull" : "none"); 851 852 if (label && !is_out) { 853 int irq = gpio_to_irq(gpio); 854 struct irq_desc *desc = irq_to_desc(irq); 855 856 /* This races with request_irq(), set_irq_type(), 857 * and set_irq_wake() ... but those are "rare". 858 */ 859 if (irq >= 0 && desc->action) { 860 char *trigger; 861 u32 bitmask = nmk_gpio_get_bitmask(gpio); 862 863 if (nmk_chip->edge_rising & bitmask) 864 trigger = "edge-rising"; 865 else if (nmk_chip->edge_falling & bitmask) 866 trigger = "edge-falling"; 867 else 868 trigger = "edge-undefined"; 869 870 seq_printf(s, " irq-%d %s%s", 871 irq, trigger, 872 irqd_is_wakeup_set(&desc->irq_data) 873 ? " wakeup" : ""); 874 } 875 } 876 877 seq_printf(s, "\n"); 878 } 879 } 880 881 #else 882 #define nmk_gpio_dbg_show NULL 883 #endif 884 885 /* This structure is replicated for each GPIO block allocated at probe time */ 886 static struct gpio_chip nmk_gpio_template = { 887 .direction_input = nmk_gpio_make_input, 888 .get = nmk_gpio_get_input, 889 .direction_output = nmk_gpio_make_output, 890 .set = nmk_gpio_set_output, 891 .to_irq = nmk_gpio_to_irq, 892 .dbg_show = nmk_gpio_dbg_show, 893 .can_sleep = 0, 894 }; 895 896 /* 897 * Called from the suspend/resume path to only keep the real wakeup interrupts 898 * (those that have had set_irq_wake() called on them) as wakeup interrupts, 899 * and not the rest of the interrupts which we needed to have as wakeups for 900 * cpuidle. 901 * 902 * PM ops are not used since this needs to be done at the end, after all the 903 * other drivers are done with their suspend callbacks. 904 */ 905 void nmk_gpio_wakeups_suspend(void) 906 { 907 int i; 908 909 for (i = 0; i < NUM_BANKS; i++) { 910 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 911 912 if (!chip) 913 break; 914 915 chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); 916 chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); 917 918 writel(chip->rwimsc & chip->real_wake, 919 chip->addr + NMK_GPIO_RWIMSC); 920 writel(chip->fwimsc & chip->real_wake, 921 chip->addr + NMK_GPIO_FWIMSC); 922 923 if (chip->sleepmode) { 924 chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); 925 926 /* 0 -> wakeup enable */ 927 writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); 928 } 929 } 930 } 931 932 void nmk_gpio_wakeups_resume(void) 933 { 934 int i; 935 936 for (i = 0; i < NUM_BANKS; i++) { 937 struct nmk_gpio_chip *chip = nmk_gpio_chips[i]; 938 939 if (!chip) 940 break; 941 942 writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); 943 writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); 944 945 if (chip->sleepmode) 946 writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); 947 } 948 } 949 950 /* 951 * Read the pull up/pull down status. 952 * A bit set in 'pull_up' means that pull up 953 * is selected if pull is enabled in PDIS register. 954 * Note: only pull up/down set via this driver can 955 * be detected due to HW limitations. 956 */ 957 void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) 958 { 959 if (gpio_bank < NUM_BANKS) { 960 struct nmk_gpio_chip *chip = nmk_gpio_chips[gpio_bank]; 961 962 if (!chip) 963 return; 964 965 *pull_up = chip->pull_up; 966 } 967 } 968 969 static int __devinit nmk_gpio_probe(struct platform_device *dev) 970 { 971 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 972 struct nmk_gpio_chip *nmk_chip; 973 struct gpio_chip *chip; 974 struct resource *res; 975 struct clk *clk; 976 int secondary_irq; 977 int irq; 978 int ret; 979 980 if (!pdata) 981 return -ENODEV; 982 983 res = platform_get_resource(dev, IORESOURCE_MEM, 0); 984 if (!res) { 985 ret = -ENOENT; 986 goto out; 987 } 988 989 irq = platform_get_irq(dev, 0); 990 if (irq < 0) { 991 ret = irq; 992 goto out; 993 } 994 995 secondary_irq = platform_get_irq(dev, 1); 996 if (secondary_irq >= 0 && !pdata->get_secondary_status) { 997 ret = -EINVAL; 998 goto out; 999 } 1000 1001 if (request_mem_region(res->start, resource_size(res), 1002 dev_name(&dev->dev)) == NULL) { 1003 ret = -EBUSY; 1004 goto out; 1005 } 1006 1007 clk = clk_get(&dev->dev, NULL); 1008 if (IS_ERR(clk)) { 1009 ret = PTR_ERR(clk); 1010 goto out_release; 1011 } 1012 1013 clk_enable(clk); 1014 1015 nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); 1016 if (!nmk_chip) { 1017 ret = -ENOMEM; 1018 goto out_clk; 1019 } 1020 /* 1021 * The virt address in nmk_chip->addr is in the nomadik register space, 1022 * so we can simply convert the resource address, without remapping 1023 */ 1024 nmk_chip->bank = dev->id; 1025 nmk_chip->clk = clk; 1026 nmk_chip->addr = io_p2v(res->start); 1027 nmk_chip->chip = nmk_gpio_template; 1028 nmk_chip->parent_irq = irq; 1029 nmk_chip->secondary_parent_irq = secondary_irq; 1030 nmk_chip->get_secondary_status = pdata->get_secondary_status; 1031 nmk_chip->set_ioforce = pdata->set_ioforce; 1032 nmk_chip->sleepmode = pdata->supports_sleepmode; 1033 spin_lock_init(&nmk_chip->lock); 1034 1035 chip = &nmk_chip->chip; 1036 chip->base = pdata->first_gpio; 1037 chip->ngpio = pdata->num_gpio; 1038 chip->label = pdata->name ?: dev_name(&dev->dev); 1039 chip->dev = &dev->dev; 1040 chip->owner = THIS_MODULE; 1041 1042 ret = gpiochip_add(&nmk_chip->chip); 1043 if (ret) 1044 goto out_free; 1045 1046 BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); 1047 1048 nmk_gpio_chips[nmk_chip->bank] = nmk_chip; 1049 platform_set_drvdata(dev, nmk_chip); 1050 1051 nmk_gpio_init_irq(nmk_chip); 1052 1053 dev_info(&dev->dev, "Bits %i-%i at address %p\n", 1054 nmk_chip->chip.base, nmk_chip->chip.base+31, nmk_chip->addr); 1055 return 0; 1056 1057 out_free: 1058 kfree(nmk_chip); 1059 out_clk: 1060 clk_disable(clk); 1061 clk_put(clk); 1062 out_release: 1063 release_mem_region(res->start, resource_size(res)); 1064 out: 1065 dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, 1066 pdata->first_gpio, pdata->first_gpio+31); 1067 return ret; 1068 } 1069 1070 static struct platform_driver nmk_gpio_driver = { 1071 .driver = { 1072 .owner = THIS_MODULE, 1073 .name = "gpio", 1074 }, 1075 .probe = nmk_gpio_probe, 1076 }; 1077 1078 static int __init nmk_gpio_init(void) 1079 { 1080 return platform_driver_register(&nmk_gpio_driver); 1081 } 1082 1083 core_initcall(nmk_gpio_init); 1084 1085 MODULE_AUTHOR("Prafulla WADASKAR and Alessandro Rubini"); 1086 MODULE_DESCRIPTION("Nomadik GPIO Driver"); 1087 MODULE_LICENSE("GPL"); 1088