1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for the IP block found in the Nomadik SoC; it is an AMBA device, 4 * managing 32 pins with alternate functions. It can also handle the STA2X11 5 * block from ST. 6 * 7 * The GPIO chips are shared with pinctrl-nomadik if used; it needs access for 8 * pinmuxing functionality and others. 9 * 10 * This driver also handles the mobileye,eyeq5-gpio compatible. It is an STA2X11 11 * but with only data, direction and interrupts register active. We want to 12 * avoid touching SLPM, RWIMSC, FWIMSC, AFSLA and AFSLB registers; that is, 13 * wake and alternate function registers. It is NOT compatible with 14 * pinctrl-nomadik. 15 * 16 * Copyright (C) 2008,2009 STMicroelectronics 17 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 18 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 19 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org> 20 */ 21 #include <linux/cleanup.h> 22 #include <linux/clk.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/gpio/driver.h> 25 #include <linux/interrupt.h> 26 #include <linux/kernel.h> 27 #include <linux/pinctrl/pinctrl.h> 28 #include <linux/platform_device.h> 29 #include <linux/property.h> 30 #include <linux/reset.h> 31 #include <linux/seq_file.h> 32 #include <linux/slab.h> 33 #include <linux/string_choices.h> 34 #include <linux/types.h> 35 36 #include <linux/gpio/gpio-nomadik.h> 37 38 #ifndef CONFIG_PINCTRL_NOMADIK 39 static DEFINE_SPINLOCK(nmk_gpio_slpm_lock); 40 #endif 41 42 void __nmk_gpio_set_slpm(struct nmk_gpio_chip *nmk_chip, unsigned int offset, 43 enum nmk_gpio_slpm mode) 44 { 45 u32 slpm; 46 47 /* We should NOT have been called. */ 48 if (WARN_ON(nmk_chip->is_mobileye_soc)) 49 return; 50 51 slpm = readl(nmk_chip->addr + NMK_GPIO_SLPC); 52 if (mode == NMK_GPIO_SLPM_NOCHANGE) 53 slpm |= BIT(offset); 54 else 55 slpm &= ~BIT(offset); 56 writel(slpm, nmk_chip->addr + NMK_GPIO_SLPC); 57 } 58 59 static void __nmk_gpio_set_output(struct nmk_gpio_chip *nmk_chip, 60 unsigned int offset, int val) 61 { 62 if (val) 63 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATS); 64 else 65 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DATC); 66 } 67 68 void __nmk_gpio_make_output(struct nmk_gpio_chip *nmk_chip, 69 unsigned int offset, int val) 70 { 71 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRS); 72 __nmk_gpio_set_output(nmk_chip, offset, val); 73 } 74 75 /* IRQ functions */ 76 77 static void nmk_gpio_irq_ack(struct irq_data *d) 78 { 79 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 80 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 81 82 clk_enable(nmk_chip->clk); 83 writel(BIT(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); 84 clk_disable(nmk_chip->clk); 85 } 86 87 enum nmk_gpio_irq_type { 88 NORMAL, 89 WAKE, 90 }; 91 92 static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, 93 int offset, enum nmk_gpio_irq_type which, 94 bool enable) 95 { 96 u32 *rimscval; 97 u32 *fimscval; 98 u32 rimscreg; 99 u32 fimscreg; 100 101 if (which == NORMAL) { 102 rimscreg = NMK_GPIO_RIMSC; 103 fimscreg = NMK_GPIO_FIMSC; 104 rimscval = &nmk_chip->rimsc; 105 fimscval = &nmk_chip->fimsc; 106 } else { 107 /* We should NOT have been called. */ 108 if (WARN_ON(nmk_chip->is_mobileye_soc)) 109 return; 110 rimscreg = NMK_GPIO_RWIMSC; 111 fimscreg = NMK_GPIO_FWIMSC; 112 rimscval = &nmk_chip->rwimsc; 113 fimscval = &nmk_chip->fwimsc; 114 } 115 116 /* we must individually set/clear the two edges */ 117 if (nmk_chip->edge_rising & BIT(offset)) { 118 if (enable) 119 *rimscval |= BIT(offset); 120 else 121 *rimscval &= ~BIT(offset); 122 writel(*rimscval, nmk_chip->addr + rimscreg); 123 } 124 if (nmk_chip->edge_falling & BIT(offset)) { 125 if (enable) 126 *fimscval |= BIT(offset); 127 else 128 *fimscval &= ~BIT(offset); 129 writel(*fimscval, nmk_chip->addr + fimscreg); 130 } 131 } 132 133 static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, 134 int offset, bool on) 135 { 136 /* We should NOT have been called. */ 137 if (WARN_ON(nmk_chip->is_mobileye_soc)) 138 return; 139 140 /* 141 * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is 142 * disabled, since setting SLPM to 1 increases power consumption, and 143 * wakeup is anyhow controlled by the RIMSC and FIMSC registers. 144 */ 145 if (nmk_chip->sleepmode && on) { 146 __nmk_gpio_set_slpm(nmk_chip, offset, 147 NMK_GPIO_SLPM_WAKEUP_ENABLE); 148 } 149 150 __nmk_gpio_irq_modify(nmk_chip, offset, WAKE, on); 151 } 152 153 static void nmk_gpio_irq_maskunmask(struct nmk_gpio_chip *nmk_chip, 154 struct irq_data *d, bool enable) 155 { 156 unsigned long flags; 157 158 clk_enable(nmk_chip->clk); 159 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 160 spin_lock(&nmk_chip->lock); 161 162 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); 163 164 if (!nmk_chip->is_mobileye_soc && !(nmk_chip->real_wake & BIT(d->hwirq))) 165 __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); 166 167 spin_unlock(&nmk_chip->lock); 168 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 169 clk_disable(nmk_chip->clk); 170 } 171 172 static void nmk_gpio_irq_mask(struct irq_data *d) 173 { 174 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 175 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 176 177 nmk_gpio_irq_maskunmask(nmk_chip, d, false); 178 gpiochip_disable_irq(gc, irqd_to_hwirq(d)); 179 } 180 181 static void nmk_gpio_irq_unmask(struct irq_data *d) 182 { 183 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 184 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 185 186 gpiochip_enable_irq(gc, irqd_to_hwirq(d)); 187 nmk_gpio_irq_maskunmask(nmk_chip, d, true); 188 } 189 190 static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) 191 { 192 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 193 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 194 unsigned long flags; 195 196 /* Handler is registered in all cases. */ 197 if (nmk_chip->is_mobileye_soc) 198 return -ENXIO; 199 200 clk_enable(nmk_chip->clk); 201 spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); 202 spin_lock(&nmk_chip->lock); 203 204 if (irqd_irq_disabled(d)) 205 __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); 206 207 if (on) 208 nmk_chip->real_wake |= BIT(d->hwirq); 209 else 210 nmk_chip->real_wake &= ~BIT(d->hwirq); 211 212 spin_unlock(&nmk_chip->lock); 213 spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); 214 clk_disable(nmk_chip->clk); 215 216 return 0; 217 } 218 219 static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) 220 { 221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 222 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 223 bool enabled = !irqd_irq_disabled(d); 224 bool wake = irqd_is_wakeup_set(d); 225 unsigned long flags; 226 227 if (type & IRQ_TYPE_LEVEL_HIGH) 228 return -EINVAL; 229 if (type & IRQ_TYPE_LEVEL_LOW) 230 return -EINVAL; 231 232 clk_enable(nmk_chip->clk); 233 spin_lock_irqsave(&nmk_chip->lock, flags); 234 235 if (enabled) 236 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); 237 238 if (!nmk_chip->is_mobileye_soc && (enabled || wake)) 239 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); 240 241 nmk_chip->edge_rising &= ~BIT(d->hwirq); 242 if (type & IRQ_TYPE_EDGE_RISING) 243 nmk_chip->edge_rising |= BIT(d->hwirq); 244 245 nmk_chip->edge_falling &= ~BIT(d->hwirq); 246 if (type & IRQ_TYPE_EDGE_FALLING) 247 nmk_chip->edge_falling |= BIT(d->hwirq); 248 249 if (enabled) 250 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); 251 252 if (!nmk_chip->is_mobileye_soc && (enabled || wake)) 253 __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); 254 255 spin_unlock_irqrestore(&nmk_chip->lock, flags); 256 clk_disable(nmk_chip->clk); 257 258 return 0; 259 } 260 261 static unsigned int nmk_gpio_irq_startup(struct irq_data *d) 262 { 263 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 264 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 265 266 clk_enable(nmk_chip->clk); 267 nmk_gpio_irq_unmask(d); 268 return 0; 269 } 270 271 static void nmk_gpio_irq_shutdown(struct irq_data *d) 272 { 273 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 274 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 275 276 nmk_gpio_irq_mask(d); 277 clk_disable(nmk_chip->clk); 278 } 279 280 static irqreturn_t nmk_gpio_irq_handler(int irq, void *dev_id) 281 { 282 struct nmk_gpio_chip *nmk_chip = dev_id; 283 struct gpio_chip *chip = &nmk_chip->chip; 284 unsigned long mask = GENMASK(chip->ngpio - 1, 0); 285 unsigned long status; 286 int bit; 287 288 clk_enable(nmk_chip->clk); 289 290 status = readl(nmk_chip->addr + NMK_GPIO_IS); 291 292 /* Ensure we cannot leave pending bits; this should never occur. */ 293 if (unlikely(status & ~mask)) 294 writel(status & ~mask, nmk_chip->addr + NMK_GPIO_IC); 295 296 clk_disable(nmk_chip->clk); 297 298 for_each_set_bit(bit, &status, chip->ngpio) 299 generic_handle_domain_irq_safe(chip->irq.domain, bit); 300 301 return IRQ_RETVAL((status & mask) != 0); 302 } 303 304 /* I/O Functions */ 305 306 static int nmk_gpio_get_dir(struct gpio_chip *chip, unsigned int offset) 307 { 308 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 309 int dir; 310 311 clk_enable(nmk_chip->clk); 312 313 dir = readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset); 314 315 clk_disable(nmk_chip->clk); 316 317 if (dir) 318 return GPIO_LINE_DIRECTION_OUT; 319 320 return GPIO_LINE_DIRECTION_IN; 321 } 322 323 static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned int offset) 324 { 325 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 326 327 clk_enable(nmk_chip->clk); 328 329 writel(BIT(offset), nmk_chip->addr + NMK_GPIO_DIRC); 330 331 clk_disable(nmk_chip->clk); 332 333 return 0; 334 } 335 336 static int nmk_gpio_get_input(struct gpio_chip *chip, unsigned int offset) 337 { 338 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 339 int value; 340 341 clk_enable(nmk_chip->clk); 342 343 value = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 344 345 clk_disable(nmk_chip->clk); 346 347 return value; 348 } 349 350 static int nmk_gpio_set_output(struct gpio_chip *chip, unsigned int offset, 351 int val) 352 { 353 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 354 355 clk_enable(nmk_chip->clk); 356 357 __nmk_gpio_set_output(nmk_chip, offset, val); 358 359 clk_disable(nmk_chip->clk); 360 361 return 0; 362 } 363 364 static int nmk_gpio_make_output(struct gpio_chip *chip, unsigned int offset, 365 int val) 366 { 367 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 368 369 clk_enable(nmk_chip->clk); 370 371 __nmk_gpio_make_output(nmk_chip, offset, val); 372 373 clk_disable(nmk_chip->clk); 374 375 return 0; 376 } 377 378 #ifdef CONFIG_DEBUG_FS 379 380 static int nmk_gpio_get_mode(struct nmk_gpio_chip *nmk_chip, int offset) 381 { 382 u32 afunc, bfunc; 383 384 /* We don't support modes. */ 385 if (nmk_chip->is_mobileye_soc) 386 return NMK_GPIO_ALT_GPIO; 387 388 clk_enable(nmk_chip->clk); 389 390 afunc = readl(nmk_chip->addr + NMK_GPIO_AFSLA) & BIT(offset); 391 bfunc = readl(nmk_chip->addr + NMK_GPIO_AFSLB) & BIT(offset); 392 393 clk_disable(nmk_chip->clk); 394 395 return (afunc ? NMK_GPIO_ALT_A : 0) | (bfunc ? NMK_GPIO_ALT_B : 0); 396 } 397 398 void nmk_gpio_dbg_show_one(struct seq_file *s, struct pinctrl_dev *pctldev, 399 struct gpio_chip *chip, unsigned int offset) 400 { 401 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(chip); 402 #ifdef CONFIG_PINCTRL_NOMADIK 403 struct gpio_desc *desc; 404 #endif 405 int mode; 406 bool is_out; 407 bool data_out; 408 bool pull; 409 static const char * const modes[] = { 410 [NMK_GPIO_ALT_GPIO] = "gpio", 411 [NMK_GPIO_ALT_A] = "altA", 412 [NMK_GPIO_ALT_B] = "altB", 413 [NMK_GPIO_ALT_C] = "altC", 414 [NMK_GPIO_ALT_C + 1] = "altC1", 415 [NMK_GPIO_ALT_C + 2] = "altC2", 416 [NMK_GPIO_ALT_C + 3] = "altC3", 417 [NMK_GPIO_ALT_C + 4] = "altC4", 418 }; 419 420 char *label = gpiochip_dup_line_label(chip, offset); 421 if (IS_ERR(label)) 422 return; 423 424 clk_enable(nmk_chip->clk); 425 is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & BIT(offset)); 426 pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & BIT(offset)); 427 data_out = !!(readl(nmk_chip->addr + NMK_GPIO_DAT) & BIT(offset)); 428 mode = nmk_gpio_get_mode(nmk_chip, offset); 429 #ifdef CONFIG_PINCTRL_NOMADIK 430 if (mode == NMK_GPIO_ALT_C && pctldev) { 431 desc = gpio_device_get_desc(chip->gpiodev, offset); 432 if (IS_ERR(desc)) 433 return; 434 435 mode = nmk_prcm_gpiocr_get_mode(pctldev, desc_to_gpio(desc)); 436 } 437 #endif 438 439 if (is_out) { 440 seq_printf(s, " gpio-%-3d (%-20.20s) out %s %s", 441 offset, label ?: "(none)", str_hi_lo(data_out), 442 (mode < 0) ? "unknown" : modes[mode]); 443 } else { 444 int irq = chip->to_irq(chip, offset); 445 const int pullidx = pull ? 1 : 0; 446 int val; 447 static const char * const pulls[] = { 448 "none ", 449 "pull enabled", 450 }; 451 452 seq_printf(s, " gpio-%-3d (%-20.20s) in %s %s", 453 offset, label ?: "(none)", pulls[pullidx], 454 (mode < 0) ? "unknown" : modes[mode]); 455 456 val = nmk_gpio_get_input(chip, offset); 457 seq_printf(s, " VAL %d", val); 458 459 /* 460 * This races with request_irq(), set_irq_type(), 461 * and set_irq_wake() ... but those are "rare". 462 */ 463 if (irq > 0 && irq_has_action(irq)) { 464 char *trigger; 465 bool wake; 466 467 if (nmk_chip->edge_rising & BIT(offset)) 468 trigger = "edge-rising"; 469 else if (nmk_chip->edge_falling & BIT(offset)) 470 trigger = "edge-falling"; 471 else 472 trigger = "edge-undefined"; 473 474 wake = !!(nmk_chip->real_wake & BIT(offset)); 475 476 seq_printf(s, " irq-%d %s%s", 477 irq, trigger, wake ? " wakeup" : ""); 478 } 479 } 480 clk_disable(nmk_chip->clk); 481 } 482 483 static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 484 { 485 unsigned int i; 486 487 for (i = 0; i < chip->ngpio; i++) { 488 nmk_gpio_dbg_show_one(s, NULL, chip, i); 489 seq_puts(s, "\n"); 490 } 491 } 492 493 #else 494 495 #define nmk_gpio_dbg_show NULL 496 497 #endif 498 499 /* 500 * We will allocate memory for the state container using devm* allocators 501 * binding to the first device reaching this point, it doesn't matter if 502 * it is the pin controller or GPIO driver. However we need to use the right 503 * platform device when looking up resources so pay attention to pdev. 504 */ 505 struct nmk_gpio_chip *nmk_gpio_populate_chip(struct fwnode_handle *fwnode, 506 struct platform_device *pdev) 507 { 508 struct nmk_gpio_chip *nmk_chip; 509 struct platform_device *gpio_pdev; 510 struct device *dev = &pdev->dev; 511 struct reset_control *reset; 512 struct device *gpio_dev; 513 struct gpio_chip *chip; 514 struct resource *res; 515 struct clk *clk; 516 void __iomem *base; 517 u32 id, ngpio; 518 int ret; 519 520 gpio_dev = bus_find_device_by_fwnode(&platform_bus_type, fwnode); 521 if (!gpio_dev) { 522 ret = -ENODEV; 523 dev_err_probe(dev, ret, "populate \"%pfwP\": device not found\n", fwnode); 524 return ERR_PTR(ret); 525 } 526 gpio_pdev = to_platform_device(gpio_dev); 527 528 if (device_property_read_u32(gpio_dev, "gpio-bank", &id)) { 529 ret = -EINVAL; 530 dev_err_probe(dev, ret, "populate: gpio-bank property not found\n"); 531 goto err_put_pdev; 532 } 533 534 #ifdef CONFIG_PINCTRL_NOMADIK 535 if (id >= ARRAY_SIZE(nmk_gpio_chips)) { 536 ret = -EINVAL; 537 dev_err_probe(dev, ret, "populate: invalid id: %u\n", id); 538 goto err_put_pdev; 539 } 540 /* Already populated? */ 541 nmk_chip = nmk_gpio_chips[id]; 542 if (nmk_chip) { 543 platform_device_put(gpio_pdev); 544 return nmk_chip; 545 } 546 #endif 547 548 nmk_chip = devm_kzalloc(dev, sizeof(*nmk_chip), GFP_KERNEL); 549 if (!nmk_chip) { 550 ret = -ENOMEM; 551 goto err_put_pdev; 552 } 553 554 if (device_property_read_u32(gpio_dev, "ngpios", &ngpio)) { 555 ngpio = NMK_GPIO_PER_CHIP; 556 dev_dbg(dev, "populate: using default ngpio (%u)\n", ngpio); 557 } 558 559 nmk_chip->is_mobileye_soc = device_is_compatible(gpio_dev, 560 "mobileye,eyeq5-gpio"); 561 nmk_chip->bank = id; 562 chip = &nmk_chip->chip; 563 chip->base = -1; 564 chip->ngpio = ngpio; 565 chip->label = dev_name(gpio_dev); 566 chip->parent = gpio_dev; 567 568 /* NOTE: different devices! No devm_platform_ioremap_resource() here! */ 569 res = platform_get_resource(gpio_pdev, IORESOURCE_MEM, 0); 570 base = devm_ioremap_resource(dev, res); 571 if (IS_ERR(base)) { 572 ret = PTR_ERR(base); 573 goto err_put_pdev; 574 } 575 nmk_chip->addr = base; 576 577 /* NOTE: do not use devm_ here! */ 578 clk = clk_get_optional(gpio_dev, NULL); 579 if (IS_ERR(clk)) { 580 ret = PTR_ERR(clk); 581 dev_err_probe(dev, ret, "failed getting clock\n"); 582 goto err_put_pdev; 583 } 584 clk_prepare(clk); 585 nmk_chip->clk = clk; 586 587 /* NOTE: do not use devm_ here! */ 588 reset = reset_control_get_optional_shared(gpio_dev, NULL); 589 if (IS_ERR(reset)) { 590 ret = PTR_ERR(reset); 591 dev_err_probe(dev, ret, "failed getting reset control\n"); 592 goto err_unprepare_clk; 593 } 594 595 /* 596 * Reset might be shared and asserts/deasserts calls are unbalanced. We 597 * only support sharing this reset with other gpio-nomadik devices that 598 * use this reset to ensure deassertion at probe. 599 */ 600 ret = reset_control_deassert(reset); 601 if (ret) { 602 dev_err_probe(dev, ret, "failed reset deassert\n"); 603 goto err_put_reset; 604 } 605 606 #ifdef CONFIG_PINCTRL_NOMADIK 607 nmk_gpio_chips[id] = nmk_chip; 608 #endif 609 return nmk_chip; 610 611 err_put_reset: 612 reset_control_put(reset); 613 err_unprepare_clk: 614 clk_unprepare(clk); 615 clk_put(clk); 616 err_put_pdev: 617 platform_device_put(gpio_pdev); 618 return ERR_PTR(ret); 619 } 620 621 static void nmk_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 622 { 623 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 624 struct nmk_gpio_chip *nmk_chip = gpiochip_get_data(gc); 625 626 seq_printf(p, "nmk%u-%u-%u", nmk_chip->bank, 627 gc->base, gc->base + gc->ngpio - 1); 628 } 629 630 static const struct irq_chip nmk_irq_chip = { 631 .irq_ack = nmk_gpio_irq_ack, 632 .irq_mask = nmk_gpio_irq_mask, 633 .irq_unmask = nmk_gpio_irq_unmask, 634 .irq_set_type = nmk_gpio_irq_set_type, 635 .irq_set_wake = nmk_gpio_irq_set_wake, 636 .irq_startup = nmk_gpio_irq_startup, 637 .irq_shutdown = nmk_gpio_irq_shutdown, 638 .irq_print_chip = nmk_gpio_irq_print_chip, 639 .flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_IMMUTABLE, 640 GPIOCHIP_IRQ_RESOURCE_HELPERS, 641 }; 642 643 static int nmk_gpio_probe(struct platform_device *pdev) 644 { 645 struct device *dev = &pdev->dev; 646 struct nmk_gpio_chip *nmk_chip; 647 struct gpio_irq_chip *girq; 648 bool supports_sleepmode; 649 struct gpio_chip *chip; 650 int irq; 651 int ret; 652 653 nmk_chip = nmk_gpio_populate_chip(dev_fwnode(dev), pdev); 654 if (IS_ERR(nmk_chip)) 655 return PTR_ERR(nmk_chip); 656 657 supports_sleepmode = 658 device_property_read_bool(dev, "st,supports-sleepmode"); 659 660 /* Correct platform device ID */ 661 pdev->id = nmk_chip->bank; 662 663 irq = platform_get_irq(pdev, 0); 664 if (irq < 0) 665 return irq; 666 667 /* 668 * The virt address in nmk_chip->addr is in the nomadik register space, 669 * so we can simply convert the resource address, without remapping 670 */ 671 nmk_chip->sleepmode = supports_sleepmode; 672 spin_lock_init(&nmk_chip->lock); 673 674 chip = &nmk_chip->chip; 675 chip->parent = dev; 676 chip->request = gpiochip_generic_request; 677 chip->free = gpiochip_generic_free; 678 chip->get_direction = nmk_gpio_get_dir; 679 chip->direction_input = nmk_gpio_make_input; 680 chip->get = nmk_gpio_get_input; 681 chip->direction_output = nmk_gpio_make_output; 682 chip->set = nmk_gpio_set_output; 683 chip->dbg_show = nmk_gpio_dbg_show; 684 chip->can_sleep = false; 685 chip->owner = THIS_MODULE; 686 687 girq = &chip->irq; 688 gpio_irq_chip_set_chip(girq, &nmk_irq_chip); 689 girq->parent_handler = NULL; 690 girq->num_parents = 0; 691 girq->parents = NULL; 692 girq->default_type = IRQ_TYPE_NONE; 693 girq->handler = handle_edge_irq; 694 695 ret = devm_request_irq(dev, irq, nmk_gpio_irq_handler, IRQF_SHARED, 696 dev_name(dev), nmk_chip); 697 if (ret) { 698 dev_err_probe(dev, ret, "failed requesting IRQ\n"); 699 return ret; 700 } 701 702 if (!nmk_chip->is_mobileye_soc) { 703 clk_enable(nmk_chip->clk); 704 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 705 clk_disable(nmk_chip->clk); 706 } 707 708 ret = gpiochip_add_data(chip, nmk_chip); 709 if (ret) 710 return ret; 711 712 platform_set_drvdata(pdev, nmk_chip); 713 714 return 0; 715 } 716 717 static const struct of_device_id nmk_gpio_match[] = { 718 { .compatible = "st,nomadik-gpio", }, 719 { .compatible = "mobileye,eyeq5-gpio", }, 720 {} 721 }; 722 723 static struct platform_driver nmk_gpio_driver = { 724 .driver = { 725 .name = "nomadik-gpio", 726 .of_match_table = nmk_gpio_match, 727 .suppress_bind_attrs = true, 728 }, 729 .probe = nmk_gpio_probe, 730 }; 731 732 static int __init nmk_gpio_init(void) 733 { 734 return platform_driver_register(&nmk_gpio_driver); 735 } 736 subsys_initcall(nmk_gpio_init); 737