1 /* 2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de 4 * 5 * Based on code from Freescale, 6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License 10 * as published by the Free Software Foundation; either version 2 11 * of the License, or (at your option) any later version. 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 * You should have received a copy of the GNU General Public License 18 * along with this program; if not, write to the Free Software 19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, 20 * MA 02110-1301, USA. 21 */ 22 23 #include <linux/init.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/gpio.h> 28 #include <linux/platform_device.h> 29 #include <linux/slab.h> 30 #include <linux/basic_mmio_gpio.h> 31 #include <mach/mxs.h> 32 33 #define MXS_SET 0x4 34 #define MXS_CLR 0x8 35 36 #define PINCTRL_DOUT(n) ((cpu_is_mx23() ? 0x0500 : 0x0700) + (n) * 0x10) 37 #define PINCTRL_DIN(n) ((cpu_is_mx23() ? 0x0600 : 0x0900) + (n) * 0x10) 38 #define PINCTRL_DOE(n) ((cpu_is_mx23() ? 0x0700 : 0x0b00) + (n) * 0x10) 39 #define PINCTRL_PIN2IRQ(n) ((cpu_is_mx23() ? 0x0800 : 0x1000) + (n) * 0x10) 40 #define PINCTRL_IRQEN(n) ((cpu_is_mx23() ? 0x0900 : 0x1100) + (n) * 0x10) 41 #define PINCTRL_IRQLEV(n) ((cpu_is_mx23() ? 0x0a00 : 0x1200) + (n) * 0x10) 42 #define PINCTRL_IRQPOL(n) ((cpu_is_mx23() ? 0x0b00 : 0x1300) + (n) * 0x10) 43 #define PINCTRL_IRQSTAT(n) ((cpu_is_mx23() ? 0x0c00 : 0x1400) + (n) * 0x10) 44 45 #define GPIO_INT_FALL_EDGE 0x0 46 #define GPIO_INT_LOW_LEV 0x1 47 #define GPIO_INT_RISE_EDGE 0x2 48 #define GPIO_INT_HIGH_LEV 0x3 49 #define GPIO_INT_LEV_MASK (1 << 0) 50 #define GPIO_INT_POL_MASK (1 << 1) 51 52 struct mxs_gpio_port { 53 void __iomem *base; 54 int id; 55 int irq; 56 int virtual_irq_start; 57 struct bgpio_chip bgc; 58 }; 59 60 /* Note: This driver assumes 32 GPIOs are handled in one register */ 61 62 static void clear_gpio_irqstatus(struct mxs_gpio_port *port, u32 index) 63 { 64 writel(1 << index, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR); 65 } 66 67 static void set_gpio_irqenable(struct mxs_gpio_port *port, u32 index, 68 int enable) 69 { 70 if (enable) { 71 writel(1 << index, 72 port->base + PINCTRL_IRQEN(port->id) + MXS_SET); 73 writel(1 << index, 74 port->base + PINCTRL_PIN2IRQ(port->id) + MXS_SET); 75 } else { 76 writel(1 << index, 77 port->base + PINCTRL_IRQEN(port->id) + MXS_CLR); 78 } 79 } 80 81 static void mxs_gpio_ack_irq(struct irq_data *d) 82 { 83 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d); 84 u32 gpio = irq_to_gpio(d->irq); 85 clear_gpio_irqstatus(port, gpio & 0x1f); 86 } 87 88 static void mxs_gpio_mask_irq(struct irq_data *d) 89 { 90 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d); 91 u32 gpio = irq_to_gpio(d->irq); 92 set_gpio_irqenable(port, gpio & 0x1f, 0); 93 } 94 95 static void mxs_gpio_unmask_irq(struct irq_data *d) 96 { 97 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d); 98 u32 gpio = irq_to_gpio(d->irq); 99 set_gpio_irqenable(port, gpio & 0x1f, 1); 100 } 101 102 static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) 103 { 104 u32 gpio = irq_to_gpio(d->irq); 105 u32 pin_mask = 1 << (gpio & 31); 106 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d); 107 void __iomem *pin_addr; 108 int edge; 109 110 switch (type) { 111 case IRQ_TYPE_EDGE_RISING: 112 edge = GPIO_INT_RISE_EDGE; 113 break; 114 case IRQ_TYPE_EDGE_FALLING: 115 edge = GPIO_INT_FALL_EDGE; 116 break; 117 case IRQ_TYPE_LEVEL_LOW: 118 edge = GPIO_INT_LOW_LEV; 119 break; 120 case IRQ_TYPE_LEVEL_HIGH: 121 edge = GPIO_INT_HIGH_LEV; 122 break; 123 default: 124 return -EINVAL; 125 } 126 127 /* set level or edge */ 128 pin_addr = port->base + PINCTRL_IRQLEV(port->id); 129 if (edge & GPIO_INT_LEV_MASK) 130 writel(pin_mask, pin_addr + MXS_SET); 131 else 132 writel(pin_mask, pin_addr + MXS_CLR); 133 134 /* set polarity */ 135 pin_addr = port->base + PINCTRL_IRQPOL(port->id); 136 if (edge & GPIO_INT_POL_MASK) 137 writel(pin_mask, pin_addr + MXS_SET); 138 else 139 writel(pin_mask, pin_addr + MXS_CLR); 140 141 clear_gpio_irqstatus(port, gpio & 0x1f); 142 143 return 0; 144 } 145 146 /* MXS has one interrupt *per* gpio port */ 147 static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) 148 { 149 u32 irq_stat; 150 struct mxs_gpio_port *port = irq_get_handler_data(irq); 151 u32 gpio_irq_no_base = port->virtual_irq_start; 152 153 desc->irq_data.chip->irq_ack(&desc->irq_data); 154 155 irq_stat = readl(port->base + PINCTRL_IRQSTAT(port->id)) & 156 readl(port->base + PINCTRL_IRQEN(port->id)); 157 158 while (irq_stat != 0) { 159 int irqoffset = fls(irq_stat) - 1; 160 generic_handle_irq(gpio_irq_no_base + irqoffset); 161 irq_stat &= ~(1 << irqoffset); 162 } 163 } 164 165 /* 166 * Set interrupt number "irq" in the GPIO as a wake-up source. 167 * While system is running, all registered GPIO interrupts need to have 168 * wake-up enabled. When system is suspended, only selected GPIO interrupts 169 * need to have wake-up enabled. 170 * @param irq interrupt source number 171 * @param enable enable as wake-up if equal to non-zero 172 * @return This function returns 0 on success. 173 */ 174 static int mxs_gpio_set_wake_irq(struct irq_data *d, unsigned int enable) 175 { 176 struct mxs_gpio_port *port = irq_data_get_irq_chip_data(d); 177 178 if (enable) 179 enable_irq_wake(port->irq); 180 else 181 disable_irq_wake(port->irq); 182 183 return 0; 184 } 185 186 static struct irq_chip gpio_irq_chip = { 187 .name = "mxs gpio", 188 .irq_ack = mxs_gpio_ack_irq, 189 .irq_mask = mxs_gpio_mask_irq, 190 .irq_unmask = mxs_gpio_unmask_irq, 191 .irq_set_type = mxs_gpio_set_irq_type, 192 .irq_set_wake = mxs_gpio_set_wake_irq, 193 }; 194 195 static int mxs_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 196 { 197 struct bgpio_chip *bgc = to_bgpio_chip(gc); 198 struct mxs_gpio_port *port = 199 container_of(bgc, struct mxs_gpio_port, bgc); 200 201 return port->virtual_irq_start + offset; 202 } 203 204 static int __devinit mxs_gpio_probe(struct platform_device *pdev) 205 { 206 static void __iomem *base; 207 struct mxs_gpio_port *port; 208 struct resource *iores = NULL; 209 int err, i; 210 211 port = kzalloc(sizeof(struct mxs_gpio_port), GFP_KERNEL); 212 if (!port) 213 return -ENOMEM; 214 215 port->id = pdev->id; 216 port->virtual_irq_start = MXS_GPIO_IRQ_START + port->id * 32; 217 218 /* 219 * map memory region only once, as all the gpio ports 220 * share the same one 221 */ 222 if (!base) { 223 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 224 if (!iores) { 225 err = -ENODEV; 226 goto out_kfree; 227 } 228 229 if (!request_mem_region(iores->start, resource_size(iores), 230 pdev->name)) { 231 err = -EBUSY; 232 goto out_kfree; 233 } 234 235 base = ioremap(iores->start, resource_size(iores)); 236 if (!base) { 237 err = -ENOMEM; 238 goto out_release_mem; 239 } 240 } 241 port->base = base; 242 243 port->irq = platform_get_irq(pdev, 0); 244 if (port->irq < 0) { 245 err = -EINVAL; 246 goto out_iounmap; 247 } 248 249 /* disable the interrupt and clear the status */ 250 writel(0, port->base + PINCTRL_PIN2IRQ(port->id)); 251 writel(0, port->base + PINCTRL_IRQEN(port->id)); 252 253 /* clear address has to be used to clear IRQSTAT bits */ 254 writel(~0U, port->base + PINCTRL_IRQSTAT(port->id) + MXS_CLR); 255 256 for (i = port->virtual_irq_start; 257 i < port->virtual_irq_start + 32; i++) { 258 irq_set_chip_and_handler(i, &gpio_irq_chip, 259 handle_level_irq); 260 set_irq_flags(i, IRQF_VALID); 261 irq_set_chip_data(i, port); 262 } 263 264 /* setup one handler for each entry */ 265 irq_set_chained_handler(port->irq, mxs_gpio_irq_handler); 266 irq_set_handler_data(port->irq, port); 267 268 err = bgpio_init(&port->bgc, &pdev->dev, 4, 269 port->base + PINCTRL_DIN(port->id), 270 port->base + PINCTRL_DOUT(port->id), NULL, 271 port->base + PINCTRL_DOE(port->id), NULL, false); 272 if (err) 273 goto out_iounmap; 274 275 port->bgc.gc.to_irq = mxs_gpio_to_irq; 276 port->bgc.gc.base = port->id * 32; 277 278 err = gpiochip_add(&port->bgc.gc); 279 if (err) 280 goto out_bgpio_remove; 281 282 return 0; 283 284 out_bgpio_remove: 285 bgpio_remove(&port->bgc); 286 out_iounmap: 287 if (iores) 288 iounmap(port->base); 289 out_release_mem: 290 if (iores) 291 release_mem_region(iores->start, resource_size(iores)); 292 out_kfree: 293 kfree(port); 294 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 295 return err; 296 } 297 298 static struct platform_driver mxs_gpio_driver = { 299 .driver = { 300 .name = "gpio-mxs", 301 .owner = THIS_MODULE, 302 }, 303 .probe = mxs_gpio_probe, 304 }; 305 306 static int __init mxs_gpio_init(void) 307 { 308 return platform_driver_register(&mxs_gpio_driver); 309 } 310 postcore_initcall(mxs_gpio_init); 311 312 MODULE_AUTHOR("Freescale Semiconductor, " 313 "Daniel Mack <danielncaiaq.de>, " 314 "Juergen Beisert <kernel@pengutronix.de>"); 315 MODULE_DESCRIPTION("Freescale MXS GPIO"); 316 MODULE_LICENSE("GPL"); 317