xref: /linux/drivers/gpio/gpio-mxc.c (revision fada1935590f66dc6784981e0d557ca09013c847)
1 /*
2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
4  *
5  * Based on code from Freescale Semiconductor,
6  * Authors: Daniel Mack, Juergen Beisert.
7  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8  *
9  * This program is free software; you can redistribute it and/or
10  * modify it under the terms of the GNU General Public License
11  * as published by the Free Software Foundation; either version 2
12  * of the License, or (at your option) any later version.
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License
19  * along with this program; if not, write to the Free Software
20  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
21  */
22 
23 #include <linux/err.h>
24 #include <linux/init.h>
25 #include <linux/interrupt.h>
26 #include <linux/io.h>
27 #include <linux/irq.h>
28 #include <linux/irqdomain.h>
29 #include <linux/irqchip/chained_irq.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/gpio/driver.h>
33 /* FIXME: for gpio_get_value() replace this with direct register read */
34 #include <linux/gpio.h>
35 #include <linux/of.h>
36 #include <linux/of_device.h>
37 #include <linux/bug.h>
38 
39 enum mxc_gpio_hwtype {
40 	IMX1_GPIO,	/* runs on i.mx1 */
41 	IMX21_GPIO,	/* runs on i.mx21 and i.mx27 */
42 	IMX31_GPIO,	/* runs on i.mx31 */
43 	IMX35_GPIO,	/* runs on all other i.mx */
44 };
45 
46 /* device type dependent stuff */
47 struct mxc_gpio_hwdata {
48 	unsigned dr_reg;
49 	unsigned gdir_reg;
50 	unsigned psr_reg;
51 	unsigned icr1_reg;
52 	unsigned icr2_reg;
53 	unsigned imr_reg;
54 	unsigned isr_reg;
55 	int edge_sel_reg;
56 	unsigned low_level;
57 	unsigned high_level;
58 	unsigned rise_edge;
59 	unsigned fall_edge;
60 };
61 
62 struct mxc_gpio_port {
63 	struct list_head node;
64 	void __iomem *base;
65 	int irq;
66 	int irq_high;
67 	struct irq_domain *domain;
68 	struct gpio_chip gc;
69 	struct device *dev;
70 	u32 both_edges;
71 };
72 
73 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
74 	.dr_reg		= 0x1c,
75 	.gdir_reg	= 0x00,
76 	.psr_reg	= 0x24,
77 	.icr1_reg	= 0x28,
78 	.icr2_reg	= 0x2c,
79 	.imr_reg	= 0x30,
80 	.isr_reg	= 0x34,
81 	.edge_sel_reg	= -EINVAL,
82 	.low_level	= 0x03,
83 	.high_level	= 0x02,
84 	.rise_edge	= 0x00,
85 	.fall_edge	= 0x01,
86 };
87 
88 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
89 	.dr_reg		= 0x00,
90 	.gdir_reg	= 0x04,
91 	.psr_reg	= 0x08,
92 	.icr1_reg	= 0x0c,
93 	.icr2_reg	= 0x10,
94 	.imr_reg	= 0x14,
95 	.isr_reg	= 0x18,
96 	.edge_sel_reg	= -EINVAL,
97 	.low_level	= 0x00,
98 	.high_level	= 0x01,
99 	.rise_edge	= 0x02,
100 	.fall_edge	= 0x03,
101 };
102 
103 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
104 	.dr_reg		= 0x00,
105 	.gdir_reg	= 0x04,
106 	.psr_reg	= 0x08,
107 	.icr1_reg	= 0x0c,
108 	.icr2_reg	= 0x10,
109 	.imr_reg	= 0x14,
110 	.isr_reg	= 0x18,
111 	.edge_sel_reg	= 0x1c,
112 	.low_level	= 0x00,
113 	.high_level	= 0x01,
114 	.rise_edge	= 0x02,
115 	.fall_edge	= 0x03,
116 };
117 
118 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
119 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
120 
121 #define GPIO_DR			(mxc_gpio_hwdata->dr_reg)
122 #define GPIO_GDIR		(mxc_gpio_hwdata->gdir_reg)
123 #define GPIO_PSR		(mxc_gpio_hwdata->psr_reg)
124 #define GPIO_ICR1		(mxc_gpio_hwdata->icr1_reg)
125 #define GPIO_ICR2		(mxc_gpio_hwdata->icr2_reg)
126 #define GPIO_IMR		(mxc_gpio_hwdata->imr_reg)
127 #define GPIO_ISR		(mxc_gpio_hwdata->isr_reg)
128 #define GPIO_EDGE_SEL		(mxc_gpio_hwdata->edge_sel_reg)
129 
130 #define GPIO_INT_LOW_LEV	(mxc_gpio_hwdata->low_level)
131 #define GPIO_INT_HIGH_LEV	(mxc_gpio_hwdata->high_level)
132 #define GPIO_INT_RISE_EDGE	(mxc_gpio_hwdata->rise_edge)
133 #define GPIO_INT_FALL_EDGE	(mxc_gpio_hwdata->fall_edge)
134 #define GPIO_INT_BOTH_EDGES	0x4
135 
136 static const struct platform_device_id mxc_gpio_devtype[] = {
137 	{
138 		.name = "imx1-gpio",
139 		.driver_data = IMX1_GPIO,
140 	}, {
141 		.name = "imx21-gpio",
142 		.driver_data = IMX21_GPIO,
143 	}, {
144 		.name = "imx31-gpio",
145 		.driver_data = IMX31_GPIO,
146 	}, {
147 		.name = "imx35-gpio",
148 		.driver_data = IMX35_GPIO,
149 	}, {
150 		/* sentinel */
151 	}
152 };
153 
154 static const struct of_device_id mxc_gpio_dt_ids[] = {
155 	{ .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
156 	{ .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
157 	{ .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
158 	{ .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
159 	{ /* sentinel */ }
160 };
161 
162 /*
163  * MX2 has one interrupt *for all* gpio ports. The list is used
164  * to save the references to all ports, so that mx2_gpio_irq_handler
165  * can walk through all interrupt status registers.
166  */
167 static LIST_HEAD(mxc_gpio_ports);
168 
169 /* Note: This driver assumes 32 GPIOs are handled in one register */
170 
171 static int gpio_set_irq_type(struct irq_data *d, u32 type)
172 {
173 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
174 	struct mxc_gpio_port *port = gc->private;
175 	u32 bit, val;
176 	u32 gpio_idx = d->hwirq;
177 	u32 gpio = port->gc.base + gpio_idx;
178 	int edge;
179 	void __iomem *reg = port->base;
180 
181 	port->both_edges &= ~(1 << gpio_idx);
182 	switch (type) {
183 	case IRQ_TYPE_EDGE_RISING:
184 		edge = GPIO_INT_RISE_EDGE;
185 		break;
186 	case IRQ_TYPE_EDGE_FALLING:
187 		edge = GPIO_INT_FALL_EDGE;
188 		break;
189 	case IRQ_TYPE_EDGE_BOTH:
190 		if (GPIO_EDGE_SEL >= 0) {
191 			edge = GPIO_INT_BOTH_EDGES;
192 		} else {
193 			val = gpio_get_value(gpio);
194 			if (val) {
195 				edge = GPIO_INT_LOW_LEV;
196 				pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
197 			} else {
198 				edge = GPIO_INT_HIGH_LEV;
199 				pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
200 			}
201 			port->both_edges |= 1 << gpio_idx;
202 		}
203 		break;
204 	case IRQ_TYPE_LEVEL_LOW:
205 		edge = GPIO_INT_LOW_LEV;
206 		break;
207 	case IRQ_TYPE_LEVEL_HIGH:
208 		edge = GPIO_INT_HIGH_LEV;
209 		break;
210 	default:
211 		return -EINVAL;
212 	}
213 
214 	if (GPIO_EDGE_SEL >= 0) {
215 		val = readl(port->base + GPIO_EDGE_SEL);
216 		if (edge == GPIO_INT_BOTH_EDGES)
217 			writel(val | (1 << gpio_idx),
218 				port->base + GPIO_EDGE_SEL);
219 		else
220 			writel(val & ~(1 << gpio_idx),
221 				port->base + GPIO_EDGE_SEL);
222 	}
223 
224 	if (edge != GPIO_INT_BOTH_EDGES) {
225 		reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
226 		bit = gpio_idx & 0xf;
227 		val = readl(reg) & ~(0x3 << (bit << 1));
228 		writel(val | (edge << (bit << 1)), reg);
229 	}
230 
231 	writel(1 << gpio_idx, port->base + GPIO_ISR);
232 
233 	return 0;
234 }
235 
236 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
237 {
238 	void __iomem *reg = port->base;
239 	u32 bit, val;
240 	int edge;
241 
242 	reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
243 	bit = gpio & 0xf;
244 	val = readl(reg);
245 	edge = (val >> (bit << 1)) & 3;
246 	val &= ~(0x3 << (bit << 1));
247 	if (edge == GPIO_INT_HIGH_LEV) {
248 		edge = GPIO_INT_LOW_LEV;
249 		pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
250 	} else if (edge == GPIO_INT_LOW_LEV) {
251 		edge = GPIO_INT_HIGH_LEV;
252 		pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
253 	} else {
254 		pr_err("mxc: invalid configuration for GPIO %d: %x\n",
255 		       gpio, edge);
256 		return;
257 	}
258 	writel(val | (edge << (bit << 1)), reg);
259 }
260 
261 /* handle 32 interrupts in one status register */
262 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
263 {
264 	while (irq_stat != 0) {
265 		int irqoffset = fls(irq_stat) - 1;
266 
267 		if (port->both_edges & (1 << irqoffset))
268 			mxc_flip_edge(port, irqoffset);
269 
270 		generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
271 
272 		irq_stat &= ~(1 << irqoffset);
273 	}
274 }
275 
276 /* MX1 and MX3 has one interrupt *per* gpio port */
277 static void mx3_gpio_irq_handler(struct irq_desc *desc)
278 {
279 	u32 irq_stat;
280 	struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
281 	struct irq_chip *chip = irq_desc_get_chip(desc);
282 
283 	chained_irq_enter(chip, desc);
284 
285 	irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
286 
287 	mxc_gpio_irq_handler(port, irq_stat);
288 
289 	chained_irq_exit(chip, desc);
290 }
291 
292 /* MX2 has one interrupt *for all* gpio ports */
293 static void mx2_gpio_irq_handler(struct irq_desc *desc)
294 {
295 	u32 irq_msk, irq_stat;
296 	struct mxc_gpio_port *port;
297 	struct irq_chip *chip = irq_desc_get_chip(desc);
298 
299 	chained_irq_enter(chip, desc);
300 
301 	/* walk through all interrupt status registers */
302 	list_for_each_entry(port, &mxc_gpio_ports, node) {
303 		irq_msk = readl(port->base + GPIO_IMR);
304 		if (!irq_msk)
305 			continue;
306 
307 		irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
308 		if (irq_stat)
309 			mxc_gpio_irq_handler(port, irq_stat);
310 	}
311 	chained_irq_exit(chip, desc);
312 }
313 
314 /*
315  * Set interrupt number "irq" in the GPIO as a wake-up source.
316  * While system is running, all registered GPIO interrupts need to have
317  * wake-up enabled. When system is suspended, only selected GPIO interrupts
318  * need to have wake-up enabled.
319  * @param  irq          interrupt source number
320  * @param  enable       enable as wake-up if equal to non-zero
321  * @return       This function returns 0 on success.
322  */
323 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
324 {
325 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
326 	struct mxc_gpio_port *port = gc->private;
327 	u32 gpio_idx = d->hwirq;
328 	int ret;
329 
330 	if (enable) {
331 		if (port->irq_high && (gpio_idx >= 16))
332 			ret = enable_irq_wake(port->irq_high);
333 		else
334 			ret = enable_irq_wake(port->irq);
335 	} else {
336 		if (port->irq_high && (gpio_idx >= 16))
337 			ret = disable_irq_wake(port->irq_high);
338 		else
339 			ret = disable_irq_wake(port->irq);
340 	}
341 
342 	return ret;
343 }
344 
345 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
346 {
347 	struct irq_chip_generic *gc;
348 	struct irq_chip_type *ct;
349 	int rv;
350 
351 	gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base,
352 					 port->base, handle_level_irq);
353 	if (!gc)
354 		return -ENOMEM;
355 	gc->private = port;
356 
357 	ct = gc->chip_types;
358 	ct->chip.irq_ack = irq_gc_ack_set_bit;
359 	ct->chip.irq_mask = irq_gc_mask_clr_bit;
360 	ct->chip.irq_unmask = irq_gc_mask_set_bit;
361 	ct->chip.irq_set_type = gpio_set_irq_type;
362 	ct->chip.irq_set_wake = gpio_set_wake_irq;
363 	ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
364 	ct->regs.ack = GPIO_ISR;
365 	ct->regs.mask = GPIO_IMR;
366 
367 	rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32),
368 					 IRQ_GC_INIT_NESTED_LOCK,
369 					 IRQ_NOREQUEST, 0);
370 
371 	return rv;
372 }
373 
374 static void mxc_gpio_get_hw(struct platform_device *pdev)
375 {
376 	const struct of_device_id *of_id =
377 			of_match_device(mxc_gpio_dt_ids, &pdev->dev);
378 	enum mxc_gpio_hwtype hwtype;
379 
380 	if (of_id)
381 		pdev->id_entry = of_id->data;
382 	hwtype = pdev->id_entry->driver_data;
383 
384 	if (mxc_gpio_hwtype) {
385 		/*
386 		 * The driver works with a reasonable presupposition,
387 		 * that is all gpio ports must be the same type when
388 		 * running on one soc.
389 		 */
390 		BUG_ON(mxc_gpio_hwtype != hwtype);
391 		return;
392 	}
393 
394 	if (hwtype == IMX35_GPIO)
395 		mxc_gpio_hwdata = &imx35_gpio_hwdata;
396 	else if (hwtype == IMX31_GPIO)
397 		mxc_gpio_hwdata = &imx31_gpio_hwdata;
398 	else
399 		mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
400 
401 	mxc_gpio_hwtype = hwtype;
402 }
403 
404 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
405 {
406 	struct mxc_gpio_port *port = gpiochip_get_data(gc);
407 
408 	return irq_find_mapping(port->domain, offset);
409 }
410 
411 static int mxc_gpio_probe(struct platform_device *pdev)
412 {
413 	struct device_node *np = pdev->dev.of_node;
414 	struct mxc_gpio_port *port;
415 	struct resource *iores;
416 	int irq_base;
417 	int err;
418 
419 	mxc_gpio_get_hw(pdev);
420 
421 	port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
422 	if (!port)
423 		return -ENOMEM;
424 
425 	port->dev = &pdev->dev;
426 
427 	iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
428 	port->base = devm_ioremap_resource(&pdev->dev, iores);
429 	if (IS_ERR(port->base))
430 		return PTR_ERR(port->base);
431 
432 	port->irq_high = platform_get_irq(pdev, 1);
433 	if (port->irq_high < 0)
434 		port->irq_high = 0;
435 
436 	port->irq = platform_get_irq(pdev, 0);
437 	if (port->irq < 0)
438 		return port->irq;
439 
440 	/* disable the interrupt and clear the status */
441 	writel(0, port->base + GPIO_IMR);
442 	writel(~0, port->base + GPIO_ISR);
443 
444 	if (mxc_gpio_hwtype == IMX21_GPIO) {
445 		/*
446 		 * Setup one handler for all GPIO interrupts. Actually setting
447 		 * the handler is needed only once, but doing it for every port
448 		 * is more robust and easier.
449 		 */
450 		irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
451 	} else {
452 		/* setup one handler for each entry */
453 		irq_set_chained_handler_and_data(port->irq,
454 						 mx3_gpio_irq_handler, port);
455 		if (port->irq_high > 0)
456 			/* setup handler for GPIO 16 to 31 */
457 			irq_set_chained_handler_and_data(port->irq_high,
458 							 mx3_gpio_irq_handler,
459 							 port);
460 	}
461 
462 	err = bgpio_init(&port->gc, &pdev->dev, 4,
463 			 port->base + GPIO_PSR,
464 			 port->base + GPIO_DR, NULL,
465 			 port->base + GPIO_GDIR, NULL,
466 			 BGPIOF_READ_OUTPUT_REG_SET);
467 	if (err)
468 		goto out_bgio;
469 
470 	if (of_property_read_bool(np, "gpio-ranges")) {
471 		port->gc.request = gpiochip_generic_request;
472 		port->gc.free = gpiochip_generic_free;
473 	}
474 
475 	port->gc.to_irq = mxc_gpio_to_irq;
476 	port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
477 					     pdev->id * 32;
478 
479 	err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
480 	if (err)
481 		goto out_bgio;
482 
483 	irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id());
484 	if (irq_base < 0) {
485 		err = irq_base;
486 		goto out_bgio;
487 	}
488 
489 	port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
490 					     &irq_domain_simple_ops, NULL);
491 	if (!port->domain) {
492 		err = -ENODEV;
493 		goto out_bgio;
494 	}
495 
496 	/* gpio-mxc can be a generic irq chip */
497 	err = mxc_gpio_init_gc(port, irq_base);
498 	if (err < 0)
499 		goto out_irqdomain_remove;
500 
501 	list_add_tail(&port->node, &mxc_gpio_ports);
502 
503 	return 0;
504 
505 out_irqdomain_remove:
506 	irq_domain_remove(port->domain);
507 out_bgio:
508 	dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
509 	return err;
510 }
511 
512 static struct platform_driver mxc_gpio_driver = {
513 	.driver		= {
514 		.name	= "gpio-mxc",
515 		.of_match_table = mxc_gpio_dt_ids,
516 		.suppress_bind_attrs = true,
517 	},
518 	.probe		= mxc_gpio_probe,
519 	.id_table	= mxc_gpio_devtype,
520 };
521 
522 static int __init gpio_mxc_init(void)
523 {
524 	return platform_driver_register(&mxc_gpio_driver);
525 }
526 subsys_initcall(gpio_mxc_init);
527