1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 // 6 // Based on code from Freescale Semiconductor, 7 // Authors: Daniel Mack, Juergen Beisert. 8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 10 #include <linux/clk.h> 11 #include <linux/err.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/irqchip/chained_irq.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/slab.h> 21 #include <linux/syscore_ops.h> 22 #include <linux/gpio/driver.h> 23 #include <linux/of.h> 24 #include <linux/of_device.h> 25 #include <linux/bug.h> 26 27 #define IMX_SCU_WAKEUP_OFF 0 28 #define IMX_SCU_WAKEUP_LOW_LVL 4 29 #define IMX_SCU_WAKEUP_FALL_EDGE 5 30 #define IMX_SCU_WAKEUP_RISE_EDGE 6 31 #define IMX_SCU_WAKEUP_HIGH_LVL 7 32 33 /* device type dependent stuff */ 34 struct mxc_gpio_hwdata { 35 unsigned dr_reg; 36 unsigned gdir_reg; 37 unsigned psr_reg; 38 unsigned icr1_reg; 39 unsigned icr2_reg; 40 unsigned imr_reg; 41 unsigned isr_reg; 42 int edge_sel_reg; 43 unsigned low_level; 44 unsigned high_level; 45 unsigned rise_edge; 46 unsigned fall_edge; 47 }; 48 49 struct mxc_gpio_reg_saved { 50 u32 icr1; 51 u32 icr2; 52 u32 imr; 53 u32 gdir; 54 u32 edge_sel; 55 u32 dr; 56 }; 57 58 struct mxc_gpio_port { 59 struct list_head node; 60 void __iomem *base; 61 struct clk *clk; 62 int irq; 63 int irq_high; 64 struct irq_domain *domain; 65 struct gpio_chip gc; 66 struct device *dev; 67 u32 both_edges; 68 struct mxc_gpio_reg_saved gpio_saved_reg; 69 bool power_off; 70 u32 wakeup_pads; 71 bool is_pad_wakeup; 72 u32 pad_type[32]; 73 const struct mxc_gpio_hwdata *hwdata; 74 }; 75 76 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 77 .dr_reg = 0x1c, 78 .gdir_reg = 0x00, 79 .psr_reg = 0x24, 80 .icr1_reg = 0x28, 81 .icr2_reg = 0x2c, 82 .imr_reg = 0x30, 83 .isr_reg = 0x34, 84 .edge_sel_reg = -EINVAL, 85 .low_level = 0x03, 86 .high_level = 0x02, 87 .rise_edge = 0x00, 88 .fall_edge = 0x01, 89 }; 90 91 static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 92 .dr_reg = 0x00, 93 .gdir_reg = 0x04, 94 .psr_reg = 0x08, 95 .icr1_reg = 0x0c, 96 .icr2_reg = 0x10, 97 .imr_reg = 0x14, 98 .isr_reg = 0x18, 99 .edge_sel_reg = -EINVAL, 100 .low_level = 0x00, 101 .high_level = 0x01, 102 .rise_edge = 0x02, 103 .fall_edge = 0x03, 104 }; 105 106 static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 107 .dr_reg = 0x00, 108 .gdir_reg = 0x04, 109 .psr_reg = 0x08, 110 .icr1_reg = 0x0c, 111 .icr2_reg = 0x10, 112 .imr_reg = 0x14, 113 .isr_reg = 0x18, 114 .edge_sel_reg = 0x1c, 115 .low_level = 0x00, 116 .high_level = 0x01, 117 .rise_edge = 0x02, 118 .fall_edge = 0x03, 119 }; 120 121 #define GPIO_DR (port->hwdata->dr_reg) 122 #define GPIO_GDIR (port->hwdata->gdir_reg) 123 #define GPIO_PSR (port->hwdata->psr_reg) 124 #define GPIO_ICR1 (port->hwdata->icr1_reg) 125 #define GPIO_ICR2 (port->hwdata->icr2_reg) 126 #define GPIO_IMR (port->hwdata->imr_reg) 127 #define GPIO_ISR (port->hwdata->isr_reg) 128 #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 129 130 #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 131 #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 132 #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 133 #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 134 #define GPIO_INT_BOTH_EDGES 0x4 135 136 static const struct of_device_id mxc_gpio_dt_ids[] = { 137 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 138 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 139 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 140 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 141 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 142 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, 143 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, 144 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, 145 { /* sentinel */ } 146 }; 147 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 148 149 /* 150 * MX2 has one interrupt *for all* gpio ports. The list is used 151 * to save the references to all ports, so that mx2_gpio_irq_handler 152 * can walk through all interrupt status registers. 153 */ 154 static LIST_HEAD(mxc_gpio_ports); 155 156 /* Note: This driver assumes 32 GPIOs are handled in one register */ 157 158 static int gpio_set_irq_type(struct irq_data *d, u32 type) 159 { 160 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 161 struct mxc_gpio_port *port = gc->private; 162 u32 bit, val; 163 u32 gpio_idx = d->hwirq; 164 int edge; 165 void __iomem *reg = port->base; 166 167 port->both_edges &= ~(1 << gpio_idx); 168 switch (type) { 169 case IRQ_TYPE_EDGE_RISING: 170 edge = GPIO_INT_RISE_EDGE; 171 break; 172 case IRQ_TYPE_EDGE_FALLING: 173 edge = GPIO_INT_FALL_EDGE; 174 break; 175 case IRQ_TYPE_EDGE_BOTH: 176 if (GPIO_EDGE_SEL >= 0) { 177 edge = GPIO_INT_BOTH_EDGES; 178 } else { 179 val = port->gc.get(&port->gc, gpio_idx); 180 if (val) { 181 edge = GPIO_INT_LOW_LEV; 182 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 183 } else { 184 edge = GPIO_INT_HIGH_LEV; 185 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 186 } 187 port->both_edges |= 1 << gpio_idx; 188 } 189 break; 190 case IRQ_TYPE_LEVEL_LOW: 191 edge = GPIO_INT_LOW_LEV; 192 break; 193 case IRQ_TYPE_LEVEL_HIGH: 194 edge = GPIO_INT_HIGH_LEV; 195 break; 196 default: 197 return -EINVAL; 198 } 199 200 if (GPIO_EDGE_SEL >= 0) { 201 val = readl(port->base + GPIO_EDGE_SEL); 202 if (edge == GPIO_INT_BOTH_EDGES) 203 writel(val | (1 << gpio_idx), 204 port->base + GPIO_EDGE_SEL); 205 else 206 writel(val & ~(1 << gpio_idx), 207 port->base + GPIO_EDGE_SEL); 208 } 209 210 if (edge != GPIO_INT_BOTH_EDGES) { 211 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 212 bit = gpio_idx & 0xf; 213 val = readl(reg) & ~(0x3 << (bit << 1)); 214 writel(val | (edge << (bit << 1)), reg); 215 } 216 217 writel(1 << gpio_idx, port->base + GPIO_ISR); 218 port->pad_type[gpio_idx] = type; 219 220 return 0; 221 } 222 223 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 224 { 225 void __iomem *reg = port->base; 226 u32 bit, val; 227 int edge; 228 229 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 230 bit = gpio & 0xf; 231 val = readl(reg); 232 edge = (val >> (bit << 1)) & 3; 233 val &= ~(0x3 << (bit << 1)); 234 if (edge == GPIO_INT_HIGH_LEV) { 235 edge = GPIO_INT_LOW_LEV; 236 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 237 } else if (edge == GPIO_INT_LOW_LEV) { 238 edge = GPIO_INT_HIGH_LEV; 239 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 240 } else { 241 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 242 gpio, edge); 243 return; 244 } 245 writel(val | (edge << (bit << 1)), reg); 246 } 247 248 /* handle 32 interrupts in one status register */ 249 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 250 { 251 while (irq_stat != 0) { 252 int irqoffset = fls(irq_stat) - 1; 253 254 if (port->both_edges & (1 << irqoffset)) 255 mxc_flip_edge(port, irqoffset); 256 257 generic_handle_domain_irq(port->domain, irqoffset); 258 259 irq_stat &= ~(1 << irqoffset); 260 } 261 } 262 263 /* MX1 and MX3 has one interrupt *per* gpio port */ 264 static void mx3_gpio_irq_handler(struct irq_desc *desc) 265 { 266 u32 irq_stat; 267 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 268 struct irq_chip *chip = irq_desc_get_chip(desc); 269 270 if (port->is_pad_wakeup) 271 return; 272 273 chained_irq_enter(chip, desc); 274 275 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 276 277 mxc_gpio_irq_handler(port, irq_stat); 278 279 chained_irq_exit(chip, desc); 280 } 281 282 /* MX2 has one interrupt *for all* gpio ports */ 283 static void mx2_gpio_irq_handler(struct irq_desc *desc) 284 { 285 u32 irq_msk, irq_stat; 286 struct mxc_gpio_port *port; 287 struct irq_chip *chip = irq_desc_get_chip(desc); 288 289 chained_irq_enter(chip, desc); 290 291 /* walk through all interrupt status registers */ 292 list_for_each_entry(port, &mxc_gpio_ports, node) { 293 irq_msk = readl(port->base + GPIO_IMR); 294 if (!irq_msk) 295 continue; 296 297 irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 298 if (irq_stat) 299 mxc_gpio_irq_handler(port, irq_stat); 300 } 301 chained_irq_exit(chip, desc); 302 } 303 304 /* 305 * Set interrupt number "irq" in the GPIO as a wake-up source. 306 * While system is running, all registered GPIO interrupts need to have 307 * wake-up enabled. When system is suspended, only selected GPIO interrupts 308 * need to have wake-up enabled. 309 * @param irq interrupt source number 310 * @param enable enable as wake-up if equal to non-zero 311 * @return This function returns 0 on success. 312 */ 313 static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 314 { 315 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 316 struct mxc_gpio_port *port = gc->private; 317 u32 gpio_idx = d->hwirq; 318 int ret; 319 320 if (enable) { 321 if (port->irq_high && (gpio_idx >= 16)) 322 ret = enable_irq_wake(port->irq_high); 323 else 324 ret = enable_irq_wake(port->irq); 325 port->wakeup_pads |= (1 << gpio_idx); 326 } else { 327 if (port->irq_high && (gpio_idx >= 16)) 328 ret = disable_irq_wake(port->irq_high); 329 else 330 ret = disable_irq_wake(port->irq); 331 port->wakeup_pads &= ~(1 << gpio_idx); 332 } 333 334 return ret; 335 } 336 337 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 338 { 339 struct irq_chip_generic *gc; 340 struct irq_chip_type *ct; 341 int rv; 342 343 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 344 port->base, handle_level_irq); 345 if (!gc) 346 return -ENOMEM; 347 gc->private = port; 348 349 ct = gc->chip_types; 350 ct->chip.irq_ack = irq_gc_ack_set_bit; 351 ct->chip.irq_mask = irq_gc_mask_clr_bit; 352 ct->chip.irq_unmask = irq_gc_mask_set_bit; 353 ct->chip.irq_set_type = gpio_set_irq_type; 354 ct->chip.irq_set_wake = gpio_set_wake_irq; 355 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 356 ct->regs.ack = GPIO_ISR; 357 ct->regs.mask = GPIO_IMR; 358 359 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 360 IRQ_GC_INIT_NESTED_LOCK, 361 IRQ_NOREQUEST, 0); 362 363 return rv; 364 } 365 366 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 367 { 368 struct mxc_gpio_port *port = gpiochip_get_data(gc); 369 370 return irq_find_mapping(port->domain, offset); 371 } 372 373 static int mxc_gpio_probe(struct platform_device *pdev) 374 { 375 struct device_node *np = pdev->dev.of_node; 376 struct mxc_gpio_port *port; 377 int irq_count; 378 int irq_base; 379 int err; 380 381 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 382 if (!port) 383 return -ENOMEM; 384 385 port->dev = &pdev->dev; 386 port->hwdata = device_get_match_data(&pdev->dev); 387 388 port->base = devm_platform_ioremap_resource(pdev, 0); 389 if (IS_ERR(port->base)) 390 return PTR_ERR(port->base); 391 392 irq_count = platform_irq_count(pdev); 393 if (irq_count < 0) 394 return irq_count; 395 396 if (irq_count > 1) { 397 port->irq_high = platform_get_irq(pdev, 1); 398 if (port->irq_high < 0) 399 port->irq_high = 0; 400 } 401 402 port->irq = platform_get_irq(pdev, 0); 403 if (port->irq < 0) 404 return port->irq; 405 406 /* the controller clock is optional */ 407 port->clk = devm_clk_get_optional(&pdev->dev, NULL); 408 if (IS_ERR(port->clk)) 409 return PTR_ERR(port->clk); 410 411 err = clk_prepare_enable(port->clk); 412 if (err) { 413 dev_err(&pdev->dev, "Unable to enable clock.\n"); 414 return err; 415 } 416 417 if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 418 port->power_off = true; 419 420 /* disable the interrupt and clear the status */ 421 writel(0, port->base + GPIO_IMR); 422 writel(~0, port->base + GPIO_ISR); 423 424 if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 425 /* 426 * Setup one handler for all GPIO interrupts. Actually setting 427 * the handler is needed only once, but doing it for every port 428 * is more robust and easier. 429 */ 430 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler); 431 } else { 432 /* setup one handler for each entry */ 433 irq_set_chained_handler_and_data(port->irq, 434 mx3_gpio_irq_handler, port); 435 if (port->irq_high > 0) 436 /* setup handler for GPIO 16 to 31 */ 437 irq_set_chained_handler_and_data(port->irq_high, 438 mx3_gpio_irq_handler, 439 port); 440 } 441 442 err = bgpio_init(&port->gc, &pdev->dev, 4, 443 port->base + GPIO_PSR, 444 port->base + GPIO_DR, NULL, 445 port->base + GPIO_GDIR, NULL, 446 BGPIOF_READ_OUTPUT_REG_SET); 447 if (err) 448 goto out_bgio; 449 450 port->gc.request = gpiochip_generic_request; 451 port->gc.free = gpiochip_generic_free; 452 port->gc.to_irq = mxc_gpio_to_irq; 453 port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 : 454 pdev->id * 32; 455 456 err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port); 457 if (err) 458 goto out_bgio; 459 460 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 461 if (irq_base < 0) { 462 err = irq_base; 463 goto out_bgio; 464 } 465 466 port->domain = irq_domain_add_legacy(np, 32, irq_base, 0, 467 &irq_domain_simple_ops, NULL); 468 if (!port->domain) { 469 err = -ENODEV; 470 goto out_bgio; 471 } 472 473 /* gpio-mxc can be a generic irq chip */ 474 err = mxc_gpio_init_gc(port, irq_base); 475 if (err < 0) 476 goto out_irqdomain_remove; 477 478 list_add_tail(&port->node, &mxc_gpio_ports); 479 480 platform_set_drvdata(pdev, port); 481 482 return 0; 483 484 out_irqdomain_remove: 485 irq_domain_remove(port->domain); 486 out_bgio: 487 clk_disable_unprepare(port->clk); 488 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 489 return err; 490 } 491 492 static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 493 { 494 if (!port->power_off) 495 return; 496 497 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 498 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 499 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 500 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 501 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 502 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 503 } 504 505 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 506 { 507 if (!port->power_off) 508 return; 509 510 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 511 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 512 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 513 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 514 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 515 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 516 } 517 518 static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, 519 unsigned int offset, unsigned long conf) 520 { 521 struct device_node *np = port->dev->of_node; 522 523 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || 524 of_device_is_compatible(np, "fsl,imx8qxp-gpio") || 525 of_device_is_compatible(np, "fsl,imx8qm-gpio")) 526 return (gpiochip_generic_config(&port->gc, offset, conf) == 0); 527 528 return false; 529 } 530 531 static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) 532 { 533 unsigned long config; 534 bool ret = false; 535 int i, type; 536 537 static const u32 pad_type_map[] = { 538 IMX_SCU_WAKEUP_OFF, /* 0 */ 539 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ 540 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ 541 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_BOTH */ 542 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ 543 IMX_SCU_WAKEUP_OFF, /* 5 */ 544 IMX_SCU_WAKEUP_OFF, /* 6 */ 545 IMX_SCU_WAKEUP_OFF, /* 7 */ 546 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ 547 }; 548 549 for (i = 0; i < 32; i++) { 550 if ((port->wakeup_pads & (1 << i))) { 551 type = port->pad_type[i]; 552 if (enable) 553 config = pad_type_map[type]; 554 else 555 config = IMX_SCU_WAKEUP_OFF; 556 ret |= mxc_gpio_generic_config(port, i, config); 557 } 558 } 559 560 return ret; 561 } 562 563 static int __maybe_unused mxc_gpio_noirq_suspend(struct device *dev) 564 { 565 struct platform_device *pdev = to_platform_device(dev); 566 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 567 568 if (port->wakeup_pads > 0) 569 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); 570 571 return 0; 572 } 573 574 static int __maybe_unused mxc_gpio_noirq_resume(struct device *dev) 575 { 576 struct platform_device *pdev = to_platform_device(dev); 577 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 578 579 if (port->wakeup_pads > 0) 580 mxc_gpio_set_pad_wakeup(port, false); 581 port->is_pad_wakeup = false; 582 583 return 0; 584 } 585 586 static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { 587 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) 588 }; 589 590 static int mxc_gpio_syscore_suspend(void) 591 { 592 struct mxc_gpio_port *port; 593 594 /* walk through all ports */ 595 list_for_each_entry(port, &mxc_gpio_ports, node) { 596 mxc_gpio_save_regs(port); 597 clk_disable_unprepare(port->clk); 598 } 599 600 return 0; 601 } 602 603 static void mxc_gpio_syscore_resume(void) 604 { 605 struct mxc_gpio_port *port; 606 int ret; 607 608 /* walk through all ports */ 609 list_for_each_entry(port, &mxc_gpio_ports, node) { 610 ret = clk_prepare_enable(port->clk); 611 if (ret) { 612 pr_err("mxc: failed to enable gpio clock %d\n", ret); 613 return; 614 } 615 mxc_gpio_restore_regs(port); 616 } 617 } 618 619 static struct syscore_ops mxc_gpio_syscore_ops = { 620 .suspend = mxc_gpio_syscore_suspend, 621 .resume = mxc_gpio_syscore_resume, 622 }; 623 624 static struct platform_driver mxc_gpio_driver = { 625 .driver = { 626 .name = "gpio-mxc", 627 .of_match_table = mxc_gpio_dt_ids, 628 .suppress_bind_attrs = true, 629 .pm = &mxc_gpio_dev_pm_ops, 630 }, 631 .probe = mxc_gpio_probe, 632 }; 633 634 static int __init gpio_mxc_init(void) 635 { 636 register_syscore_ops(&mxc_gpio_syscore_ops); 637 638 return platform_driver_register(&mxc_gpio_driver); 639 } 640 subsys_initcall(gpio_mxc_init); 641 642 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 643 MODULE_DESCRIPTION("i.MX GPIO Driver"); 644 MODULE_LICENSE("GPL"); 645