1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de> 4 // Copyright 2008 Juergen Beisert, kernel@pengutronix.de 5 // 6 // Based on code from Freescale Semiconductor, 7 // Authors: Daniel Mack, Juergen Beisert. 8 // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. 9 10 #include <linux/bitops.h> 11 #include <linux/cleanup.h> 12 #include <linux/clk.h> 13 #include <linux/err.h> 14 #include <linux/init.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/irq.h> 18 #include <linux/irqdomain.h> 19 #include <linux/irqchip/chained_irq.h> 20 #include <linux/module.h> 21 #include <linux/platform_device.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/syscore_ops.h> 26 #include <linux/gpio/driver.h> 27 #include <linux/gpio/generic.h> 28 #include <linux/of.h> 29 #include <linux/bug.h> 30 31 #define IMX_SCU_WAKEUP_OFF 0 32 #define IMX_SCU_WAKEUP_LOW_LVL 4 33 #define IMX_SCU_WAKEUP_FALL_EDGE 5 34 #define IMX_SCU_WAKEUP_RISE_EDGE 6 35 #define IMX_SCU_WAKEUP_HIGH_LVL 7 36 37 /* device type dependent stuff */ 38 struct mxc_gpio_hwdata { 39 unsigned dr_reg; 40 unsigned gdir_reg; 41 unsigned psr_reg; 42 unsigned icr1_reg; 43 unsigned icr2_reg; 44 unsigned imr_reg; 45 unsigned isr_reg; 46 int edge_sel_reg; 47 unsigned low_level; 48 unsigned high_level; 49 unsigned rise_edge; 50 unsigned fall_edge; 51 }; 52 53 struct mxc_gpio_reg_saved { 54 u32 icr1; 55 u32 icr2; 56 u32 imr; 57 u32 gdir; 58 u32 edge_sel; 59 u32 dr; 60 }; 61 62 struct mxc_gpio_port { 63 struct list_head node; 64 void __iomem *base; 65 struct clk *clk; 66 int irq; 67 int irq_high; 68 void (*mx_irq_handler)(struct irq_desc *desc); 69 struct irq_domain *domain; 70 struct gpio_generic_chip gen_gc; 71 struct device *dev; 72 unsigned long both_edges; 73 struct mxc_gpio_reg_saved gpio_saved_reg; 74 bool power_off; 75 bool is_pad_wakeup; 76 unsigned long wakeup_pads; 77 u32 pad_type[32]; 78 const struct mxc_gpio_hwdata *hwdata; 79 }; 80 81 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = { 82 .dr_reg = 0x1c, 83 .gdir_reg = 0x00, 84 .psr_reg = 0x24, 85 .icr1_reg = 0x28, 86 .icr2_reg = 0x2c, 87 .imr_reg = 0x30, 88 .isr_reg = 0x34, 89 .edge_sel_reg = -EINVAL, 90 .low_level = 0x03, 91 .high_level = 0x02, 92 .rise_edge = 0x00, 93 .fall_edge = 0x01, 94 }; 95 96 static struct mxc_gpio_hwdata imx31_gpio_hwdata = { 97 .dr_reg = 0x00, 98 .gdir_reg = 0x04, 99 .psr_reg = 0x08, 100 .icr1_reg = 0x0c, 101 .icr2_reg = 0x10, 102 .imr_reg = 0x14, 103 .isr_reg = 0x18, 104 .edge_sel_reg = -EINVAL, 105 .low_level = 0x00, 106 .high_level = 0x01, 107 .rise_edge = 0x02, 108 .fall_edge = 0x03, 109 }; 110 111 static struct mxc_gpio_hwdata imx35_gpio_hwdata = { 112 .dr_reg = 0x00, 113 .gdir_reg = 0x04, 114 .psr_reg = 0x08, 115 .icr1_reg = 0x0c, 116 .icr2_reg = 0x10, 117 .imr_reg = 0x14, 118 .isr_reg = 0x18, 119 .edge_sel_reg = 0x1c, 120 .low_level = 0x00, 121 .high_level = 0x01, 122 .rise_edge = 0x02, 123 .fall_edge = 0x03, 124 }; 125 126 #define GPIO_DR (port->hwdata->dr_reg) 127 #define GPIO_GDIR (port->hwdata->gdir_reg) 128 #define GPIO_PSR (port->hwdata->psr_reg) 129 #define GPIO_ICR1 (port->hwdata->icr1_reg) 130 #define GPIO_ICR2 (port->hwdata->icr2_reg) 131 #define GPIO_IMR (port->hwdata->imr_reg) 132 #define GPIO_ISR (port->hwdata->isr_reg) 133 #define GPIO_EDGE_SEL (port->hwdata->edge_sel_reg) 134 135 #define GPIO_INT_LOW_LEV (port->hwdata->low_level) 136 #define GPIO_INT_HIGH_LEV (port->hwdata->high_level) 137 #define GPIO_INT_RISE_EDGE (port->hwdata->rise_edge) 138 #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) 139 #define GPIO_INT_BOTH_EDGES 0x4 140 141 static const struct of_device_id mxc_gpio_dt_ids[] = { 142 { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, 143 { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, 144 { .compatible = "fsl,imx31-gpio", .data = &imx31_gpio_hwdata }, 145 { .compatible = "fsl,imx35-gpio", .data = &imx35_gpio_hwdata }, 146 { .compatible = "fsl,imx7d-gpio", .data = &imx35_gpio_hwdata }, 147 { .compatible = "fsl,imx8dxl-gpio", .data = &imx35_gpio_hwdata }, 148 { .compatible = "fsl,imx8qm-gpio", .data = &imx35_gpio_hwdata }, 149 { .compatible = "fsl,imx8qxp-gpio", .data = &imx35_gpio_hwdata }, 150 { /* sentinel */ } 151 }; 152 MODULE_DEVICE_TABLE(of, mxc_gpio_dt_ids); 153 154 /* 155 * MX2 has one interrupt *for all* gpio ports. The list is used 156 * to save the references to all ports, so that mx2_gpio_irq_handler 157 * can walk through all interrupt status registers. 158 */ 159 static LIST_HEAD(mxc_gpio_ports); 160 161 /* Note: This driver assumes 32 GPIOs are handled in one register */ 162 163 static int gpio_set_irq_type(struct irq_data *d, u32 type) 164 { 165 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 166 struct mxc_gpio_port *port = gc->private; 167 u32 bit, val; 168 u32 gpio_idx = d->hwirq; 169 int edge; 170 void __iomem *reg = port->base; 171 172 clear_bit(gpio_idx, &port->both_edges); 173 switch (type) { 174 case IRQ_TYPE_EDGE_RISING: 175 edge = GPIO_INT_RISE_EDGE; 176 break; 177 case IRQ_TYPE_EDGE_FALLING: 178 edge = GPIO_INT_FALL_EDGE; 179 break; 180 case IRQ_TYPE_EDGE_BOTH: 181 if (GPIO_EDGE_SEL >= 0) { 182 edge = GPIO_INT_BOTH_EDGES; 183 } else { 184 val = port->gen_gc.gc.get(&port->gen_gc.gc, gpio_idx); 185 if (val) { 186 edge = GPIO_INT_LOW_LEV; 187 pr_debug("mxc: set GPIO %d to low trigger\n", gpio_idx); 188 } else { 189 edge = GPIO_INT_HIGH_LEV; 190 pr_debug("mxc: set GPIO %d to high trigger\n", gpio_idx); 191 } 192 set_bit(gpio_idx, &port->both_edges); 193 } 194 break; 195 case IRQ_TYPE_LEVEL_LOW: 196 edge = GPIO_INT_LOW_LEV; 197 break; 198 case IRQ_TYPE_LEVEL_HIGH: 199 edge = GPIO_INT_HIGH_LEV; 200 break; 201 default: 202 return -EINVAL; 203 } 204 205 scoped_guard(gpio_generic_lock_irqsave, &port->gen_gc) { 206 if (GPIO_EDGE_SEL >= 0) { 207 val = readl(port->base + GPIO_EDGE_SEL); 208 if (edge == GPIO_INT_BOTH_EDGES) 209 writel(val | (1 << gpio_idx), 210 port->base + GPIO_EDGE_SEL); 211 else 212 writel(val & ~(1 << gpio_idx), 213 port->base + GPIO_EDGE_SEL); 214 } 215 216 if (edge != GPIO_INT_BOTH_EDGES) { 217 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ 218 bit = gpio_idx & 0xf; 219 val = readl(reg) & ~(0x3 << (bit << 1)); 220 writel(val | (edge << (bit << 1)), reg); 221 } 222 223 writel(1 << gpio_idx, port->base + GPIO_ISR); 224 port->pad_type[gpio_idx] = type; 225 } 226 227 return port->gen_gc.gc.direction_input(&port->gen_gc.gc, gpio_idx); 228 } 229 230 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) 231 { 232 void __iomem *reg = port->base; 233 u32 bit, val; 234 int edge; 235 236 guard(gpio_generic_lock_irqsave)(&port->gen_gc); 237 238 reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ 239 bit = gpio & 0xf; 240 val = readl(reg); 241 edge = (val >> (bit << 1)) & 3; 242 val &= ~(0x3 << (bit << 1)); 243 if (edge == GPIO_INT_HIGH_LEV) { 244 edge = GPIO_INT_LOW_LEV; 245 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); 246 } else if (edge == GPIO_INT_LOW_LEV) { 247 edge = GPIO_INT_HIGH_LEV; 248 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio); 249 } else { 250 pr_err("mxc: invalid configuration for GPIO %d: %x\n", 251 gpio, edge); 252 return; 253 } 254 writel(val | (edge << (bit << 1)), reg); 255 } 256 257 /* handle 32 interrupts in one status register */ 258 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat) 259 { 260 while (irq_stat != 0) { 261 int irqoffset = fls(irq_stat) - 1; 262 263 if (test_bit(irqoffset, &port->both_edges)) 264 mxc_flip_edge(port, irqoffset); 265 266 generic_handle_domain_irq(port->domain, irqoffset); 267 268 irq_stat &= ~(1 << irqoffset); 269 } 270 } 271 272 /* MX1 and MX3 has one interrupt *per* gpio port */ 273 static void mx3_gpio_irq_handler(struct irq_desc *desc) 274 { 275 u32 irq_stat; 276 struct mxc_gpio_port *port = irq_desc_get_handler_data(desc); 277 struct irq_chip *chip = irq_desc_get_chip(desc); 278 279 if (port->is_pad_wakeup) 280 return; 281 282 chained_irq_enter(chip, desc); 283 284 irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR); 285 286 mxc_gpio_irq_handler(port, irq_stat); 287 288 chained_irq_exit(chip, desc); 289 } 290 291 /* MX2 has one interrupt *for all* gpio ports */ 292 static void mx2_gpio_irq_handler(struct irq_desc *desc) 293 { 294 u32 irq_msk, irq_stat; 295 struct mxc_gpio_port *port; 296 struct irq_chip *chip = irq_desc_get_chip(desc); 297 298 chained_irq_enter(chip, desc); 299 300 /* walk through all interrupt status registers */ 301 list_for_each_entry(port, &mxc_gpio_ports, node) { 302 irq_msk = readl(port->base + GPIO_IMR); 303 if (!irq_msk) 304 continue; 305 306 irq_stat = readl(port->base + GPIO_ISR) & irq_msk; 307 if (irq_stat) 308 mxc_gpio_irq_handler(port, irq_stat); 309 } 310 chained_irq_exit(chip, desc); 311 } 312 313 /* 314 * Set interrupt number "irq" in the GPIO as a wake-up source. 315 * While system is running, all registered GPIO interrupts need to have 316 * wake-up enabled. When system is suspended, only selected GPIO interrupts 317 * need to have wake-up enabled. 318 * @param irq interrupt source number 319 * @param enable enable as wake-up if equal to non-zero 320 * @return This function returns 0 on success. 321 */ 322 static int gpio_set_wake_irq(struct irq_data *d, u32 enable) 323 { 324 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 325 struct mxc_gpio_port *port = gc->private; 326 u32 gpio_idx = d->hwirq; 327 int ret; 328 329 if (enable) { 330 if (port->irq_high && (gpio_idx >= 16)) 331 ret = enable_irq_wake(port->irq_high); 332 else 333 ret = enable_irq_wake(port->irq); 334 } else { 335 if (port->irq_high && (gpio_idx >= 16)) 336 ret = disable_irq_wake(port->irq_high); 337 else 338 ret = disable_irq_wake(port->irq); 339 } 340 if (ret) 341 return ret; 342 343 assign_bit(gpio_idx, &port->wakeup_pads, enable); 344 345 return 0; 346 } 347 348 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base) 349 { 350 struct irq_chip_generic *gc; 351 struct irq_chip_type *ct; 352 int rv; 353 354 gc = devm_irq_alloc_generic_chip(port->dev, "gpio-mxc", 1, irq_base, 355 port->base, handle_level_irq); 356 if (!gc) 357 return -ENOMEM; 358 gc->private = port; 359 360 ct = gc->chip_types; 361 ct->chip.irq_ack = irq_gc_ack_set_bit; 362 ct->chip.irq_mask = irq_gc_mask_clr_bit; 363 ct->chip.irq_unmask = irq_gc_mask_set_bit; 364 ct->chip.irq_set_type = gpio_set_irq_type; 365 ct->chip.irq_set_wake = gpio_set_wake_irq; 366 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND; 367 ct->regs.ack = GPIO_ISR; 368 ct->regs.mask = GPIO_IMR; 369 370 rv = devm_irq_setup_generic_chip(port->dev, gc, IRQ_MSK(32), 371 IRQ_GC_INIT_NESTED_LOCK, 372 IRQ_NOREQUEST, 0); 373 374 return rv; 375 } 376 377 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 378 { 379 struct mxc_gpio_port *port = gpiochip_get_data(gc); 380 381 return irq_find_mapping(port->domain, offset); 382 } 383 384 static int mxc_gpio_request(struct gpio_chip *chip, unsigned int offset) 385 { 386 int ret; 387 388 ret = gpiochip_generic_request(chip, offset); 389 if (ret) 390 return ret; 391 392 return pm_runtime_resume_and_get(chip->parent); 393 } 394 395 static void mxc_gpio_free(struct gpio_chip *chip, unsigned int offset) 396 { 397 gpiochip_generic_free(chip, offset); 398 pm_runtime_put(chip->parent); 399 } 400 401 static void mxc_update_irq_chained_handler(struct mxc_gpio_port *port, bool enable) 402 { 403 if (enable) 404 irq_set_chained_handler_and_data(port->irq, port->mx_irq_handler, port); 405 else 406 irq_set_chained_handler_and_data(port->irq, NULL, NULL); 407 408 /* setup handler for GPIO 16 to 31 */ 409 if (port->irq_high > 0) { 410 if (enable) 411 irq_set_chained_handler_and_data(port->irq_high, 412 port->mx_irq_handler, 413 port); 414 else 415 irq_set_chained_handler_and_data(port->irq_high, NULL, NULL); 416 } 417 } 418 419 static int mxc_gpio_probe(struct platform_device *pdev) 420 { 421 struct gpio_generic_chip_config config = { }; 422 struct device_node *np = pdev->dev.of_node; 423 struct mxc_gpio_port *port; 424 int irq_count; 425 int irq_base; 426 int err; 427 428 port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL); 429 if (!port) 430 return -ENOMEM; 431 432 port->dev = &pdev->dev; 433 port->hwdata = device_get_match_data(&pdev->dev); 434 435 port->base = devm_platform_ioremap_resource(pdev, 0); 436 if (IS_ERR(port->base)) 437 return PTR_ERR(port->base); 438 439 irq_count = platform_irq_count(pdev); 440 if (irq_count < 0) 441 return irq_count; 442 443 if (irq_count > 1) { 444 port->irq_high = platform_get_irq(pdev, 1); 445 if (port->irq_high < 0) 446 port->irq_high = 0; 447 } 448 449 port->irq = platform_get_irq(pdev, 0); 450 if (port->irq < 0) 451 return port->irq; 452 453 /* the controller clock is optional */ 454 port->clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 455 if (IS_ERR(port->clk)) 456 return PTR_ERR(port->clk); 457 458 if (of_device_is_compatible(np, "fsl,imx7d-gpio")) 459 port->power_off = true; 460 461 pm_runtime_get_noresume(&pdev->dev); 462 pm_runtime_set_active(&pdev->dev); 463 pm_runtime_enable(&pdev->dev); 464 465 /* disable the interrupt and clear the status */ 466 writel(0, port->base + GPIO_IMR); 467 writel(~0, port->base + GPIO_ISR); 468 469 if (of_device_is_compatible(np, "fsl,imx21-gpio")) { 470 /* 471 * Setup one handler for all GPIO interrupts. Actually setting 472 * the handler is needed only once, but doing it for every port 473 * is more robust and easier. 474 */ 475 port->irq_high = 0; 476 port->mx_irq_handler = mx2_gpio_irq_handler; 477 } else 478 port->mx_irq_handler = mx3_gpio_irq_handler; 479 480 config.dev = &pdev->dev; 481 config.sz = 4; 482 config.dat = port->base + GPIO_PSR; 483 config.set = port->base + GPIO_DR; 484 config.dirout = port->base + GPIO_GDIR; 485 config.flags = GPIO_GENERIC_READ_OUTPUT_REG_SET; 486 487 err = gpio_generic_chip_init(&port->gen_gc, &config); 488 if (err) 489 goto out_bgio; 490 491 port->gen_gc.gc.request = mxc_gpio_request; 492 port->gen_gc.gc.free = mxc_gpio_free; 493 port->gen_gc.gc.to_irq = mxc_gpio_to_irq; 494 /* 495 * Driver is DT-only, so a fixed base needs only be maintained for legacy 496 * userspace with sysfs interface. 497 */ 498 if (IS_ENABLED(CONFIG_GPIO_SYSFS)) 499 port->gen_gc.gc.base = of_alias_get_id(np, "gpio") * 32; 500 else /* silence boot time warning */ 501 port->gen_gc.gc.base = -1; 502 503 irq_base = devm_irq_alloc_descs(&pdev->dev, -1, 0, 32, numa_node_id()); 504 if (irq_base < 0) { 505 err = irq_base; 506 goto out_bgio; 507 } 508 509 port->domain = irq_domain_create_legacy(dev_fwnode(&pdev->dev), 32, irq_base, 0, 510 &irq_domain_simple_ops, NULL); 511 if (!port->domain) { 512 err = -ENODEV; 513 goto out_bgio; 514 } 515 516 irq_domain_set_pm_device(port->domain, &pdev->dev); 517 518 /* gpio-mxc can be a generic irq chip */ 519 err = mxc_gpio_init_gc(port, irq_base); 520 if (err < 0) 521 goto out_irqdomain_remove; 522 523 /* 524 * Register the GPIO chip last: devm_gpiochip_add_data() makes the 525 * chip visible to consumers immediately, so the IRQ domain and 526 * generic irq chip must be ready before any to_irq() call. 527 */ 528 err = devm_gpiochip_add_data(&pdev->dev, &port->gen_gc.gc, port); 529 if (err) 530 goto out_irqdomain_remove; 531 532 list_add_tail(&port->node, &mxc_gpio_ports); 533 534 mxc_update_irq_chained_handler(port, true); 535 536 platform_set_drvdata(pdev, port); 537 pm_runtime_put_autosuspend(&pdev->dev); 538 539 return 0; 540 541 out_irqdomain_remove: 542 irq_domain_remove(port->domain); 543 out_bgio: 544 pm_runtime_disable(&pdev->dev); 545 pm_runtime_put_noidle(&pdev->dev); 546 dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err); 547 return err; 548 } 549 550 static void mxc_gpio_save_regs(struct mxc_gpio_port *port) 551 { 552 if (!port->power_off) 553 return; 554 555 port->gpio_saved_reg.icr1 = readl(port->base + GPIO_ICR1); 556 port->gpio_saved_reg.icr2 = readl(port->base + GPIO_ICR2); 557 port->gpio_saved_reg.imr = readl(port->base + GPIO_IMR); 558 port->gpio_saved_reg.gdir = readl(port->base + GPIO_GDIR); 559 port->gpio_saved_reg.edge_sel = readl(port->base + GPIO_EDGE_SEL); 560 port->gpio_saved_reg.dr = readl(port->base + GPIO_DR); 561 } 562 563 static void mxc_gpio_restore_regs(struct mxc_gpio_port *port) 564 { 565 if (!port->power_off) 566 return; 567 568 writel(port->gpio_saved_reg.icr1, port->base + GPIO_ICR1); 569 writel(port->gpio_saved_reg.icr2, port->base + GPIO_ICR2); 570 writel(port->gpio_saved_reg.imr, port->base + GPIO_IMR); 571 writel(port->gpio_saved_reg.gdir, port->base + GPIO_GDIR); 572 writel(port->gpio_saved_reg.edge_sel, port->base + GPIO_EDGE_SEL); 573 writel(port->gpio_saved_reg.dr, port->base + GPIO_DR); 574 } 575 576 static bool mxc_gpio_generic_config(struct mxc_gpio_port *port, 577 unsigned int offset, unsigned long conf) 578 { 579 struct device_node *np = port->dev->of_node; 580 581 if (of_device_is_compatible(np, "fsl,imx8dxl-gpio") || 582 of_device_is_compatible(np, "fsl,imx8qxp-gpio") || 583 of_device_is_compatible(np, "fsl,imx8qm-gpio")) 584 return (gpiochip_generic_config(&port->gen_gc.gc, 585 offset, conf) == 0); 586 587 return false; 588 } 589 590 static bool mxc_gpio_set_pad_wakeup(struct mxc_gpio_port *port, bool enable) 591 { 592 unsigned long config; 593 bool ret = false; 594 int i, type; 595 bool is_imx8qm = of_device_is_compatible(port->dev->of_node, "fsl,imx8qm-gpio"); 596 597 static const u32 pad_type_map[] = { 598 IMX_SCU_WAKEUP_OFF, /* 0 */ 599 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_RISING */ 600 IMX_SCU_WAKEUP_FALL_EDGE, /* IRQ_TYPE_EDGE_FALLING */ 601 IMX_SCU_WAKEUP_RISE_EDGE, /* IRQ_TYPE_EDGE_BOTH */ 602 IMX_SCU_WAKEUP_HIGH_LVL, /* IRQ_TYPE_LEVEL_HIGH */ 603 IMX_SCU_WAKEUP_OFF, /* 5 */ 604 IMX_SCU_WAKEUP_OFF, /* 6 */ 605 IMX_SCU_WAKEUP_OFF, /* 7 */ 606 IMX_SCU_WAKEUP_LOW_LVL, /* IRQ_TYPE_LEVEL_LOW */ 607 }; 608 609 for (i = 0; i < 32; i++) { 610 if ((port->wakeup_pads & (1 << i))) { 611 type = port->pad_type[i]; 612 if (enable) 613 config = pad_type_map[type]; 614 else 615 config = IMX_SCU_WAKEUP_OFF; 616 617 if (is_imx8qm && config == IMX_SCU_WAKEUP_FALL_EDGE) { 618 dev_warn_once(port->dev, 619 "No falling-edge support for wakeup on i.MX8QM\n"); 620 config = IMX_SCU_WAKEUP_OFF; 621 } 622 623 ret |= mxc_gpio_generic_config(port, i, config); 624 } 625 } 626 627 return ret; 628 } 629 630 static int mxc_gpio_runtime_suspend(struct device *dev) 631 { 632 struct mxc_gpio_port *port = dev_get_drvdata(dev); 633 634 mxc_gpio_save_regs(port); 635 clk_disable_unprepare(port->clk); 636 mxc_update_irq_chained_handler(port, false); 637 638 return 0; 639 } 640 641 static int mxc_gpio_runtime_resume(struct device *dev) 642 { 643 struct mxc_gpio_port *port = dev_get_drvdata(dev); 644 int ret; 645 646 mxc_update_irq_chained_handler(port, true); 647 ret = clk_prepare_enable(port->clk); 648 if (ret) { 649 mxc_update_irq_chained_handler(port, false); 650 return ret; 651 } 652 653 mxc_gpio_restore_regs(port); 654 655 return 0; 656 } 657 658 static int mxc_gpio_noirq_suspend(struct device *dev) 659 { 660 struct platform_device *pdev = to_platform_device(dev); 661 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 662 663 if (port->wakeup_pads > 0) 664 port->is_pad_wakeup = mxc_gpio_set_pad_wakeup(port, true); 665 666 return 0; 667 } 668 669 static int mxc_gpio_noirq_resume(struct device *dev) 670 { 671 struct platform_device *pdev = to_platform_device(dev); 672 struct mxc_gpio_port *port = platform_get_drvdata(pdev); 673 674 if (port->wakeup_pads > 0) 675 mxc_gpio_set_pad_wakeup(port, false); 676 port->is_pad_wakeup = false; 677 678 return 0; 679 } 680 681 static const struct dev_pm_ops mxc_gpio_dev_pm_ops = { 682 NOIRQ_SYSTEM_SLEEP_PM_OPS(mxc_gpio_noirq_suspend, mxc_gpio_noirq_resume) 683 RUNTIME_PM_OPS(mxc_gpio_runtime_suspend, mxc_gpio_runtime_resume, NULL) 684 }; 685 686 static int mxc_gpio_syscore_suspend(void *data) 687 { 688 struct mxc_gpio_port *port; 689 int ret; 690 691 /* walk through all ports */ 692 list_for_each_entry(port, &mxc_gpio_ports, node) { 693 ret = clk_prepare_enable(port->clk); 694 if (ret) 695 return ret; 696 mxc_gpio_save_regs(port); 697 clk_disable_unprepare(port->clk); 698 } 699 700 return 0; 701 } 702 703 static void mxc_gpio_syscore_resume(void *data) 704 { 705 struct mxc_gpio_port *port; 706 int ret; 707 708 /* walk through all ports */ 709 list_for_each_entry(port, &mxc_gpio_ports, node) { 710 ret = clk_prepare_enable(port->clk); 711 if (ret) { 712 pr_err("mxc: failed to enable gpio clock %d\n", ret); 713 return; 714 } 715 mxc_gpio_restore_regs(port); 716 clk_disable_unprepare(port->clk); 717 } 718 } 719 720 static const struct syscore_ops mxc_gpio_syscore_ops = { 721 .suspend = mxc_gpio_syscore_suspend, 722 .resume = mxc_gpio_syscore_resume, 723 }; 724 725 static struct syscore mxc_gpio_syscore = { 726 .ops = &mxc_gpio_syscore_ops, 727 }; 728 729 static struct platform_driver mxc_gpio_driver = { 730 .driver = { 731 .name = "gpio-mxc", 732 .of_match_table = mxc_gpio_dt_ids, 733 .suppress_bind_attrs = true, 734 .pm = pm_ptr(&mxc_gpio_dev_pm_ops), 735 }, 736 .probe = mxc_gpio_probe, 737 }; 738 739 static int __init gpio_mxc_init(void) 740 { 741 register_syscore(&mxc_gpio_syscore); 742 743 return platform_driver_register(&mxc_gpio_driver); 744 } 745 subsys_initcall(gpio_mxc_init); 746 747 MODULE_AUTHOR("Shawn Guo <shawn.guo@linaro.org>"); 748 MODULE_DESCRIPTION("i.MX GPIO Driver"); 749 MODULE_LICENSE("GPL"); 750