1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/gpio.h> 38 #include <linux/irq.h> 39 #include <linux/slab.h> 40 #include <linux/irqdomain.h> 41 #include <linux/io.h> 42 #include <linux/of_irq.h> 43 #include <linux/of_device.h> 44 #include <linux/pinctrl/consumer.h> 45 46 /* 47 * GPIO unit register offsets. 48 */ 49 #define GPIO_OUT_OFF 0x0000 50 #define GPIO_IO_CONF_OFF 0x0004 51 #define GPIO_BLINK_EN_OFF 0x0008 52 #define GPIO_IN_POL_OFF 0x000c 53 #define GPIO_DATA_IN_OFF 0x0010 54 #define GPIO_EDGE_CAUSE_OFF 0x0014 55 #define GPIO_EDGE_MASK_OFF 0x0018 56 #define GPIO_LEVEL_MASK_OFF 0x001c 57 58 /* The MV78200 has per-CPU registers for edge mask and level mask */ 59 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 60 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 61 62 /* The Armada XP has per-CPU registers for interrupt cause, interrupt 63 * mask and interrupt level mask. Those are relative to the 64 * percpu_membase. */ 65 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 66 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 67 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 68 69 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 70 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 71 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 72 73 #define MVEBU_MAX_GPIO_PER_BANK 32 74 75 struct mvebu_gpio_chip { 76 struct gpio_chip chip; 77 spinlock_t lock; 78 void __iomem *membase; 79 void __iomem *percpu_membase; 80 unsigned int irqbase; 81 struct irq_domain *domain; 82 int soc_variant; 83 }; 84 85 /* 86 * Functions returning addresses of individual registers for a given 87 * GPIO controller. 88 */ 89 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) 90 { 91 return mvchip->membase + GPIO_OUT_OFF; 92 } 93 94 static inline void __iomem *mvebu_gpioreg_blink(struct mvebu_gpio_chip *mvchip) 95 { 96 return mvchip->membase + GPIO_BLINK_EN_OFF; 97 } 98 99 static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) 100 { 101 return mvchip->membase + GPIO_IO_CONF_OFF; 102 } 103 104 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) 105 { 106 return mvchip->membase + GPIO_IN_POL_OFF; 107 } 108 109 static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) 110 { 111 return mvchip->membase + GPIO_DATA_IN_OFF; 112 } 113 114 static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) 115 { 116 int cpu; 117 118 switch(mvchip->soc_variant) { 119 case MVEBU_GPIO_SOC_VARIANT_ORION: 120 case MVEBU_GPIO_SOC_VARIANT_MV78200: 121 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 122 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 123 cpu = smp_processor_id(); 124 return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 125 default: 126 BUG(); 127 } 128 } 129 130 static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) 131 { 132 int cpu; 133 134 switch(mvchip->soc_variant) { 135 case MVEBU_GPIO_SOC_VARIANT_ORION: 136 return mvchip->membase + GPIO_EDGE_MASK_OFF; 137 case MVEBU_GPIO_SOC_VARIANT_MV78200: 138 cpu = smp_processor_id(); 139 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 140 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 141 cpu = smp_processor_id(); 142 return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 143 default: 144 BUG(); 145 } 146 } 147 148 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) 149 { 150 int cpu; 151 152 switch(mvchip->soc_variant) { 153 case MVEBU_GPIO_SOC_VARIANT_ORION: 154 return mvchip->membase + GPIO_LEVEL_MASK_OFF; 155 case MVEBU_GPIO_SOC_VARIANT_MV78200: 156 cpu = smp_processor_id(); 157 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); 158 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 159 cpu = smp_processor_id(); 160 return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 161 default: 162 BUG(); 163 } 164 } 165 166 /* 167 * Functions implementing the gpio_chip methods 168 */ 169 170 static int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin) 171 { 172 return pinctrl_request_gpio(chip->base + pin); 173 } 174 175 static void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin) 176 { 177 pinctrl_free_gpio(chip->base + pin); 178 } 179 180 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 181 { 182 struct mvebu_gpio_chip *mvchip = 183 container_of(chip, struct mvebu_gpio_chip, chip); 184 unsigned long flags; 185 u32 u; 186 187 spin_lock_irqsave(&mvchip->lock, flags); 188 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 189 if (value) 190 u |= 1 << pin; 191 else 192 u &= ~(1 << pin); 193 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 194 spin_unlock_irqrestore(&mvchip->lock, flags); 195 } 196 197 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) 198 { 199 struct mvebu_gpio_chip *mvchip = 200 container_of(chip, struct mvebu_gpio_chip, chip); 201 u32 u; 202 203 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { 204 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ 205 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 206 } else { 207 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 208 } 209 210 return (u >> pin) & 1; 211 } 212 213 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned pin, int value) 214 { 215 struct mvebu_gpio_chip *mvchip = 216 container_of(chip, struct mvebu_gpio_chip, chip); 217 unsigned long flags; 218 u32 u; 219 220 spin_lock_irqsave(&mvchip->lock, flags); 221 u = readl_relaxed(mvebu_gpioreg_blink(mvchip)); 222 if (value) 223 u |= 1 << pin; 224 else 225 u &= ~(1 << pin); 226 writel_relaxed(u, mvebu_gpioreg_blink(mvchip)); 227 spin_unlock_irqrestore(&mvchip->lock, flags); 228 } 229 230 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 231 { 232 struct mvebu_gpio_chip *mvchip = 233 container_of(chip, struct mvebu_gpio_chip, chip); 234 unsigned long flags; 235 int ret; 236 u32 u; 237 238 /* Check with the pinctrl driver whether this pin is usable as 239 * an input GPIO */ 240 ret = pinctrl_gpio_direction_input(chip->base + pin); 241 if (ret) 242 return ret; 243 244 spin_lock_irqsave(&mvchip->lock, flags); 245 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 246 u |= 1 << pin; 247 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 248 spin_unlock_irqrestore(&mvchip->lock, flags); 249 250 return 0; 251 } 252 253 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 254 int value) 255 { 256 struct mvebu_gpio_chip *mvchip = 257 container_of(chip, struct mvebu_gpio_chip, chip); 258 unsigned long flags; 259 int ret; 260 u32 u; 261 262 /* Check with the pinctrl driver whether this pin is usable as 263 * an output GPIO */ 264 ret = pinctrl_gpio_direction_output(chip->base + pin); 265 if (ret) 266 return ret; 267 268 mvebu_gpio_blink(chip, pin, 0); 269 mvebu_gpio_set(chip, pin, value); 270 271 spin_lock_irqsave(&mvchip->lock, flags); 272 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 273 u &= ~(1 << pin); 274 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 275 spin_unlock_irqrestore(&mvchip->lock, flags); 276 277 return 0; 278 } 279 280 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 281 { 282 struct mvebu_gpio_chip *mvchip = 283 container_of(chip, struct mvebu_gpio_chip, chip); 284 return irq_create_mapping(mvchip->domain, pin); 285 } 286 287 /* 288 * Functions implementing the irq_chip methods 289 */ 290 static void mvebu_gpio_irq_ack(struct irq_data *d) 291 { 292 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 293 struct mvebu_gpio_chip *mvchip = gc->private; 294 u32 mask = ~(1 << (d->irq - gc->irq_base)); 295 296 irq_gc_lock(gc); 297 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); 298 irq_gc_unlock(gc); 299 } 300 301 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 302 { 303 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 304 struct mvebu_gpio_chip *mvchip = gc->private; 305 u32 mask = 1 << (d->irq - gc->irq_base); 306 307 irq_gc_lock(gc); 308 gc->mask_cache &= ~mask; 309 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 310 irq_gc_unlock(gc); 311 } 312 313 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 314 { 315 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 316 struct mvebu_gpio_chip *mvchip = gc->private; 317 u32 mask = 1 << (d->irq - gc->irq_base); 318 319 irq_gc_lock(gc); 320 gc->mask_cache |= mask; 321 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 322 irq_gc_unlock(gc); 323 } 324 325 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 326 { 327 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 328 struct mvebu_gpio_chip *mvchip = gc->private; 329 u32 mask = 1 << (d->irq - gc->irq_base); 330 331 irq_gc_lock(gc); 332 gc->mask_cache &= ~mask; 333 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 334 irq_gc_unlock(gc); 335 } 336 337 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 338 { 339 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 340 struct mvebu_gpio_chip *mvchip = gc->private; 341 u32 mask = 1 << (d->irq - gc->irq_base); 342 343 irq_gc_lock(gc); 344 gc->mask_cache |= mask; 345 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 346 irq_gc_unlock(gc); 347 } 348 349 /***************************************************************************** 350 * MVEBU GPIO IRQ 351 * 352 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 353 * value of the line or the opposite value. 354 * 355 * Level IRQ handlers: DATA_IN is used directly as cause register. 356 * Interrupt are masked by LEVEL_MASK registers. 357 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 358 * Interrupt are masked by EDGE_MASK registers. 359 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 360 * the polarity to catch the next line transaction. 361 * This is a race condition that might not perfectly 362 * work on some use cases. 363 * 364 * Every eight GPIO lines are grouped (OR'ed) before going up to main 365 * cause register. 366 * 367 * EDGE cause mask 368 * data-in /--------| |-----| |----\ 369 * -----| |----- ---- to main cause reg 370 * X \----------------| |----/ 371 * polarity LEVEL mask 372 * 373 ****************************************************************************/ 374 375 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 376 { 377 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 378 struct irq_chip_type *ct = irq_data_get_chip_type(d); 379 struct mvebu_gpio_chip *mvchip = gc->private; 380 int pin; 381 u32 u; 382 383 pin = d->hwirq; 384 385 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); 386 if (!u) { 387 return -EINVAL; 388 } 389 390 type &= IRQ_TYPE_SENSE_MASK; 391 if (type == IRQ_TYPE_NONE) 392 return -EINVAL; 393 394 /* Check if we need to change chip and handler */ 395 if (!(ct->type & type)) 396 if (irq_setup_alt_chip(d, type)) 397 return -EINVAL; 398 399 /* 400 * Configure interrupt polarity. 401 */ 402 switch(type) { 403 case IRQ_TYPE_EDGE_RISING: 404 case IRQ_TYPE_LEVEL_HIGH: 405 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 406 u &= ~(1 << pin); 407 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 408 break; 409 case IRQ_TYPE_EDGE_FALLING: 410 case IRQ_TYPE_LEVEL_LOW: 411 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 412 u |= 1 << pin; 413 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 414 break; 415 case IRQ_TYPE_EDGE_BOTH: { 416 u32 v; 417 418 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ 419 readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 420 421 /* 422 * set initial polarity based on current input level 423 */ 424 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 425 if (v & (1 << pin)) 426 u |= 1 << pin; /* falling */ 427 else 428 u &= ~(1 << pin); /* rising */ 429 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 430 break; 431 } 432 } 433 return 0; 434 } 435 436 static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 437 { 438 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); 439 u32 cause, type; 440 int i; 441 442 if (mvchip == NULL) 443 return; 444 445 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 446 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 447 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 448 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 449 450 for (i = 0; i < mvchip->chip.ngpio; i++) { 451 int irq; 452 453 irq = mvchip->irqbase + i; 454 455 if (!(cause & (1 << i))) 456 continue; 457 458 type = irqd_get_trigger_type(irq_get_irq_data(irq)); 459 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 460 /* Swap polarity (race with GPIO line) */ 461 u32 polarity; 462 463 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 464 polarity ^= 1 << i; 465 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 466 } 467 generic_handle_irq(irq); 468 } 469 } 470 471 static struct of_device_id mvebu_gpio_of_match[] = { 472 { 473 .compatible = "marvell,orion-gpio", 474 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ORION, 475 }, 476 { 477 .compatible = "marvell,mv78200-gpio", 478 .data = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200, 479 }, 480 { 481 .compatible = "marvell,armadaxp-gpio", 482 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 483 }, 484 { 485 /* sentinel */ 486 }, 487 }; 488 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); 489 490 static int mvebu_gpio_probe(struct platform_device *pdev) 491 { 492 struct mvebu_gpio_chip *mvchip; 493 const struct of_device_id *match; 494 struct device_node *np = pdev->dev.of_node; 495 struct resource *res; 496 struct irq_chip_generic *gc; 497 struct irq_chip_type *ct; 498 unsigned int ngpios; 499 int soc_variant; 500 int i, cpu, id; 501 502 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 503 if (match) 504 soc_variant = (int) match->data; 505 else 506 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 507 508 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 509 if (! res) { 510 dev_err(&pdev->dev, "Cannot get memory resource\n"); 511 return -ENODEV; 512 } 513 514 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); 515 if (! mvchip){ 516 dev_err(&pdev->dev, "Cannot allocate memory\n"); 517 return -ENOMEM; 518 } 519 520 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 521 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 522 return -ENODEV; 523 } 524 525 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 526 if (id < 0) { 527 dev_err(&pdev->dev, "Couldn't get OF id\n"); 528 return id; 529 } 530 531 mvchip->soc_variant = soc_variant; 532 mvchip->chip.label = dev_name(&pdev->dev); 533 mvchip->chip.dev = &pdev->dev; 534 mvchip->chip.request = mvebu_gpio_request; 535 mvchip->chip.free = mvebu_gpio_free; 536 mvchip->chip.direction_input = mvebu_gpio_direction_input; 537 mvchip->chip.get = mvebu_gpio_get; 538 mvchip->chip.direction_output = mvebu_gpio_direction_output; 539 mvchip->chip.set = mvebu_gpio_set; 540 mvchip->chip.to_irq = mvebu_gpio_to_irq; 541 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 542 mvchip->chip.ngpio = ngpios; 543 mvchip->chip.can_sleep = 0; 544 mvchip->chip.of_node = np; 545 546 spin_lock_init(&mvchip->lock); 547 mvchip->membase = devm_request_and_ioremap(&pdev->dev, res); 548 if (! mvchip->membase) { 549 dev_err(&pdev->dev, "Cannot ioremap\n"); 550 kfree(mvchip->chip.label); 551 return -ENOMEM; 552 } 553 554 /* The Armada XP has a second range of registers for the 555 * per-CPU registers */ 556 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 557 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 558 if (! res) { 559 dev_err(&pdev->dev, "Cannot get memory resource\n"); 560 kfree(mvchip->chip.label); 561 return -ENODEV; 562 } 563 564 mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res); 565 if (! mvchip->percpu_membase) { 566 dev_err(&pdev->dev, "Cannot ioremap\n"); 567 kfree(mvchip->chip.label); 568 return -ENOMEM; 569 } 570 } 571 572 /* 573 * Mask and clear GPIO interrupts. 574 */ 575 switch(soc_variant) { 576 case MVEBU_GPIO_SOC_VARIANT_ORION: 577 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 578 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 579 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 580 break; 581 case MVEBU_GPIO_SOC_VARIANT_MV78200: 582 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 583 for (cpu = 0; cpu < 2; cpu++) { 584 writel_relaxed(0, mvchip->membase + 585 GPIO_EDGE_MASK_MV78200_OFF(cpu)); 586 writel_relaxed(0, mvchip->membase + 587 GPIO_LEVEL_MASK_MV78200_OFF(cpu)); 588 } 589 break; 590 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 591 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 592 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 593 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 594 for (cpu = 0; cpu < 4; cpu++) { 595 writel_relaxed(0, mvchip->percpu_membase + 596 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); 597 writel_relaxed(0, mvchip->percpu_membase + 598 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); 599 writel_relaxed(0, mvchip->percpu_membase + 600 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); 601 } 602 break; 603 default: 604 BUG(); 605 } 606 607 gpiochip_add(&mvchip->chip); 608 609 /* Some gpio controllers do not provide irq support */ 610 if (!of_irq_count(np)) 611 return 0; 612 613 /* Setup the interrupt handlers. Each chip can have up to 4 614 * interrupt handlers, with each handler dealing with 8 GPIO 615 * pins. */ 616 for (i = 0; i < 4; i++) { 617 int irq; 618 irq = platform_get_irq(pdev, i); 619 if (irq < 0) 620 continue; 621 irq_set_handler_data(irq, mvchip); 622 irq_set_chained_handler(irq, mvebu_gpio_irq_handler); 623 } 624 625 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); 626 if (mvchip->irqbase < 0) { 627 dev_err(&pdev->dev, "no irqs\n"); 628 kfree(mvchip->chip.label); 629 return -ENOMEM; 630 } 631 632 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, 633 mvchip->membase, handle_level_irq); 634 if (! gc) { 635 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); 636 kfree(mvchip->chip.label); 637 return -ENOMEM; 638 } 639 640 gc->private = mvchip; 641 ct = &gc->chip_types[0]; 642 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 643 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 644 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 645 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 646 ct->chip.name = mvchip->chip.label; 647 648 ct = &gc->chip_types[1]; 649 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 650 ct->chip.irq_ack = mvebu_gpio_irq_ack; 651 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 652 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 653 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 654 ct->handler = handle_edge_irq; 655 ct->chip.name = mvchip->chip.label; 656 657 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, 658 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 659 660 /* Setup irq domain on top of the generic chip. */ 661 mvchip->domain = irq_domain_add_simple(np, mvchip->chip.ngpio, 662 mvchip->irqbase, 663 &irq_domain_simple_ops, 664 mvchip); 665 if (!mvchip->domain) { 666 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 667 mvchip->chip.label); 668 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, 669 IRQ_LEVEL | IRQ_NOPROBE); 670 kfree(gc); 671 kfree(mvchip->chip.label); 672 return -ENODEV; 673 } 674 675 return 0; 676 } 677 678 static struct platform_driver mvebu_gpio_driver = { 679 .driver = { 680 .name = "mvebu-gpio", 681 .owner = THIS_MODULE, 682 .of_match_table = mvebu_gpio_of_match, 683 }, 684 .probe = mvebu_gpio_probe, 685 }; 686 687 static int __init mvebu_gpio_init(void) 688 { 689 return platform_driver_register(&mvebu_gpio_driver); 690 } 691 postcore_initcall(mvebu_gpio_init); 692