1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for Marvell SoCs 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 10 * 11 * This driver is a fairly straightforward GPIO driver for the 12 * complete family of Marvell EBU SoC platforms (Orion, Dove, 13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 14 * driver is the different register layout that exists between the 15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 16 * platforms (MV78200 from the Discovery family and the Armada 17 * XP). Therefore, this driver handles three variants of the GPIO 18 * block: 19 * - the basic variant, called "orion-gpio", with the simplest 20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 21 * non-SMP Discovery systems 22 * - the mv78200 variant for MV78200 Discovery systems. This variant 23 * turns the edge mask and level mask registers into CPU0 edge 24 * mask/level mask registers, and adds CPU1 edge mask/level mask 25 * registers. 26 * - the armadaxp variant for Armada XP systems. This variant keeps 27 * the normal cause/edge mask/level mask registers when the global 28 * interrupts are used, but adds per-CPU cause/edge mask/level mask 29 * registers n a separate memory area for the per-CPU GPIO 30 * interrupts. 31 */ 32 33 #include <linux/bitops.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/gpio/driver.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/gpio/machine.h> 39 #include <linux/init.h> 40 #include <linux/io.h> 41 #include <linux/irq.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqdomain.h> 44 #include <linux/mfd/syscon.h> 45 #include <linux/of.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/platform_device.h> 48 #include <linux/property.h> 49 #include <linux/pwm.h> 50 #include <linux/regmap.h> 51 #include <linux/slab.h> 52 #include <linux/string_choices.h> 53 54 /* 55 * GPIO unit register offsets. 56 */ 57 #define GPIO_OUT_OFF 0x0000 58 #define GPIO_IO_CONF_OFF 0x0004 59 #define GPIO_BLINK_EN_OFF 0x0008 60 #define GPIO_IN_POL_OFF 0x000c 61 #define GPIO_DATA_IN_OFF 0x0010 62 #define GPIO_EDGE_CAUSE_OFF 0x0014 63 #define GPIO_EDGE_MASK_OFF 0x0018 64 #define GPIO_LEVEL_MASK_OFF 0x001c 65 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 66 67 /* 68 * PWM register offsets. 69 */ 70 #define PWM_BLINK_ON_DURATION_OFF 0x0 71 #define PWM_BLINK_OFF_DURATION_OFF 0x4 72 #define PWM_BLINK_COUNTER_B_OFF 0x8 73 74 /* Armada 8k variant gpios register offsets */ 75 #define AP80X_GPIO0_OFF_A8K 0x1040 76 #define CP11X_GPIO0_OFF_A8K 0x100 77 #define CP11X_GPIO1_OFF_A8K 0x140 78 79 /* The MV78200 has per-CPU registers for edge mask and level mask */ 80 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 81 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 82 83 /* 84 * The Armada XP has per-CPU registers for interrupt cause, interrupt 85 * mask and interrupt level mask. Those are in percpu_regs range. 86 */ 87 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 88 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 89 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 90 91 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 92 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 93 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 94 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 95 96 #define MVEBU_MAX_GPIO_PER_BANK 32 97 98 struct mvebu_pwm { 99 struct regmap *regs; 100 u32 offset; 101 unsigned long clk_rate; 102 struct gpio_desc *gpiod; 103 spinlock_t lock; 104 struct mvebu_gpio_chip *mvchip; 105 106 /* Used to preserve GPIO/PWM registers across suspend/resume */ 107 u32 blink_select; 108 u32 blink_on_duration; 109 u32 blink_off_duration; 110 }; 111 112 struct mvebu_gpio_chip { 113 struct gpio_chip chip; 114 struct regmap *regs; 115 u32 offset; 116 struct regmap *percpu_regs; 117 int irqbase; 118 struct irq_domain *domain; 119 int soc_variant; 120 121 /* Used for PWM support */ 122 struct clk *clk; 123 struct mvebu_pwm *mvpwm; 124 125 /* Used to preserve GPIO registers across suspend/resume */ 126 u32 out_reg; 127 u32 io_conf_reg; 128 u32 blink_en_reg; 129 u32 in_pol_reg; 130 u32 edge_mask_regs[4]; 131 u32 level_mask_regs[4]; 132 }; 133 134 /* 135 * Functions returning addresses of individual registers for a given 136 * GPIO controller. 137 */ 138 139 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 140 struct regmap **map, unsigned int *offset) 141 { 142 int cpu; 143 144 switch (mvchip->soc_variant) { 145 case MVEBU_GPIO_SOC_VARIANT_ORION: 146 case MVEBU_GPIO_SOC_VARIANT_MV78200: 147 case MVEBU_GPIO_SOC_VARIANT_A8K: 148 *map = mvchip->regs; 149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 150 break; 151 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 152 cpu = smp_processor_id(); 153 *map = mvchip->percpu_regs; 154 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 155 break; 156 default: 157 BUG(); 158 } 159 } 160 161 static u32 162 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 163 { 164 struct regmap *map; 165 unsigned int offset; 166 u32 val; 167 168 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 169 regmap_read(map, offset, &val); 170 171 return val; 172 } 173 174 static void 175 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 176 { 177 struct regmap *map; 178 unsigned int offset; 179 180 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 181 regmap_write(map, offset, val); 182 } 183 184 static inline void 185 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 186 struct regmap **map, unsigned int *offset) 187 { 188 int cpu; 189 190 switch (mvchip->soc_variant) { 191 case MVEBU_GPIO_SOC_VARIANT_ORION: 192 case MVEBU_GPIO_SOC_VARIANT_A8K: 193 *map = mvchip->regs; 194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 195 break; 196 case MVEBU_GPIO_SOC_VARIANT_MV78200: 197 cpu = smp_processor_id(); 198 *map = mvchip->regs; 199 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 200 break; 201 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 202 cpu = smp_processor_id(); 203 *map = mvchip->percpu_regs; 204 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 205 break; 206 default: 207 BUG(); 208 } 209 } 210 211 static u32 212 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 213 { 214 struct regmap *map; 215 unsigned int offset; 216 u32 val; 217 218 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 219 regmap_read(map, offset, &val); 220 221 return val; 222 } 223 224 static void 225 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 226 { 227 struct regmap *map; 228 unsigned int offset; 229 230 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 231 regmap_write(map, offset, val); 232 } 233 234 static void 235 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 236 struct regmap **map, unsigned int *offset) 237 { 238 int cpu; 239 240 switch (mvchip->soc_variant) { 241 case MVEBU_GPIO_SOC_VARIANT_ORION: 242 case MVEBU_GPIO_SOC_VARIANT_A8K: 243 *map = mvchip->regs; 244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 245 break; 246 case MVEBU_GPIO_SOC_VARIANT_MV78200: 247 cpu = smp_processor_id(); 248 *map = mvchip->regs; 249 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 250 break; 251 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 252 cpu = smp_processor_id(); 253 *map = mvchip->percpu_regs; 254 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 255 break; 256 default: 257 BUG(); 258 } 259 } 260 261 static u32 262 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 263 { 264 struct regmap *map; 265 unsigned int offset; 266 u32 val; 267 268 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 269 regmap_read(map, offset, &val); 270 271 return val; 272 } 273 274 static void 275 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 276 { 277 struct regmap *map; 278 unsigned int offset; 279 280 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 281 regmap_write(map, offset, val); 282 } 283 284 /* 285 * Functions returning offsets of individual registers for a given 286 * PWM controller. 287 */ 288 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 289 { 290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; 291 } 292 293 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 294 { 295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; 296 } 297 298 /* 299 * Functions implementing the gpio_chip methods 300 */ 301 static int mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 302 { 303 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 304 305 return regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 306 BIT(pin), value ? BIT(pin) : 0); 307 } 308 309 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 310 { 311 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 312 u32 u; 313 314 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 315 316 if (u & BIT(pin)) { 317 u32 data_in, in_pol; 318 319 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 320 &data_in); 321 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 322 &in_pol); 323 u = data_in ^ in_pol; 324 } else { 325 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 326 } 327 328 return (u >> pin) & 1; 329 } 330 331 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 332 int value) 333 { 334 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 335 336 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 337 BIT(pin), value ? BIT(pin) : 0); 338 } 339 340 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 341 { 342 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 343 int ret; 344 345 /* 346 * Check with the pinctrl driver whether this pin is usable as 347 * an input GPIO 348 */ 349 ret = pinctrl_gpio_direction_input(chip, pin); 350 if (ret) 351 return ret; 352 353 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 354 BIT(pin), BIT(pin)); 355 356 return 0; 357 } 358 359 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 360 int value) 361 { 362 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 363 int ret; 364 365 /* 366 * Check with the pinctrl driver whether this pin is usable as 367 * an output GPIO 368 */ 369 ret = pinctrl_gpio_direction_output(chip, pin); 370 if (ret) 371 return ret; 372 373 mvebu_gpio_blink(chip, pin, 0); 374 mvebu_gpio_set(chip, pin, value); 375 376 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 377 BIT(pin), 0); 378 379 return 0; 380 } 381 382 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 383 { 384 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 385 u32 u; 386 387 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 388 389 if (u & BIT(pin)) 390 return GPIO_LINE_DIRECTION_IN; 391 392 return GPIO_LINE_DIRECTION_OUT; 393 } 394 395 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 396 { 397 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 398 399 return irq_create_mapping(mvchip->domain, pin); 400 } 401 402 /* 403 * Functions implementing the irq_chip methods 404 */ 405 static void mvebu_gpio_irq_ack(struct irq_data *d) 406 { 407 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 408 struct mvebu_gpio_chip *mvchip = gc->private; 409 u32 mask = d->mask; 410 411 guard(raw_spinlock)(&gc->lock); 412 mvebu_gpio_write_edge_cause(mvchip, ~mask); 413 } 414 415 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 416 { 417 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 418 struct mvebu_gpio_chip *mvchip = gc->private; 419 struct irq_chip_type *ct = irq_data_get_chip_type(d); 420 u32 mask = d->mask; 421 422 guard(raw_spinlock)(&gc->lock); 423 ct->mask_cache_priv &= ~mask; 424 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 425 } 426 427 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 428 { 429 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 430 struct mvebu_gpio_chip *mvchip = gc->private; 431 struct irq_chip_type *ct = irq_data_get_chip_type(d); 432 u32 mask = d->mask; 433 434 guard(raw_spinlock)(&gc->lock); 435 mvebu_gpio_write_edge_cause(mvchip, ~mask); 436 ct->mask_cache_priv |= mask; 437 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 438 } 439 440 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 441 { 442 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 443 struct mvebu_gpio_chip *mvchip = gc->private; 444 struct irq_chip_type *ct = irq_data_get_chip_type(d); 445 u32 mask = d->mask; 446 447 guard(raw_spinlock)(&gc->lock); 448 ct->mask_cache_priv &= ~mask; 449 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 450 } 451 452 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 453 { 454 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 455 struct mvebu_gpio_chip *mvchip = gc->private; 456 struct irq_chip_type *ct = irq_data_get_chip_type(d); 457 u32 mask = d->mask; 458 459 guard(raw_spinlock)(&gc->lock); 460 ct->mask_cache_priv |= mask; 461 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 462 } 463 464 /***************************************************************************** 465 * MVEBU GPIO IRQ 466 * 467 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 468 * value of the line or the opposite value. 469 * 470 * Level IRQ handlers: DATA_IN is used directly as cause register. 471 * Interrupt are masked by LEVEL_MASK registers. 472 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 473 * Interrupt are masked by EDGE_MASK registers. 474 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 475 * the polarity to catch the next line transaction. 476 * This is a race condition that might not perfectly 477 * work on some use cases. 478 * 479 * Every eight GPIO lines are grouped (OR'ed) before going up to main 480 * cause register. 481 * 482 * EDGE cause mask 483 * data-in /--------| |-----| |----\ 484 * -----| |----- ---- to main cause reg 485 * X \----------------| |----/ 486 * polarity LEVEL mask 487 * 488 ****************************************************************************/ 489 490 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 491 { 492 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 493 struct irq_chip_type *ct = irq_data_get_chip_type(d); 494 struct mvebu_gpio_chip *mvchip = gc->private; 495 int pin; 496 u32 u; 497 498 pin = d->hwirq; 499 500 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 501 if ((u & BIT(pin)) == 0) 502 return -EINVAL; 503 504 type &= IRQ_TYPE_SENSE_MASK; 505 if (type == IRQ_TYPE_NONE) 506 return -EINVAL; 507 508 /* Check if we need to change chip and handler */ 509 if (!(ct->type & type)) 510 if (irq_setup_alt_chip(d, type)) 511 return -EINVAL; 512 513 /* 514 * Configure interrupt polarity. 515 */ 516 switch (type) { 517 case IRQ_TYPE_EDGE_RISING: 518 case IRQ_TYPE_LEVEL_HIGH: 519 regmap_update_bits(mvchip->regs, 520 GPIO_IN_POL_OFF + mvchip->offset, 521 BIT(pin), 0); 522 break; 523 case IRQ_TYPE_EDGE_FALLING: 524 case IRQ_TYPE_LEVEL_LOW: 525 regmap_update_bits(mvchip->regs, 526 GPIO_IN_POL_OFF + mvchip->offset, 527 BIT(pin), BIT(pin)); 528 break; 529 case IRQ_TYPE_EDGE_BOTH: { 530 u32 data_in, in_pol, val; 531 532 regmap_read(mvchip->regs, 533 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 534 regmap_read(mvchip->regs, 535 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 536 537 /* 538 * set initial polarity based on current input level 539 */ 540 if ((data_in ^ in_pol) & BIT(pin)) 541 val = BIT(pin); /* falling */ 542 else 543 val = 0; /* raising */ 544 545 regmap_update_bits(mvchip->regs, 546 GPIO_IN_POL_OFF + mvchip->offset, 547 BIT(pin), val); 548 break; 549 } 550 } 551 return 0; 552 } 553 554 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 555 { 556 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 557 struct irq_chip *chip = irq_desc_get_chip(desc); 558 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 559 int i; 560 561 if (mvchip == NULL) 562 return; 563 564 chained_irq_enter(chip, desc); 565 566 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 567 level_mask = mvebu_gpio_read_level_mask(mvchip); 568 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 569 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 570 571 cause = (data_in & level_mask) | (edge_cause & edge_mask); 572 573 for (i = 0; i < mvchip->chip.ngpio; i++) { 574 int irq; 575 576 irq = irq_find_mapping(mvchip->domain, i); 577 578 if (!(cause & BIT(i))) 579 continue; 580 581 type = irq_get_trigger_type(irq); 582 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 583 /* Swap polarity (race with GPIO line) */ 584 u32 polarity; 585 586 regmap_read(mvchip->regs, 587 GPIO_IN_POL_OFF + mvchip->offset, 588 &polarity); 589 polarity ^= BIT(i); 590 regmap_write(mvchip->regs, 591 GPIO_IN_POL_OFF + mvchip->offset, 592 polarity); 593 } 594 595 generic_handle_irq(irq); 596 } 597 598 chained_irq_exit(chip, desc); 599 } 600 601 static const struct regmap_config mvebu_gpio_regmap_config = { 602 .reg_bits = 32, 603 .reg_stride = 4, 604 .val_bits = 32, 605 .fast_io = true, 606 }; 607 608 /* 609 * Functions implementing the pwm_chip methods 610 */ 611 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 612 { 613 return pwmchip_get_drvdata(chip); 614 } 615 616 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 617 { 618 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 619 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 620 struct gpio_desc *desc; 621 unsigned long flags; 622 int ret = 0; 623 624 spin_lock_irqsave(&mvpwm->lock, flags); 625 626 if (mvpwm->gpiod) { 627 ret = -EBUSY; 628 } else { 629 desc = gpiochip_request_own_desc(&mvchip->chip, 630 pwm->hwpwm, "mvebu-pwm", 631 GPIO_ACTIVE_HIGH, 632 GPIOD_OUT_LOW); 633 if (IS_ERR(desc)) { 634 ret = PTR_ERR(desc); 635 goto out; 636 } 637 638 mvpwm->gpiod = desc; 639 } 640 out: 641 spin_unlock_irqrestore(&mvpwm->lock, flags); 642 return ret; 643 } 644 645 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 646 { 647 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 648 unsigned long flags; 649 650 spin_lock_irqsave(&mvpwm->lock, flags); 651 gpiochip_free_own_desc(mvpwm->gpiod); 652 mvpwm->gpiod = NULL; 653 spin_unlock_irqrestore(&mvpwm->lock, flags); 654 } 655 656 static int mvebu_pwm_get_state(struct pwm_chip *chip, 657 struct pwm_device *pwm, 658 struct pwm_state *state) 659 { 660 661 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 662 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 663 unsigned long long val; 664 unsigned long flags; 665 u32 u; 666 667 spin_lock_irqsave(&mvpwm->lock, flags); 668 669 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); 670 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ 671 if (u > 0) 672 val = u; 673 else 674 val = UINT_MAX + 1ULL; 675 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, 676 mvpwm->clk_rate); 677 678 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); 679 /* period = on + off duration */ 680 if (u > 0) 681 val += u; 682 else 683 val += UINT_MAX + 1ULL; 684 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); 685 686 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 687 if (u) 688 state->enabled = true; 689 else 690 state->enabled = false; 691 692 spin_unlock_irqrestore(&mvpwm->lock, flags); 693 694 return 0; 695 } 696 697 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 698 const struct pwm_state *state) 699 { 700 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 701 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 702 unsigned long long val; 703 unsigned long flags; 704 unsigned int on, off; 705 706 if (state->polarity != PWM_POLARITY_NORMAL) 707 return -EINVAL; 708 709 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 710 do_div(val, NSEC_PER_SEC); 711 if (val > UINT_MAX + 1ULL) 712 return -EINVAL; 713 /* 714 * Zero on/off values don't work as expected. Experimentation shows 715 * that zero value is treated as 2^32. This behavior is not documented. 716 */ 717 if (val == UINT_MAX + 1ULL) 718 on = 0; 719 else if (val) 720 on = val; 721 else 722 on = 1; 723 724 val = (unsigned long long) mvpwm->clk_rate * state->period; 725 do_div(val, NSEC_PER_SEC); 726 val -= on; 727 if (val > UINT_MAX + 1ULL) 728 return -EINVAL; 729 if (val == UINT_MAX + 1ULL) 730 off = 0; 731 else if (val) 732 off = val; 733 else 734 off = 1; 735 736 spin_lock_irqsave(&mvpwm->lock, flags); 737 738 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); 739 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); 740 if (state->enabled) 741 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 742 else 743 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 744 745 spin_unlock_irqrestore(&mvpwm->lock, flags); 746 747 return 0; 748 } 749 750 static const struct pwm_ops mvebu_pwm_ops = { 751 .request = mvebu_pwm_request, 752 .free = mvebu_pwm_free, 753 .get_state = mvebu_pwm_get_state, 754 .apply = mvebu_pwm_apply, 755 }; 756 757 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 758 { 759 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 760 761 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 762 &mvpwm->blink_select); 763 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 764 &mvpwm->blink_on_duration); 765 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 766 &mvpwm->blink_off_duration); 767 } 768 769 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 770 { 771 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 772 773 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 774 mvpwm->blink_select); 775 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 776 mvpwm->blink_on_duration); 777 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 778 mvpwm->blink_off_duration); 779 } 780 781 static int mvebu_pwm_probe(struct platform_device *pdev, 782 struct mvebu_gpio_chip *mvchip, 783 int id) 784 { 785 struct device *dev = &pdev->dev; 786 struct mvebu_pwm *mvpwm; 787 struct pwm_chip *chip; 788 void __iomem *base; 789 u32 offset; 790 u32 set; 791 792 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 793 int ret = device_property_read_u32(dev, "marvell,pwm-offset", 794 &offset); 795 if (ret < 0) 796 return 0; 797 } else { 798 /* 799 * There are only two sets of PWM configuration registers for 800 * all the GPIO lines on those SoCs which this driver reserves 801 * for the first two GPIO chips. So if the resource is missing 802 * we can't treat it as an error. 803 */ 804 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 805 return 0; 806 offset = 0; 807 } 808 809 if (IS_ERR(mvchip->clk)) 810 return PTR_ERR(mvchip->clk); 811 812 chip = devm_pwmchip_alloc(dev, mvchip->chip.ngpio, sizeof(*mvpwm)); 813 if (IS_ERR(chip)) 814 return PTR_ERR(chip); 815 mvpwm = to_mvebu_pwm(chip); 816 817 mvchip->mvpwm = mvpwm; 818 mvpwm->mvchip = mvchip; 819 mvpwm->offset = offset; 820 821 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 822 mvpwm->regs = mvchip->regs; 823 824 switch (mvchip->offset) { 825 case AP80X_GPIO0_OFF_A8K: 826 case CP11X_GPIO0_OFF_A8K: 827 /* Blink counter A */ 828 set = 0; 829 break; 830 case CP11X_GPIO1_OFF_A8K: 831 /* Blink counter B */ 832 set = U32_MAX; 833 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; 834 break; 835 default: 836 return -EINVAL; 837 } 838 } else { 839 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); 840 if (IS_ERR(base)) 841 return PTR_ERR(base); 842 843 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, 844 &mvebu_gpio_regmap_config); 845 if (IS_ERR(mvpwm->regs)) 846 return PTR_ERR(mvpwm->regs); 847 848 /* 849 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 850 * with id 1. Don't allow further GPIO chips to be used for PWM. 851 */ 852 if (id == 0) 853 set = 0; 854 else if (id == 1) 855 set = U32_MAX; 856 else 857 return -EINVAL; 858 } 859 860 regmap_write(mvchip->regs, 861 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 862 863 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 864 if (!mvpwm->clk_rate) { 865 dev_err(dev, "failed to get clock rate\n"); 866 return -EINVAL; 867 } 868 869 chip->ops = &mvebu_pwm_ops; 870 871 spin_lock_init(&mvpwm->lock); 872 873 return devm_pwmchip_add(dev, chip); 874 } 875 876 #ifdef CONFIG_DEBUG_FS 877 #include <linux/seq_file.h> 878 879 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 880 { 881 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 882 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 883 const char *label; 884 int i; 885 886 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 887 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 888 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 889 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 890 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 891 cause = mvebu_gpio_read_edge_cause(mvchip); 892 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 893 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 894 895 for_each_requested_gpio(chip, i, label) { 896 u32 msk; 897 bool is_out; 898 899 msk = BIT(i); 900 is_out = !(io_conf & msk); 901 902 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 903 904 if (is_out) { 905 seq_printf(s, " out %s %s\n", 906 str_hi_lo(out & msk), 907 blink & msk ? "(blink )" : ""); 908 continue; 909 } 910 911 seq_printf(s, " in %s (act %s) - IRQ", 912 str_hi_lo((data_in ^ in_pol) & msk), 913 str_lo_hi(in_pol & msk)); 914 if (!((edg_msk | lvl_msk) & msk)) { 915 seq_puts(s, " disabled\n"); 916 continue; 917 } 918 if (edg_msk & msk) 919 seq_puts(s, " edge "); 920 if (lvl_msk & msk) 921 seq_puts(s, " level"); 922 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 923 } 924 } 925 #else 926 #define mvebu_gpio_dbg_show NULL 927 #endif 928 929 static const struct of_device_id mvebu_gpio_of_match[] = { 930 { 931 .compatible = "marvell,orion-gpio", 932 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 933 }, 934 { 935 .compatible = "marvell,mv78200-gpio", 936 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 937 }, 938 { 939 .compatible = "marvell,armadaxp-gpio", 940 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 941 }, 942 { 943 .compatible = "marvell,armada-370-gpio", 944 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 945 }, 946 { 947 .compatible = "marvell,armada-8k-gpio", 948 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 949 }, 950 { 951 /* sentinel */ 952 }, 953 }; 954 955 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 956 { 957 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 958 int i; 959 960 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 961 &mvchip->out_reg); 962 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 963 &mvchip->io_conf_reg); 964 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 965 &mvchip->blink_en_reg); 966 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 967 &mvchip->in_pol_reg); 968 969 switch (mvchip->soc_variant) { 970 case MVEBU_GPIO_SOC_VARIANT_ORION: 971 case MVEBU_GPIO_SOC_VARIANT_A8K: 972 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 973 &mvchip->edge_mask_regs[0]); 974 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 975 &mvchip->level_mask_regs[0]); 976 break; 977 case MVEBU_GPIO_SOC_VARIANT_MV78200: 978 for (i = 0; i < 2; i++) { 979 regmap_read(mvchip->regs, 980 GPIO_EDGE_MASK_MV78200_OFF(i), 981 &mvchip->edge_mask_regs[i]); 982 regmap_read(mvchip->regs, 983 GPIO_LEVEL_MASK_MV78200_OFF(i), 984 &mvchip->level_mask_regs[i]); 985 } 986 break; 987 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 988 for (i = 0; i < 4; i++) { 989 regmap_read(mvchip->regs, 990 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 991 &mvchip->edge_mask_regs[i]); 992 regmap_read(mvchip->regs, 993 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 994 &mvchip->level_mask_regs[i]); 995 } 996 break; 997 default: 998 BUG(); 999 } 1000 1001 if (IS_REACHABLE(CONFIG_PWM)) 1002 mvebu_pwm_suspend(mvchip); 1003 1004 return 0; 1005 } 1006 1007 static int mvebu_gpio_resume(struct platform_device *pdev) 1008 { 1009 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 1010 int i; 1011 1012 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 1013 mvchip->out_reg); 1014 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 1015 mvchip->io_conf_reg); 1016 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 1017 mvchip->blink_en_reg); 1018 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 1019 mvchip->in_pol_reg); 1020 1021 switch (mvchip->soc_variant) { 1022 case MVEBU_GPIO_SOC_VARIANT_ORION: 1023 case MVEBU_GPIO_SOC_VARIANT_A8K: 1024 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 1025 mvchip->edge_mask_regs[0]); 1026 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 1027 mvchip->level_mask_regs[0]); 1028 break; 1029 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1030 for (i = 0; i < 2; i++) { 1031 regmap_write(mvchip->regs, 1032 GPIO_EDGE_MASK_MV78200_OFF(i), 1033 mvchip->edge_mask_regs[i]); 1034 regmap_write(mvchip->regs, 1035 GPIO_LEVEL_MASK_MV78200_OFF(i), 1036 mvchip->level_mask_regs[i]); 1037 } 1038 break; 1039 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1040 for (i = 0; i < 4; i++) { 1041 regmap_write(mvchip->regs, 1042 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1043 mvchip->edge_mask_regs[i]); 1044 regmap_write(mvchip->regs, 1045 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1046 mvchip->level_mask_regs[i]); 1047 } 1048 break; 1049 default: 1050 BUG(); 1051 } 1052 1053 if (IS_REACHABLE(CONFIG_PWM)) 1054 mvebu_pwm_resume(mvchip); 1055 1056 return 0; 1057 } 1058 1059 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1060 struct mvebu_gpio_chip *mvchip) 1061 { 1062 void __iomem *base; 1063 1064 base = devm_platform_ioremap_resource(pdev, 0); 1065 if (IS_ERR(base)) 1066 return PTR_ERR(base); 1067 1068 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1069 &mvebu_gpio_regmap_config); 1070 if (IS_ERR(mvchip->regs)) 1071 return PTR_ERR(mvchip->regs); 1072 1073 /* 1074 * For the legacy SoCs, the regmap directly maps to the GPIO 1075 * registers, so no offset is needed. 1076 */ 1077 mvchip->offset = 0; 1078 1079 /* 1080 * The Armada XP has a second range of registers for the 1081 * per-CPU registers 1082 */ 1083 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1084 base = devm_platform_ioremap_resource(pdev, 1); 1085 if (IS_ERR(base)) 1086 return PTR_ERR(base); 1087 1088 mvchip->percpu_regs = 1089 devm_regmap_init_mmio(&pdev->dev, base, 1090 &mvebu_gpio_regmap_config); 1091 if (IS_ERR(mvchip->percpu_regs)) 1092 return PTR_ERR(mvchip->percpu_regs); 1093 } 1094 1095 return 0; 1096 } 1097 1098 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1099 struct mvebu_gpio_chip *mvchip) 1100 { 1101 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1102 if (IS_ERR(mvchip->regs)) 1103 return PTR_ERR(mvchip->regs); 1104 1105 if (device_property_read_u32(&pdev->dev, "offset", &mvchip->offset)) 1106 return -EINVAL; 1107 1108 return 0; 1109 } 1110 1111 static void mvebu_gpio_remove_irq_domain(void *data) 1112 { 1113 struct irq_domain *domain = data; 1114 1115 irq_domain_remove(domain); 1116 } 1117 1118 static int mvebu_gpio_probe(struct platform_device *pdev) 1119 { 1120 struct mvebu_gpio_chip *mvchip; 1121 struct device_node *np = pdev->dev.of_node; 1122 struct irq_chip_generic *gc; 1123 struct irq_chip_type *ct; 1124 unsigned int ngpios; 1125 bool have_irqs; 1126 int soc_variant; 1127 int i, cpu, id; 1128 int err; 1129 1130 soc_variant = (unsigned long)device_get_match_data(&pdev->dev); 1131 1132 /* Some gpio controllers do not provide irq support */ 1133 err = platform_irq_count(pdev); 1134 if (err < 0) 1135 return err; 1136 1137 have_irqs = err != 0; 1138 1139 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1140 GFP_KERNEL); 1141 if (!mvchip) 1142 return -ENOMEM; 1143 1144 platform_set_drvdata(pdev, mvchip); 1145 1146 if (device_property_read_u32(&pdev->dev, "ngpios", &ngpios)) { 1147 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1148 return -ENODEV; 1149 } 1150 1151 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1152 if (id < 0) { 1153 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1154 return id; 1155 } 1156 1157 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1158 /* Not all SoCs require a clock.*/ 1159 if (!IS_ERR(mvchip->clk)) 1160 clk_prepare_enable(mvchip->clk); 1161 1162 mvchip->soc_variant = soc_variant; 1163 mvchip->chip.label = dev_name(&pdev->dev); 1164 mvchip->chip.parent = &pdev->dev; 1165 mvchip->chip.request = gpiochip_generic_request; 1166 mvchip->chip.free = gpiochip_generic_free; 1167 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1168 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1169 mvchip->chip.get = mvebu_gpio_get; 1170 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1171 mvchip->chip.set = mvebu_gpio_set; 1172 if (have_irqs) 1173 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1174 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1175 mvchip->chip.ngpio = ngpios; 1176 mvchip->chip.can_sleep = false; 1177 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1178 1179 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1180 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1181 else 1182 err = mvebu_gpio_probe_raw(pdev, mvchip); 1183 1184 if (err) 1185 return err; 1186 1187 /* 1188 * Mask and clear GPIO interrupts. 1189 */ 1190 switch (soc_variant) { 1191 case MVEBU_GPIO_SOC_VARIANT_ORION: 1192 case MVEBU_GPIO_SOC_VARIANT_A8K: 1193 regmap_write(mvchip->regs, 1194 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1195 regmap_write(mvchip->regs, 1196 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1197 regmap_write(mvchip->regs, 1198 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1199 break; 1200 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1201 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1202 for (cpu = 0; cpu < 2; cpu++) { 1203 regmap_write(mvchip->regs, 1204 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1205 regmap_write(mvchip->regs, 1206 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1207 } 1208 break; 1209 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1210 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1211 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1212 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1213 for (cpu = 0; cpu < 4; cpu++) { 1214 regmap_write(mvchip->percpu_regs, 1215 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1216 regmap_write(mvchip->percpu_regs, 1217 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1218 regmap_write(mvchip->percpu_regs, 1219 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1220 } 1221 break; 1222 default: 1223 BUG(); 1224 } 1225 1226 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1227 1228 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1229 if (IS_REACHABLE(CONFIG_PWM)) { 1230 err = mvebu_pwm_probe(pdev, mvchip, id); 1231 if (err) 1232 return err; 1233 } 1234 1235 /* Some gpio controllers do not provide irq support */ 1236 if (!have_irqs) 1237 return 0; 1238 1239 mvchip->domain = irq_domain_create_linear(dev_fwnode(&pdev->dev), ngpios, 1240 &irq_generic_chip_ops, NULL); 1241 if (!mvchip->domain) { 1242 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1243 mvchip->chip.label); 1244 return -ENODEV; 1245 } 1246 1247 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, 1248 mvchip->domain); 1249 if (err) 1250 return err; 1251 1252 err = irq_alloc_domain_generic_chips( 1253 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1254 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1255 if (err) { 1256 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1257 mvchip->chip.label); 1258 return err; 1259 } 1260 1261 /* 1262 * NOTE: The common accessors cannot be used because of the percpu 1263 * access to the mask registers 1264 */ 1265 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1266 gc->private = mvchip; 1267 ct = &gc->chip_types[0]; 1268 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1269 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1270 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1271 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1272 ct->chip.name = mvchip->chip.label; 1273 1274 ct = &gc->chip_types[1]; 1275 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1276 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1277 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1278 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1279 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1280 ct->handler = handle_edge_irq; 1281 ct->chip.name = mvchip->chip.label; 1282 1283 /* 1284 * Setup the interrupt handlers. Each chip can have up to 4 1285 * interrupt handlers, with each handler dealing with 8 GPIO 1286 * pins. 1287 */ 1288 for (i = 0; i < 4; i++) { 1289 int irq = platform_get_irq_optional(pdev, i); 1290 1291 if (irq < 0) 1292 continue; 1293 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1294 mvchip); 1295 } 1296 1297 return 0; 1298 } 1299 1300 static struct platform_driver mvebu_gpio_driver = { 1301 .driver = { 1302 .name = "mvebu-gpio", 1303 .of_match_table = mvebu_gpio_of_match, 1304 }, 1305 .probe = mvebu_gpio_probe, 1306 .suspend = mvebu_gpio_suspend, 1307 .resume = mvebu_gpio_resume, 1308 }; 1309 builtin_platform_driver(mvebu_gpio_driver); 1310