1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIO driver for Marvell SoCs 4 * 5 * Copyright (C) 2012 Marvell 6 * 7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 8 * Andrew Lunn <andrew@lunn.ch> 9 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 10 * 11 * This driver is a fairly straightforward GPIO driver for the 12 * complete family of Marvell EBU SoC platforms (Orion, Dove, 13 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 14 * driver is the different register layout that exists between the 15 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 16 * platforms (MV78200 from the Discovery family and the Armada 17 * XP). Therefore, this driver handles three variants of the GPIO 18 * block: 19 * - the basic variant, called "orion-gpio", with the simplest 20 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 21 * non-SMP Discovery systems 22 * - the mv78200 variant for MV78200 Discovery systems. This variant 23 * turns the edge mask and level mask registers into CPU0 edge 24 * mask/level mask registers, and adds CPU1 edge mask/level mask 25 * registers. 26 * - the armadaxp variant for Armada XP systems. This variant keeps 27 * the normal cause/edge mask/level mask registers when the global 28 * interrupts are used, but adds per-CPU cause/edge mask/level mask 29 * registers n a separate memory area for the per-CPU GPIO 30 * interrupts. 31 */ 32 33 #include <linux/bitops.h> 34 #include <linux/clk.h> 35 #include <linux/err.h> 36 #include <linux/gpio/driver.h> 37 #include <linux/gpio/consumer.h> 38 #include <linux/gpio/machine.h> 39 #include <linux/init.h> 40 #include <linux/io.h> 41 #include <linux/irq.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqdomain.h> 44 #include <linux/mfd/syscon.h> 45 #include <linux/of.h> 46 #include <linux/pinctrl/consumer.h> 47 #include <linux/platform_device.h> 48 #include <linux/property.h> 49 #include <linux/pwm.h> 50 #include <linux/regmap.h> 51 #include <linux/slab.h> 52 53 /* 54 * GPIO unit register offsets. 55 */ 56 #define GPIO_OUT_OFF 0x0000 57 #define GPIO_IO_CONF_OFF 0x0004 58 #define GPIO_BLINK_EN_OFF 0x0008 59 #define GPIO_IN_POL_OFF 0x000c 60 #define GPIO_DATA_IN_OFF 0x0010 61 #define GPIO_EDGE_CAUSE_OFF 0x0014 62 #define GPIO_EDGE_MASK_OFF 0x0018 63 #define GPIO_LEVEL_MASK_OFF 0x001c 64 #define GPIO_BLINK_CNT_SELECT_OFF 0x0020 65 66 /* 67 * PWM register offsets. 68 */ 69 #define PWM_BLINK_ON_DURATION_OFF 0x0 70 #define PWM_BLINK_OFF_DURATION_OFF 0x4 71 #define PWM_BLINK_COUNTER_B_OFF 0x8 72 73 /* Armada 8k variant gpios register offsets */ 74 #define AP80X_GPIO0_OFF_A8K 0x1040 75 #define CP11X_GPIO0_OFF_A8K 0x100 76 #define CP11X_GPIO1_OFF_A8K 0x140 77 78 /* The MV78200 has per-CPU registers for edge mask and level mask */ 79 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 80 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 81 82 /* 83 * The Armada XP has per-CPU registers for interrupt cause, interrupt 84 * mask and interrupt level mask. Those are in percpu_regs range. 85 */ 86 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 87 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 88 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 89 90 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 91 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 92 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 93 #define MVEBU_GPIO_SOC_VARIANT_A8K 0x4 94 95 #define MVEBU_MAX_GPIO_PER_BANK 32 96 97 struct mvebu_pwm { 98 struct regmap *regs; 99 u32 offset; 100 unsigned long clk_rate; 101 struct gpio_desc *gpiod; 102 struct pwm_chip chip; 103 spinlock_t lock; 104 struct mvebu_gpio_chip *mvchip; 105 106 /* Used to preserve GPIO/PWM registers across suspend/resume */ 107 u32 blink_select; 108 u32 blink_on_duration; 109 u32 blink_off_duration; 110 }; 111 112 struct mvebu_gpio_chip { 113 struct gpio_chip chip; 114 struct regmap *regs; 115 u32 offset; 116 struct regmap *percpu_regs; 117 int irqbase; 118 struct irq_domain *domain; 119 int soc_variant; 120 121 /* Used for PWM support */ 122 struct clk *clk; 123 struct mvebu_pwm *mvpwm; 124 125 /* Used to preserve GPIO registers across suspend/resume */ 126 u32 out_reg; 127 u32 io_conf_reg; 128 u32 blink_en_reg; 129 u32 in_pol_reg; 130 u32 edge_mask_regs[4]; 131 u32 level_mask_regs[4]; 132 }; 133 134 /* 135 * Functions returning addresses of individual registers for a given 136 * GPIO controller. 137 */ 138 139 static void mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip, 140 struct regmap **map, unsigned int *offset) 141 { 142 int cpu; 143 144 switch (mvchip->soc_variant) { 145 case MVEBU_GPIO_SOC_VARIANT_ORION: 146 case MVEBU_GPIO_SOC_VARIANT_MV78200: 147 case MVEBU_GPIO_SOC_VARIANT_A8K: 148 *map = mvchip->regs; 149 *offset = GPIO_EDGE_CAUSE_OFF + mvchip->offset; 150 break; 151 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 152 cpu = smp_processor_id(); 153 *map = mvchip->percpu_regs; 154 *offset = GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 155 break; 156 default: 157 BUG(); 158 } 159 } 160 161 static u32 162 mvebu_gpio_read_edge_cause(struct mvebu_gpio_chip *mvchip) 163 { 164 struct regmap *map; 165 unsigned int offset; 166 u32 val; 167 168 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 169 regmap_read(map, offset, &val); 170 171 return val; 172 } 173 174 static void 175 mvebu_gpio_write_edge_cause(struct mvebu_gpio_chip *mvchip, u32 val) 176 { 177 struct regmap *map; 178 unsigned int offset; 179 180 mvebu_gpioreg_edge_cause(mvchip, &map, &offset); 181 regmap_write(map, offset, val); 182 } 183 184 static inline void 185 mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip, 186 struct regmap **map, unsigned int *offset) 187 { 188 int cpu; 189 190 switch (mvchip->soc_variant) { 191 case MVEBU_GPIO_SOC_VARIANT_ORION: 192 case MVEBU_GPIO_SOC_VARIANT_A8K: 193 *map = mvchip->regs; 194 *offset = GPIO_EDGE_MASK_OFF + mvchip->offset; 195 break; 196 case MVEBU_GPIO_SOC_VARIANT_MV78200: 197 cpu = smp_processor_id(); 198 *map = mvchip->regs; 199 *offset = GPIO_EDGE_MASK_MV78200_OFF(cpu); 200 break; 201 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 202 cpu = smp_processor_id(); 203 *map = mvchip->percpu_regs; 204 *offset = GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 205 break; 206 default: 207 BUG(); 208 } 209 } 210 211 static u32 212 mvebu_gpio_read_edge_mask(struct mvebu_gpio_chip *mvchip) 213 { 214 struct regmap *map; 215 unsigned int offset; 216 u32 val; 217 218 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 219 regmap_read(map, offset, &val); 220 221 return val; 222 } 223 224 static void 225 mvebu_gpio_write_edge_mask(struct mvebu_gpio_chip *mvchip, u32 val) 226 { 227 struct regmap *map; 228 unsigned int offset; 229 230 mvebu_gpioreg_edge_mask(mvchip, &map, &offset); 231 regmap_write(map, offset, val); 232 } 233 234 static void 235 mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip, 236 struct regmap **map, unsigned int *offset) 237 { 238 int cpu; 239 240 switch (mvchip->soc_variant) { 241 case MVEBU_GPIO_SOC_VARIANT_ORION: 242 case MVEBU_GPIO_SOC_VARIANT_A8K: 243 *map = mvchip->regs; 244 *offset = GPIO_LEVEL_MASK_OFF + mvchip->offset; 245 break; 246 case MVEBU_GPIO_SOC_VARIANT_MV78200: 247 cpu = smp_processor_id(); 248 *map = mvchip->regs; 249 *offset = GPIO_LEVEL_MASK_MV78200_OFF(cpu); 250 break; 251 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 252 cpu = smp_processor_id(); 253 *map = mvchip->percpu_regs; 254 *offset = GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 255 break; 256 default: 257 BUG(); 258 } 259 } 260 261 static u32 262 mvebu_gpio_read_level_mask(struct mvebu_gpio_chip *mvchip) 263 { 264 struct regmap *map; 265 unsigned int offset; 266 u32 val; 267 268 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 269 regmap_read(map, offset, &val); 270 271 return val; 272 } 273 274 static void 275 mvebu_gpio_write_level_mask(struct mvebu_gpio_chip *mvchip, u32 val) 276 { 277 struct regmap *map; 278 unsigned int offset; 279 280 mvebu_gpioreg_level_mask(mvchip, &map, &offset); 281 regmap_write(map, offset, val); 282 } 283 284 /* 285 * Functions returning offsets of individual registers for a given 286 * PWM controller. 287 */ 288 static unsigned int mvebu_pwmreg_blink_on_duration(struct mvebu_pwm *mvpwm) 289 { 290 return mvpwm->offset + PWM_BLINK_ON_DURATION_OFF; 291 } 292 293 static unsigned int mvebu_pwmreg_blink_off_duration(struct mvebu_pwm *mvpwm) 294 { 295 return mvpwm->offset + PWM_BLINK_OFF_DURATION_OFF; 296 } 297 298 /* 299 * Functions implementing the gpio_chip methods 300 */ 301 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned int pin, int value) 302 { 303 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 304 305 regmap_update_bits(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 306 BIT(pin), value ? BIT(pin) : 0); 307 } 308 309 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned int pin) 310 { 311 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 312 u32 u; 313 314 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 315 316 if (u & BIT(pin)) { 317 u32 data_in, in_pol; 318 319 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, 320 &data_in); 321 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 322 &in_pol); 323 u = data_in ^ in_pol; 324 } else { 325 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &u); 326 } 327 328 return (u >> pin) & 1; 329 } 330 331 static void mvebu_gpio_blink(struct gpio_chip *chip, unsigned int pin, 332 int value) 333 { 334 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 335 336 regmap_update_bits(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 337 BIT(pin), value ? BIT(pin) : 0); 338 } 339 340 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned int pin) 341 { 342 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 343 int ret; 344 345 /* 346 * Check with the pinctrl driver whether this pin is usable as 347 * an input GPIO 348 */ 349 ret = pinctrl_gpio_direction_input(chip, pin); 350 if (ret) 351 return ret; 352 353 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 354 BIT(pin), BIT(pin)); 355 356 return 0; 357 } 358 359 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned int pin, 360 int value) 361 { 362 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 363 int ret; 364 365 /* 366 * Check with the pinctrl driver whether this pin is usable as 367 * an output GPIO 368 */ 369 ret = pinctrl_gpio_direction_output(chip, pin); 370 if (ret) 371 return ret; 372 373 mvebu_gpio_blink(chip, pin, 0); 374 mvebu_gpio_set(chip, pin, value); 375 376 regmap_update_bits(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 377 BIT(pin), 0); 378 379 return 0; 380 } 381 382 static int mvebu_gpio_get_direction(struct gpio_chip *chip, unsigned int pin) 383 { 384 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 385 u32 u; 386 387 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 388 389 if (u & BIT(pin)) 390 return GPIO_LINE_DIRECTION_IN; 391 392 return GPIO_LINE_DIRECTION_OUT; 393 } 394 395 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned int pin) 396 { 397 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 398 399 return irq_create_mapping(mvchip->domain, pin); 400 } 401 402 /* 403 * Functions implementing the irq_chip methods 404 */ 405 static void mvebu_gpio_irq_ack(struct irq_data *d) 406 { 407 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 408 struct mvebu_gpio_chip *mvchip = gc->private; 409 u32 mask = d->mask; 410 411 irq_gc_lock(gc); 412 mvebu_gpio_write_edge_cause(mvchip, ~mask); 413 irq_gc_unlock(gc); 414 } 415 416 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 417 { 418 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 419 struct mvebu_gpio_chip *mvchip = gc->private; 420 struct irq_chip_type *ct = irq_data_get_chip_type(d); 421 u32 mask = d->mask; 422 423 irq_gc_lock(gc); 424 ct->mask_cache_priv &= ~mask; 425 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 426 irq_gc_unlock(gc); 427 } 428 429 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 430 { 431 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 432 struct mvebu_gpio_chip *mvchip = gc->private; 433 struct irq_chip_type *ct = irq_data_get_chip_type(d); 434 u32 mask = d->mask; 435 436 irq_gc_lock(gc); 437 mvebu_gpio_write_edge_cause(mvchip, ~mask); 438 ct->mask_cache_priv |= mask; 439 mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv); 440 irq_gc_unlock(gc); 441 } 442 443 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 444 { 445 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 446 struct mvebu_gpio_chip *mvchip = gc->private; 447 struct irq_chip_type *ct = irq_data_get_chip_type(d); 448 u32 mask = d->mask; 449 450 irq_gc_lock(gc); 451 ct->mask_cache_priv &= ~mask; 452 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 453 irq_gc_unlock(gc); 454 } 455 456 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 457 { 458 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 459 struct mvebu_gpio_chip *mvchip = gc->private; 460 struct irq_chip_type *ct = irq_data_get_chip_type(d); 461 u32 mask = d->mask; 462 463 irq_gc_lock(gc); 464 ct->mask_cache_priv |= mask; 465 mvebu_gpio_write_level_mask(mvchip, ct->mask_cache_priv); 466 irq_gc_unlock(gc); 467 } 468 469 /***************************************************************************** 470 * MVEBU GPIO IRQ 471 * 472 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 473 * value of the line or the opposite value. 474 * 475 * Level IRQ handlers: DATA_IN is used directly as cause register. 476 * Interrupt are masked by LEVEL_MASK registers. 477 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 478 * Interrupt are masked by EDGE_MASK registers. 479 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 480 * the polarity to catch the next line transaction. 481 * This is a race condition that might not perfectly 482 * work on some use cases. 483 * 484 * Every eight GPIO lines are grouped (OR'ed) before going up to main 485 * cause register. 486 * 487 * EDGE cause mask 488 * data-in /--------| |-----| |----\ 489 * -----| |----- ---- to main cause reg 490 * X \----------------| |----/ 491 * polarity LEVEL mask 492 * 493 ****************************************************************************/ 494 495 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 496 { 497 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 498 struct irq_chip_type *ct = irq_data_get_chip_type(d); 499 struct mvebu_gpio_chip *mvchip = gc->private; 500 int pin; 501 u32 u; 502 503 pin = d->hwirq; 504 505 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &u); 506 if ((u & BIT(pin)) == 0) 507 return -EINVAL; 508 509 type &= IRQ_TYPE_SENSE_MASK; 510 if (type == IRQ_TYPE_NONE) 511 return -EINVAL; 512 513 /* Check if we need to change chip and handler */ 514 if (!(ct->type & type)) 515 if (irq_setup_alt_chip(d, type)) 516 return -EINVAL; 517 518 /* 519 * Configure interrupt polarity. 520 */ 521 switch (type) { 522 case IRQ_TYPE_EDGE_RISING: 523 case IRQ_TYPE_LEVEL_HIGH: 524 regmap_update_bits(mvchip->regs, 525 GPIO_IN_POL_OFF + mvchip->offset, 526 BIT(pin), 0); 527 break; 528 case IRQ_TYPE_EDGE_FALLING: 529 case IRQ_TYPE_LEVEL_LOW: 530 regmap_update_bits(mvchip->regs, 531 GPIO_IN_POL_OFF + mvchip->offset, 532 BIT(pin), BIT(pin)); 533 break; 534 case IRQ_TYPE_EDGE_BOTH: { 535 u32 data_in, in_pol, val; 536 537 regmap_read(mvchip->regs, 538 GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 539 regmap_read(mvchip->regs, 540 GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 541 542 /* 543 * set initial polarity based on current input level 544 */ 545 if ((data_in ^ in_pol) & BIT(pin)) 546 val = BIT(pin); /* falling */ 547 else 548 val = 0; /* raising */ 549 550 regmap_update_bits(mvchip->regs, 551 GPIO_IN_POL_OFF + mvchip->offset, 552 BIT(pin), val); 553 break; 554 } 555 } 556 return 0; 557 } 558 559 static void mvebu_gpio_irq_handler(struct irq_desc *desc) 560 { 561 struct mvebu_gpio_chip *mvchip = irq_desc_get_handler_data(desc); 562 struct irq_chip *chip = irq_desc_get_chip(desc); 563 u32 cause, type, data_in, level_mask, edge_cause, edge_mask; 564 int i; 565 566 if (mvchip == NULL) 567 return; 568 569 chained_irq_enter(chip, desc); 570 571 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 572 level_mask = mvebu_gpio_read_level_mask(mvchip); 573 edge_cause = mvebu_gpio_read_edge_cause(mvchip); 574 edge_mask = mvebu_gpio_read_edge_mask(mvchip); 575 576 cause = (data_in & level_mask) | (edge_cause & edge_mask); 577 578 for (i = 0; i < mvchip->chip.ngpio; i++) { 579 int irq; 580 581 irq = irq_find_mapping(mvchip->domain, i); 582 583 if (!(cause & BIT(i))) 584 continue; 585 586 type = irq_get_trigger_type(irq); 587 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 588 /* Swap polarity (race with GPIO line) */ 589 u32 polarity; 590 591 regmap_read(mvchip->regs, 592 GPIO_IN_POL_OFF + mvchip->offset, 593 &polarity); 594 polarity ^= BIT(i); 595 regmap_write(mvchip->regs, 596 GPIO_IN_POL_OFF + mvchip->offset, 597 polarity); 598 } 599 600 generic_handle_irq(irq); 601 } 602 603 chained_irq_exit(chip, desc); 604 } 605 606 static const struct regmap_config mvebu_gpio_regmap_config = { 607 .reg_bits = 32, 608 .reg_stride = 4, 609 .val_bits = 32, 610 .fast_io = true, 611 }; 612 613 /* 614 * Functions implementing the pwm_chip methods 615 */ 616 static struct mvebu_pwm *to_mvebu_pwm(struct pwm_chip *chip) 617 { 618 return container_of(chip, struct mvebu_pwm, chip); 619 } 620 621 static int mvebu_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 622 { 623 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 624 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 625 struct gpio_desc *desc; 626 unsigned long flags; 627 int ret = 0; 628 629 spin_lock_irqsave(&mvpwm->lock, flags); 630 631 if (mvpwm->gpiod) { 632 ret = -EBUSY; 633 } else { 634 desc = gpiochip_request_own_desc(&mvchip->chip, 635 pwm->hwpwm, "mvebu-pwm", 636 GPIO_ACTIVE_HIGH, 637 GPIOD_OUT_LOW); 638 if (IS_ERR(desc)) { 639 ret = PTR_ERR(desc); 640 goto out; 641 } 642 643 mvpwm->gpiod = desc; 644 } 645 out: 646 spin_unlock_irqrestore(&mvpwm->lock, flags); 647 return ret; 648 } 649 650 static void mvebu_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 651 { 652 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 653 unsigned long flags; 654 655 spin_lock_irqsave(&mvpwm->lock, flags); 656 gpiochip_free_own_desc(mvpwm->gpiod); 657 mvpwm->gpiod = NULL; 658 spin_unlock_irqrestore(&mvpwm->lock, flags); 659 } 660 661 static int mvebu_pwm_get_state(struct pwm_chip *chip, 662 struct pwm_device *pwm, 663 struct pwm_state *state) 664 { 665 666 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 667 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 668 unsigned long long val; 669 unsigned long flags; 670 u32 u; 671 672 spin_lock_irqsave(&mvpwm->lock, flags); 673 674 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), &u); 675 /* Hardware treats zero as 2^32. See mvebu_pwm_apply(). */ 676 if (u > 0) 677 val = u; 678 else 679 val = UINT_MAX + 1ULL; 680 state->duty_cycle = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, 681 mvpwm->clk_rate); 682 683 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), &u); 684 /* period = on + off duration */ 685 if (u > 0) 686 val += u; 687 else 688 val += UINT_MAX + 1ULL; 689 state->period = DIV_ROUND_UP_ULL(val * NSEC_PER_SEC, mvpwm->clk_rate); 690 691 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &u); 692 if (u) 693 state->enabled = true; 694 else 695 state->enabled = false; 696 697 spin_unlock_irqrestore(&mvpwm->lock, flags); 698 699 return 0; 700 } 701 702 static int mvebu_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 703 const struct pwm_state *state) 704 { 705 struct mvebu_pwm *mvpwm = to_mvebu_pwm(chip); 706 struct mvebu_gpio_chip *mvchip = mvpwm->mvchip; 707 unsigned long long val; 708 unsigned long flags; 709 unsigned int on, off; 710 711 if (state->polarity != PWM_POLARITY_NORMAL) 712 return -EINVAL; 713 714 val = (unsigned long long) mvpwm->clk_rate * state->duty_cycle; 715 do_div(val, NSEC_PER_SEC); 716 if (val > UINT_MAX + 1ULL) 717 return -EINVAL; 718 /* 719 * Zero on/off values don't work as expected. Experimentation shows 720 * that zero value is treated as 2^32. This behavior is not documented. 721 */ 722 if (val == UINT_MAX + 1ULL) 723 on = 0; 724 else if (val) 725 on = val; 726 else 727 on = 1; 728 729 val = (unsigned long long) mvpwm->clk_rate * state->period; 730 do_div(val, NSEC_PER_SEC); 731 val -= on; 732 if (val > UINT_MAX + 1ULL) 733 return -EINVAL; 734 if (val == UINT_MAX + 1ULL) 735 off = 0; 736 else if (val) 737 off = val; 738 else 739 off = 1; 740 741 spin_lock_irqsave(&mvpwm->lock, flags); 742 743 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), on); 744 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), off); 745 if (state->enabled) 746 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 1); 747 else 748 mvebu_gpio_blink(&mvchip->chip, pwm->hwpwm, 0); 749 750 spin_unlock_irqrestore(&mvpwm->lock, flags); 751 752 return 0; 753 } 754 755 static const struct pwm_ops mvebu_pwm_ops = { 756 .request = mvebu_pwm_request, 757 .free = mvebu_pwm_free, 758 .get_state = mvebu_pwm_get_state, 759 .apply = mvebu_pwm_apply, 760 }; 761 762 static void __maybe_unused mvebu_pwm_suspend(struct mvebu_gpio_chip *mvchip) 763 { 764 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 765 766 regmap_read(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 767 &mvpwm->blink_select); 768 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 769 &mvpwm->blink_on_duration); 770 regmap_read(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 771 &mvpwm->blink_off_duration); 772 } 773 774 static void __maybe_unused mvebu_pwm_resume(struct mvebu_gpio_chip *mvchip) 775 { 776 struct mvebu_pwm *mvpwm = mvchip->mvpwm; 777 778 regmap_write(mvchip->regs, GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, 779 mvpwm->blink_select); 780 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_on_duration(mvpwm), 781 mvpwm->blink_on_duration); 782 regmap_write(mvpwm->regs, mvebu_pwmreg_blink_off_duration(mvpwm), 783 mvpwm->blink_off_duration); 784 } 785 786 static int mvebu_pwm_probe(struct platform_device *pdev, 787 struct mvebu_gpio_chip *mvchip, 788 int id) 789 { 790 struct device *dev = &pdev->dev; 791 struct mvebu_pwm *mvpwm; 792 void __iomem *base; 793 u32 offset; 794 u32 set; 795 796 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 797 int ret = of_property_read_u32(dev->of_node, 798 "marvell,pwm-offset", &offset); 799 if (ret < 0) 800 return 0; 801 } else { 802 /* 803 * There are only two sets of PWM configuration registers for 804 * all the GPIO lines on those SoCs which this driver reserves 805 * for the first two GPIO chips. So if the resource is missing 806 * we can't treat it as an error. 807 */ 808 if (!platform_get_resource_byname(pdev, IORESOURCE_MEM, "pwm")) 809 return 0; 810 offset = 0; 811 } 812 813 if (IS_ERR(mvchip->clk)) 814 return PTR_ERR(mvchip->clk); 815 816 mvpwm = devm_kzalloc(dev, sizeof(struct mvebu_pwm), GFP_KERNEL); 817 if (!mvpwm) 818 return -ENOMEM; 819 mvchip->mvpwm = mvpwm; 820 mvpwm->mvchip = mvchip; 821 mvpwm->offset = offset; 822 823 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) { 824 mvpwm->regs = mvchip->regs; 825 826 switch (mvchip->offset) { 827 case AP80X_GPIO0_OFF_A8K: 828 case CP11X_GPIO0_OFF_A8K: 829 /* Blink counter A */ 830 set = 0; 831 break; 832 case CP11X_GPIO1_OFF_A8K: 833 /* Blink counter B */ 834 set = U32_MAX; 835 mvpwm->offset += PWM_BLINK_COUNTER_B_OFF; 836 break; 837 default: 838 return -EINVAL; 839 } 840 } else { 841 base = devm_platform_ioremap_resource_byname(pdev, "pwm"); 842 if (IS_ERR(base)) 843 return PTR_ERR(base); 844 845 mvpwm->regs = devm_regmap_init_mmio(&pdev->dev, base, 846 &mvebu_gpio_regmap_config); 847 if (IS_ERR(mvpwm->regs)) 848 return PTR_ERR(mvpwm->regs); 849 850 /* 851 * Use set A for lines of GPIO chip with id 0, B for GPIO chip 852 * with id 1. Don't allow further GPIO chips to be used for PWM. 853 */ 854 if (id == 0) 855 set = 0; 856 else if (id == 1) 857 set = U32_MAX; 858 else 859 return -EINVAL; 860 } 861 862 regmap_write(mvchip->regs, 863 GPIO_BLINK_CNT_SELECT_OFF + mvchip->offset, set); 864 865 mvpwm->clk_rate = clk_get_rate(mvchip->clk); 866 if (!mvpwm->clk_rate) { 867 dev_err(dev, "failed to get clock rate\n"); 868 return -EINVAL; 869 } 870 871 mvpwm->chip.dev = dev; 872 mvpwm->chip.ops = &mvebu_pwm_ops; 873 mvpwm->chip.npwm = mvchip->chip.ngpio; 874 875 spin_lock_init(&mvpwm->lock); 876 877 return devm_pwmchip_add(dev, &mvpwm->chip); 878 } 879 880 #ifdef CONFIG_DEBUG_FS 881 #include <linux/seq_file.h> 882 883 static void mvebu_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) 884 { 885 struct mvebu_gpio_chip *mvchip = gpiochip_get_data(chip); 886 u32 out, io_conf, blink, in_pol, data_in, cause, edg_msk, lvl_msk; 887 const char *label; 888 int i; 889 890 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, &out); 891 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, &io_conf); 892 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, &blink); 893 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, &in_pol); 894 regmap_read(mvchip->regs, GPIO_DATA_IN_OFF + mvchip->offset, &data_in); 895 cause = mvebu_gpio_read_edge_cause(mvchip); 896 edg_msk = mvebu_gpio_read_edge_mask(mvchip); 897 lvl_msk = mvebu_gpio_read_level_mask(mvchip); 898 899 for_each_requested_gpio(chip, i, label) { 900 u32 msk; 901 bool is_out; 902 903 msk = BIT(i); 904 is_out = !(io_conf & msk); 905 906 seq_printf(s, " gpio-%-3d (%-20.20s)", chip->base + i, label); 907 908 if (is_out) { 909 seq_printf(s, " out %s %s\n", 910 out & msk ? "hi" : "lo", 911 blink & msk ? "(blink )" : ""); 912 continue; 913 } 914 915 seq_printf(s, " in %s (act %s) - IRQ", 916 (data_in ^ in_pol) & msk ? "hi" : "lo", 917 in_pol & msk ? "lo" : "hi"); 918 if (!((edg_msk | lvl_msk) & msk)) { 919 seq_puts(s, " disabled\n"); 920 continue; 921 } 922 if (edg_msk & msk) 923 seq_puts(s, " edge "); 924 if (lvl_msk & msk) 925 seq_puts(s, " level"); 926 seq_printf(s, " (%s)\n", cause & msk ? "pending" : "clear "); 927 } 928 } 929 #else 930 #define mvebu_gpio_dbg_show NULL 931 #endif 932 933 static const struct of_device_id mvebu_gpio_of_match[] = { 934 { 935 .compatible = "marvell,orion-gpio", 936 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 937 }, 938 { 939 .compatible = "marvell,mv78200-gpio", 940 .data = (void *) MVEBU_GPIO_SOC_VARIANT_MV78200, 941 }, 942 { 943 .compatible = "marvell,armadaxp-gpio", 944 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 945 }, 946 { 947 .compatible = "marvell,armada-370-gpio", 948 .data = (void *) MVEBU_GPIO_SOC_VARIANT_ORION, 949 }, 950 { 951 .compatible = "marvell,armada-8k-gpio", 952 .data = (void *) MVEBU_GPIO_SOC_VARIANT_A8K, 953 }, 954 { 955 /* sentinel */ 956 }, 957 }; 958 959 static int mvebu_gpio_suspend(struct platform_device *pdev, pm_message_t state) 960 { 961 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 962 int i; 963 964 regmap_read(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 965 &mvchip->out_reg); 966 regmap_read(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 967 &mvchip->io_conf_reg); 968 regmap_read(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 969 &mvchip->blink_en_reg); 970 regmap_read(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 971 &mvchip->in_pol_reg); 972 973 switch (mvchip->soc_variant) { 974 case MVEBU_GPIO_SOC_VARIANT_ORION: 975 case MVEBU_GPIO_SOC_VARIANT_A8K: 976 regmap_read(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 977 &mvchip->edge_mask_regs[0]); 978 regmap_read(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 979 &mvchip->level_mask_regs[0]); 980 break; 981 case MVEBU_GPIO_SOC_VARIANT_MV78200: 982 for (i = 0; i < 2; i++) { 983 regmap_read(mvchip->regs, 984 GPIO_EDGE_MASK_MV78200_OFF(i), 985 &mvchip->edge_mask_regs[i]); 986 regmap_read(mvchip->regs, 987 GPIO_LEVEL_MASK_MV78200_OFF(i), 988 &mvchip->level_mask_regs[i]); 989 } 990 break; 991 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 992 for (i = 0; i < 4; i++) { 993 regmap_read(mvchip->regs, 994 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 995 &mvchip->edge_mask_regs[i]); 996 regmap_read(mvchip->regs, 997 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 998 &mvchip->level_mask_regs[i]); 999 } 1000 break; 1001 default: 1002 BUG(); 1003 } 1004 1005 if (IS_REACHABLE(CONFIG_PWM)) 1006 mvebu_pwm_suspend(mvchip); 1007 1008 return 0; 1009 } 1010 1011 static int mvebu_gpio_resume(struct platform_device *pdev) 1012 { 1013 struct mvebu_gpio_chip *mvchip = platform_get_drvdata(pdev); 1014 int i; 1015 1016 regmap_write(mvchip->regs, GPIO_OUT_OFF + mvchip->offset, 1017 mvchip->out_reg); 1018 regmap_write(mvchip->regs, GPIO_IO_CONF_OFF + mvchip->offset, 1019 mvchip->io_conf_reg); 1020 regmap_write(mvchip->regs, GPIO_BLINK_EN_OFF + mvchip->offset, 1021 mvchip->blink_en_reg); 1022 regmap_write(mvchip->regs, GPIO_IN_POL_OFF + mvchip->offset, 1023 mvchip->in_pol_reg); 1024 1025 switch (mvchip->soc_variant) { 1026 case MVEBU_GPIO_SOC_VARIANT_ORION: 1027 case MVEBU_GPIO_SOC_VARIANT_A8K: 1028 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF + mvchip->offset, 1029 mvchip->edge_mask_regs[0]); 1030 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF + mvchip->offset, 1031 mvchip->level_mask_regs[0]); 1032 break; 1033 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1034 for (i = 0; i < 2; i++) { 1035 regmap_write(mvchip->regs, 1036 GPIO_EDGE_MASK_MV78200_OFF(i), 1037 mvchip->edge_mask_regs[i]); 1038 regmap_write(mvchip->regs, 1039 GPIO_LEVEL_MASK_MV78200_OFF(i), 1040 mvchip->level_mask_regs[i]); 1041 } 1042 break; 1043 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1044 for (i = 0; i < 4; i++) { 1045 regmap_write(mvchip->regs, 1046 GPIO_EDGE_MASK_ARMADAXP_OFF(i), 1047 mvchip->edge_mask_regs[i]); 1048 regmap_write(mvchip->regs, 1049 GPIO_LEVEL_MASK_ARMADAXP_OFF(i), 1050 mvchip->level_mask_regs[i]); 1051 } 1052 break; 1053 default: 1054 BUG(); 1055 } 1056 1057 if (IS_REACHABLE(CONFIG_PWM)) 1058 mvebu_pwm_resume(mvchip); 1059 1060 return 0; 1061 } 1062 1063 static int mvebu_gpio_probe_raw(struct platform_device *pdev, 1064 struct mvebu_gpio_chip *mvchip) 1065 { 1066 void __iomem *base; 1067 1068 base = devm_platform_ioremap_resource(pdev, 0); 1069 if (IS_ERR(base)) 1070 return PTR_ERR(base); 1071 1072 mvchip->regs = devm_regmap_init_mmio(&pdev->dev, base, 1073 &mvebu_gpio_regmap_config); 1074 if (IS_ERR(mvchip->regs)) 1075 return PTR_ERR(mvchip->regs); 1076 1077 /* 1078 * For the legacy SoCs, the regmap directly maps to the GPIO 1079 * registers, so no offset is needed. 1080 */ 1081 mvchip->offset = 0; 1082 1083 /* 1084 * The Armada XP has a second range of registers for the 1085 * per-CPU registers 1086 */ 1087 if (mvchip->soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 1088 base = devm_platform_ioremap_resource(pdev, 1); 1089 if (IS_ERR(base)) 1090 return PTR_ERR(base); 1091 1092 mvchip->percpu_regs = 1093 devm_regmap_init_mmio(&pdev->dev, base, 1094 &mvebu_gpio_regmap_config); 1095 if (IS_ERR(mvchip->percpu_regs)) 1096 return PTR_ERR(mvchip->percpu_regs); 1097 } 1098 1099 return 0; 1100 } 1101 1102 static int mvebu_gpio_probe_syscon(struct platform_device *pdev, 1103 struct mvebu_gpio_chip *mvchip) 1104 { 1105 mvchip->regs = syscon_node_to_regmap(pdev->dev.parent->of_node); 1106 if (IS_ERR(mvchip->regs)) 1107 return PTR_ERR(mvchip->regs); 1108 1109 if (of_property_read_u32(pdev->dev.of_node, "offset", &mvchip->offset)) 1110 return -EINVAL; 1111 1112 return 0; 1113 } 1114 1115 static void mvebu_gpio_remove_irq_domain(void *data) 1116 { 1117 struct irq_domain *domain = data; 1118 1119 irq_domain_remove(domain); 1120 } 1121 1122 static int mvebu_gpio_probe(struct platform_device *pdev) 1123 { 1124 struct mvebu_gpio_chip *mvchip; 1125 struct device_node *np = pdev->dev.of_node; 1126 struct irq_chip_generic *gc; 1127 struct irq_chip_type *ct; 1128 unsigned int ngpios; 1129 bool have_irqs; 1130 int soc_variant; 1131 int i, cpu, id; 1132 int err; 1133 1134 soc_variant = (unsigned long)device_get_match_data(&pdev->dev); 1135 1136 /* Some gpio controllers do not provide irq support */ 1137 err = platform_irq_count(pdev); 1138 if (err < 0) 1139 return err; 1140 1141 have_irqs = err != 0; 1142 1143 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), 1144 GFP_KERNEL); 1145 if (!mvchip) 1146 return -ENOMEM; 1147 1148 platform_set_drvdata(pdev, mvchip); 1149 1150 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 1151 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 1152 return -ENODEV; 1153 } 1154 1155 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 1156 if (id < 0) { 1157 dev_err(&pdev->dev, "Couldn't get OF id\n"); 1158 return id; 1159 } 1160 1161 mvchip->clk = devm_clk_get(&pdev->dev, NULL); 1162 /* Not all SoCs require a clock.*/ 1163 if (!IS_ERR(mvchip->clk)) 1164 clk_prepare_enable(mvchip->clk); 1165 1166 mvchip->soc_variant = soc_variant; 1167 mvchip->chip.label = dev_name(&pdev->dev); 1168 mvchip->chip.parent = &pdev->dev; 1169 mvchip->chip.request = gpiochip_generic_request; 1170 mvchip->chip.free = gpiochip_generic_free; 1171 mvchip->chip.get_direction = mvebu_gpio_get_direction; 1172 mvchip->chip.direction_input = mvebu_gpio_direction_input; 1173 mvchip->chip.get = mvebu_gpio_get; 1174 mvchip->chip.direction_output = mvebu_gpio_direction_output; 1175 mvchip->chip.set = mvebu_gpio_set; 1176 if (have_irqs) 1177 mvchip->chip.to_irq = mvebu_gpio_to_irq; 1178 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 1179 mvchip->chip.ngpio = ngpios; 1180 mvchip->chip.can_sleep = false; 1181 mvchip->chip.dbg_show = mvebu_gpio_dbg_show; 1182 1183 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_A8K) 1184 err = mvebu_gpio_probe_syscon(pdev, mvchip); 1185 else 1186 err = mvebu_gpio_probe_raw(pdev, mvchip); 1187 1188 if (err) 1189 return err; 1190 1191 /* 1192 * Mask and clear GPIO interrupts. 1193 */ 1194 switch (soc_variant) { 1195 case MVEBU_GPIO_SOC_VARIANT_ORION: 1196 case MVEBU_GPIO_SOC_VARIANT_A8K: 1197 regmap_write(mvchip->regs, 1198 GPIO_EDGE_CAUSE_OFF + mvchip->offset, 0); 1199 regmap_write(mvchip->regs, 1200 GPIO_EDGE_MASK_OFF + mvchip->offset, 0); 1201 regmap_write(mvchip->regs, 1202 GPIO_LEVEL_MASK_OFF + mvchip->offset, 0); 1203 break; 1204 case MVEBU_GPIO_SOC_VARIANT_MV78200: 1205 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1206 for (cpu = 0; cpu < 2; cpu++) { 1207 regmap_write(mvchip->regs, 1208 GPIO_EDGE_MASK_MV78200_OFF(cpu), 0); 1209 regmap_write(mvchip->regs, 1210 GPIO_LEVEL_MASK_MV78200_OFF(cpu), 0); 1211 } 1212 break; 1213 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 1214 regmap_write(mvchip->regs, GPIO_EDGE_CAUSE_OFF, 0); 1215 regmap_write(mvchip->regs, GPIO_EDGE_MASK_OFF, 0); 1216 regmap_write(mvchip->regs, GPIO_LEVEL_MASK_OFF, 0); 1217 for (cpu = 0; cpu < 4; cpu++) { 1218 regmap_write(mvchip->percpu_regs, 1219 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu), 0); 1220 regmap_write(mvchip->percpu_regs, 1221 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu), 0); 1222 regmap_write(mvchip->percpu_regs, 1223 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu), 0); 1224 } 1225 break; 1226 default: 1227 BUG(); 1228 } 1229 1230 devm_gpiochip_add_data(&pdev->dev, &mvchip->chip, mvchip); 1231 1232 /* Some MVEBU SoCs have simple PWM support for GPIO lines */ 1233 if (IS_REACHABLE(CONFIG_PWM)) { 1234 err = mvebu_pwm_probe(pdev, mvchip, id); 1235 if (err) 1236 return err; 1237 } 1238 1239 /* Some gpio controllers do not provide irq support */ 1240 if (!have_irqs) 1241 return 0; 1242 1243 mvchip->domain = 1244 irq_domain_add_linear(np, ngpios, &irq_generic_chip_ops, NULL); 1245 if (!mvchip->domain) { 1246 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 1247 mvchip->chip.label); 1248 return -ENODEV; 1249 } 1250 1251 err = devm_add_action_or_reset(&pdev->dev, mvebu_gpio_remove_irq_domain, 1252 mvchip->domain); 1253 if (err) 1254 return err; 1255 1256 err = irq_alloc_domain_generic_chips( 1257 mvchip->domain, ngpios, 2, np->name, handle_level_irq, 1258 IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_LEVEL, 0, 0); 1259 if (err) { 1260 dev_err(&pdev->dev, "couldn't allocate irq chips %s (DT).\n", 1261 mvchip->chip.label); 1262 return err; 1263 } 1264 1265 /* 1266 * NOTE: The common accessors cannot be used because of the percpu 1267 * access to the mask registers 1268 */ 1269 gc = irq_get_domain_generic_chip(mvchip->domain, 0); 1270 gc->private = mvchip; 1271 ct = &gc->chip_types[0]; 1272 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 1273 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 1274 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 1275 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1276 ct->chip.name = mvchip->chip.label; 1277 1278 ct = &gc->chip_types[1]; 1279 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 1280 ct->chip.irq_ack = mvebu_gpio_irq_ack; 1281 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 1282 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 1283 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 1284 ct->handler = handle_edge_irq; 1285 ct->chip.name = mvchip->chip.label; 1286 1287 /* 1288 * Setup the interrupt handlers. Each chip can have up to 4 1289 * interrupt handlers, with each handler dealing with 8 GPIO 1290 * pins. 1291 */ 1292 for (i = 0; i < 4; i++) { 1293 int irq = platform_get_irq_optional(pdev, i); 1294 1295 if (irq < 0) 1296 continue; 1297 irq_set_chained_handler_and_data(irq, mvebu_gpio_irq_handler, 1298 mvchip); 1299 } 1300 1301 return 0; 1302 } 1303 1304 static struct platform_driver mvebu_gpio_driver = { 1305 .driver = { 1306 .name = "mvebu-gpio", 1307 .of_match_table = mvebu_gpio_of_match, 1308 }, 1309 .probe = mvebu_gpio_probe, 1310 .suspend = mvebu_gpio_suspend, 1311 .resume = mvebu_gpio_resume, 1312 }; 1313 builtin_platform_driver(mvebu_gpio_driver); 1314