1 /* 2 * GPIO driver for Marvell SoCs 3 * 4 * Copyright (C) 2012 Marvell 5 * 6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 7 * Andrew Lunn <andrew@lunn.ch> 8 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> 9 * 10 * This file is licensed under the terms of the GNU General Public 11 * License version 2. This program is licensed "as is" without any 12 * warranty of any kind, whether express or implied. 13 * 14 * This driver is a fairly straightforward GPIO driver for the 15 * complete family of Marvell EBU SoC platforms (Orion, Dove, 16 * Kirkwood, Discovery, Armada 370/XP). The only complexity of this 17 * driver is the different register layout that exists between the 18 * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP 19 * platforms (MV78200 from the Discovery family and the Armada 20 * XP). Therefore, this driver handles three variants of the GPIO 21 * block: 22 * - the basic variant, called "orion-gpio", with the simplest 23 * register set. Used on Orion, Dove, Kirkwoord, Armada 370 and 24 * non-SMP Discovery systems 25 * - the mv78200 variant for MV78200 Discovery systems. This variant 26 * turns the edge mask and level mask registers into CPU0 edge 27 * mask/level mask registers, and adds CPU1 edge mask/level mask 28 * registers. 29 * - the armadaxp variant for Armada XP systems. This variant keeps 30 * the normal cause/edge mask/level mask registers when the global 31 * interrupts are used, but adds per-CPU cause/edge mask/level mask 32 * registers n a separate memory area for the per-CPU GPIO 33 * interrupts. 34 */ 35 36 #include <linux/module.h> 37 #include <linux/gpio.h> 38 #include <linux/irq.h> 39 #include <linux/slab.h> 40 #include <linux/irqdomain.h> 41 #include <linux/io.h> 42 #include <linux/of_irq.h> 43 #include <linux/of_device.h> 44 #include <linux/platform_device.h> 45 #include <linux/pinctrl/consumer.h> 46 47 /* 48 * GPIO unit register offsets. 49 */ 50 #define GPIO_OUT_OFF 0x0000 51 #define GPIO_IO_CONF_OFF 0x0004 52 #define GPIO_BLINK_EN_OFF 0x0008 53 #define GPIO_IN_POL_OFF 0x000c 54 #define GPIO_DATA_IN_OFF 0x0010 55 #define GPIO_EDGE_CAUSE_OFF 0x0014 56 #define GPIO_EDGE_MASK_OFF 0x0018 57 #define GPIO_LEVEL_MASK_OFF 0x001c 58 59 /* The MV78200 has per-CPU registers for edge mask and level mask */ 60 #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) 61 #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) 62 63 /* The Armada XP has per-CPU registers for interrupt cause, interrupt 64 * mask and interrupt level mask. Those are relative to the 65 * percpu_membase. */ 66 #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) 67 #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) 68 #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) 69 70 #define MVEBU_GPIO_SOC_VARIANT_ORION 0x1 71 #define MVEBU_GPIO_SOC_VARIANT_MV78200 0x2 72 #define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3 73 74 #define MVEBU_MAX_GPIO_PER_BANK 32 75 76 struct mvebu_gpio_chip { 77 struct gpio_chip chip; 78 spinlock_t lock; 79 void __iomem *membase; 80 void __iomem *percpu_membase; 81 unsigned int irqbase; 82 struct irq_domain *domain; 83 int soc_variant; 84 }; 85 86 /* 87 * Functions returning addresses of individual registers for a given 88 * GPIO controller. 89 */ 90 static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip) 91 { 92 return mvchip->membase + GPIO_OUT_OFF; 93 } 94 95 static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip) 96 { 97 return mvchip->membase + GPIO_IO_CONF_OFF; 98 } 99 100 static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip) 101 { 102 return mvchip->membase + GPIO_IN_POL_OFF; 103 } 104 105 static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip) 106 { 107 return mvchip->membase + GPIO_DATA_IN_OFF; 108 } 109 110 static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip) 111 { 112 int cpu; 113 114 switch(mvchip->soc_variant) { 115 case MVEBU_GPIO_SOC_VARIANT_ORION: 116 case MVEBU_GPIO_SOC_VARIANT_MV78200: 117 return mvchip->membase + GPIO_EDGE_CAUSE_OFF; 118 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 119 cpu = smp_processor_id(); 120 return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu); 121 default: 122 BUG(); 123 } 124 } 125 126 static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip) 127 { 128 int cpu; 129 130 switch(mvchip->soc_variant) { 131 case MVEBU_GPIO_SOC_VARIANT_ORION: 132 return mvchip->membase + GPIO_EDGE_MASK_OFF; 133 case MVEBU_GPIO_SOC_VARIANT_MV78200: 134 cpu = smp_processor_id(); 135 return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu); 136 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 137 cpu = smp_processor_id(); 138 return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu); 139 default: 140 BUG(); 141 } 142 } 143 144 static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip) 145 { 146 int cpu; 147 148 switch(mvchip->soc_variant) { 149 case MVEBU_GPIO_SOC_VARIANT_ORION: 150 return mvchip->membase + GPIO_LEVEL_MASK_OFF; 151 case MVEBU_GPIO_SOC_VARIANT_MV78200: 152 cpu = smp_processor_id(); 153 return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu); 154 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 155 cpu = smp_processor_id(); 156 return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu); 157 default: 158 BUG(); 159 } 160 } 161 162 /* 163 * Functions implementing the gpio_chip methods 164 */ 165 166 int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin) 167 { 168 return pinctrl_request_gpio(chip->base + pin); 169 } 170 171 void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin) 172 { 173 pinctrl_free_gpio(chip->base + pin); 174 } 175 176 static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value) 177 { 178 struct mvebu_gpio_chip *mvchip = 179 container_of(chip, struct mvebu_gpio_chip, chip); 180 unsigned long flags; 181 u32 u; 182 183 spin_lock_irqsave(&mvchip->lock, flags); 184 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 185 if (value) 186 u |= 1 << pin; 187 else 188 u &= ~(1 << pin); 189 writel_relaxed(u, mvebu_gpioreg_out(mvchip)); 190 spin_unlock_irqrestore(&mvchip->lock, flags); 191 } 192 193 static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin) 194 { 195 struct mvebu_gpio_chip *mvchip = 196 container_of(chip, struct mvebu_gpio_chip, chip); 197 u32 u; 198 199 if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) { 200 u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^ 201 readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 202 } else { 203 u = readl_relaxed(mvebu_gpioreg_out(mvchip)); 204 } 205 206 return (u >> pin) & 1; 207 } 208 209 static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) 210 { 211 struct mvebu_gpio_chip *mvchip = 212 container_of(chip, struct mvebu_gpio_chip, chip); 213 unsigned long flags; 214 int ret; 215 u32 u; 216 217 /* Check with the pinctrl driver whether this pin is usable as 218 * an input GPIO */ 219 ret = pinctrl_gpio_direction_input(chip->base + pin); 220 if (ret) 221 return ret; 222 223 spin_lock_irqsave(&mvchip->lock, flags); 224 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 225 u |= 1 << pin; 226 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 227 spin_unlock_irqrestore(&mvchip->lock, flags); 228 229 return 0; 230 } 231 232 static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, 233 int value) 234 { 235 struct mvebu_gpio_chip *mvchip = 236 container_of(chip, struct mvebu_gpio_chip, chip); 237 unsigned long flags; 238 int ret; 239 u32 u; 240 241 /* Check with the pinctrl driver whether this pin is usable as 242 * an output GPIO */ 243 ret = pinctrl_gpio_direction_output(chip->base + pin); 244 if (ret) 245 return ret; 246 247 mvebu_gpio_set(chip, pin, value); 248 249 spin_lock_irqsave(&mvchip->lock, flags); 250 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)); 251 u &= ~(1 << pin); 252 writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip)); 253 spin_unlock_irqrestore(&mvchip->lock, flags); 254 255 return 0; 256 } 257 258 static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin) 259 { 260 struct mvebu_gpio_chip *mvchip = 261 container_of(chip, struct mvebu_gpio_chip, chip); 262 return irq_create_mapping(mvchip->domain, pin); 263 } 264 265 /* 266 * Functions implementing the irq_chip methods 267 */ 268 static void mvebu_gpio_irq_ack(struct irq_data *d) 269 { 270 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 271 struct mvebu_gpio_chip *mvchip = gc->private; 272 u32 mask = ~(1 << (d->irq - gc->irq_base)); 273 274 irq_gc_lock(gc); 275 writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip)); 276 irq_gc_unlock(gc); 277 } 278 279 static void mvebu_gpio_edge_irq_mask(struct irq_data *d) 280 { 281 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 282 struct mvebu_gpio_chip *mvchip = gc->private; 283 u32 mask = 1 << (d->irq - gc->irq_base); 284 285 irq_gc_lock(gc); 286 gc->mask_cache &= ~mask; 287 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 288 irq_gc_unlock(gc); 289 } 290 291 static void mvebu_gpio_edge_irq_unmask(struct irq_data *d) 292 { 293 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 294 struct mvebu_gpio_chip *mvchip = gc->private; 295 u32 mask = 1 << (d->irq - gc->irq_base); 296 297 irq_gc_lock(gc); 298 gc->mask_cache |= mask; 299 writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip)); 300 irq_gc_unlock(gc); 301 } 302 303 static void mvebu_gpio_level_irq_mask(struct irq_data *d) 304 { 305 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 306 struct mvebu_gpio_chip *mvchip = gc->private; 307 u32 mask = 1 << (d->irq - gc->irq_base); 308 309 irq_gc_lock(gc); 310 gc->mask_cache &= ~mask; 311 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 312 irq_gc_unlock(gc); 313 } 314 315 static void mvebu_gpio_level_irq_unmask(struct irq_data *d) 316 { 317 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 318 struct mvebu_gpio_chip *mvchip = gc->private; 319 u32 mask = 1 << (d->irq - gc->irq_base); 320 321 irq_gc_lock(gc); 322 gc->mask_cache |= mask; 323 writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip)); 324 irq_gc_unlock(gc); 325 } 326 327 /***************************************************************************** 328 * MVEBU GPIO IRQ 329 * 330 * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same 331 * value of the line or the opposite value. 332 * 333 * Level IRQ handlers: DATA_IN is used directly as cause register. 334 * Interrupt are masked by LEVEL_MASK registers. 335 * Edge IRQ handlers: Change in DATA_IN are latched in EDGE_CAUSE. 336 * Interrupt are masked by EDGE_MASK registers. 337 * Both-edge handlers: Similar to regular Edge handlers, but also swaps 338 * the polarity to catch the next line transaction. 339 * This is a race condition that might not perfectly 340 * work on some use cases. 341 * 342 * Every eight GPIO lines are grouped (OR'ed) before going up to main 343 * cause register. 344 * 345 * EDGE cause mask 346 * data-in /--------| |-----| |----\ 347 * -----| |----- ---- to main cause reg 348 * X \----------------| |----/ 349 * polarity LEVEL mask 350 * 351 ****************************************************************************/ 352 353 static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type) 354 { 355 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 356 struct irq_chip_type *ct = irq_data_get_chip_type(d); 357 struct mvebu_gpio_chip *mvchip = gc->private; 358 int pin; 359 u32 u; 360 361 pin = d->hwirq; 362 363 u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin); 364 if (!u) { 365 return -EINVAL; 366 } 367 368 type &= IRQ_TYPE_SENSE_MASK; 369 if (type == IRQ_TYPE_NONE) 370 return -EINVAL; 371 372 /* Check if we need to change chip and handler */ 373 if (!(ct->type & type)) 374 if (irq_setup_alt_chip(d, type)) 375 return -EINVAL; 376 377 /* 378 * Configure interrupt polarity. 379 */ 380 switch(type) { 381 case IRQ_TYPE_EDGE_RISING: 382 case IRQ_TYPE_LEVEL_HIGH: 383 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 384 u &= ~(1 << pin); 385 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 386 break; 387 case IRQ_TYPE_EDGE_FALLING: 388 case IRQ_TYPE_LEVEL_LOW: 389 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 390 u |= 1 << pin; 391 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 392 break; 393 case IRQ_TYPE_EDGE_BOTH: { 394 u32 v; 395 396 v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^ 397 readl_relaxed(mvebu_gpioreg_data_in(mvchip)); 398 399 /* 400 * set initial polarity based on current input level 401 */ 402 u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 403 if (v & (1 << pin)) 404 u |= 1 << pin; /* falling */ 405 else 406 u &= ~(1 << pin); /* rising */ 407 writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip)); 408 break; 409 } 410 } 411 return 0; 412 } 413 414 static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) 415 { 416 struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq); 417 u32 cause, type; 418 int i; 419 420 if (mvchip == NULL) 421 return; 422 423 cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) & 424 readl_relaxed(mvebu_gpioreg_level_mask(mvchip)); 425 cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) & 426 readl_relaxed(mvebu_gpioreg_edge_mask(mvchip)); 427 428 for (i = 0; i < mvchip->chip.ngpio; i++) { 429 int irq; 430 431 irq = mvchip->irqbase + i; 432 433 if (!(cause & (1 << i))) 434 continue; 435 436 type = irqd_get_trigger_type(irq_get_irq_data(irq)); 437 if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) { 438 /* Swap polarity (race with GPIO line) */ 439 u32 polarity; 440 441 polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)); 442 polarity ^= 1 << i; 443 writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip)); 444 } 445 generic_handle_irq(irq); 446 } 447 } 448 449 static struct platform_device_id mvebu_gpio_ids[] = { 450 { 451 .name = "orion-gpio", 452 }, { 453 .name = "mv78200-gpio", 454 }, { 455 .name = "armadaxp-gpio", 456 }, { 457 /* sentinel */ 458 }, 459 }; 460 MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids); 461 462 static struct of_device_id mvebu_gpio_of_match[] __devinitdata = { 463 { 464 .compatible = "marvell,orion-gpio", 465 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ORION, 466 }, 467 { 468 .compatible = "marvell,mv78200-gpio", 469 .data = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200, 470 }, 471 { 472 .compatible = "marvell,armadaxp-gpio", 473 .data = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP, 474 }, 475 { 476 /* sentinel */ 477 }, 478 }; 479 MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match); 480 481 static int __devinit mvebu_gpio_probe(struct platform_device *pdev) 482 { 483 struct mvebu_gpio_chip *mvchip; 484 const struct of_device_id *match; 485 struct device_node *np = pdev->dev.of_node; 486 struct resource *res; 487 struct irq_chip_generic *gc; 488 struct irq_chip_type *ct; 489 unsigned int ngpios; 490 int soc_variant; 491 int i, cpu, id; 492 493 match = of_match_device(mvebu_gpio_of_match, &pdev->dev); 494 if (match) 495 soc_variant = (int) match->data; 496 else 497 soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION; 498 499 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 500 if (! res) { 501 dev_err(&pdev->dev, "Cannot get memory resource\n"); 502 return -ENODEV; 503 } 504 505 mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL); 506 if (! mvchip){ 507 dev_err(&pdev->dev, "Cannot allocate memory\n"); 508 return -ENOMEM; 509 } 510 511 if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) { 512 dev_err(&pdev->dev, "Missing ngpios OF property\n"); 513 return -ENODEV; 514 } 515 516 id = of_alias_get_id(pdev->dev.of_node, "gpio"); 517 if (id < 0) { 518 dev_err(&pdev->dev, "Couldn't get OF id\n"); 519 return id; 520 } 521 522 mvchip->soc_variant = soc_variant; 523 mvchip->chip.label = dev_name(&pdev->dev); 524 mvchip->chip.dev = &pdev->dev; 525 mvchip->chip.request = mvebu_gpio_request; 526 mvchip->chip.direction_input = mvebu_gpio_direction_input; 527 mvchip->chip.get = mvebu_gpio_get; 528 mvchip->chip.direction_output = mvebu_gpio_direction_output; 529 mvchip->chip.set = mvebu_gpio_set; 530 mvchip->chip.to_irq = mvebu_gpio_to_irq; 531 mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK; 532 mvchip->chip.ngpio = ngpios; 533 mvchip->chip.can_sleep = 0; 534 #ifdef CONFIG_OF 535 mvchip->chip.of_node = np; 536 #endif 537 538 spin_lock_init(&mvchip->lock); 539 mvchip->membase = devm_request_and_ioremap(&pdev->dev, res); 540 if (! mvchip->membase) { 541 dev_err(&pdev->dev, "Cannot ioremap\n"); 542 kfree(mvchip->chip.label); 543 return -ENOMEM; 544 } 545 546 /* The Armada XP has a second range of registers for the 547 * per-CPU registers */ 548 if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { 549 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 550 if (! res) { 551 dev_err(&pdev->dev, "Cannot get memory resource\n"); 552 kfree(mvchip->chip.label); 553 return -ENODEV; 554 } 555 556 mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res); 557 if (! mvchip->percpu_membase) { 558 dev_err(&pdev->dev, "Cannot ioremap\n"); 559 kfree(mvchip->chip.label); 560 return -ENOMEM; 561 } 562 } 563 564 /* 565 * Mask and clear GPIO interrupts. 566 */ 567 switch(soc_variant) { 568 case MVEBU_GPIO_SOC_VARIANT_ORION: 569 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 570 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 571 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 572 break; 573 case MVEBU_GPIO_SOC_VARIANT_MV78200: 574 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 575 for (cpu = 0; cpu < 2; cpu++) { 576 writel_relaxed(0, mvchip->membase + 577 GPIO_EDGE_MASK_MV78200_OFF(cpu)); 578 writel_relaxed(0, mvchip->membase + 579 GPIO_LEVEL_MASK_MV78200_OFF(cpu)); 580 } 581 break; 582 case MVEBU_GPIO_SOC_VARIANT_ARMADAXP: 583 writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF); 584 writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF); 585 writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF); 586 for (cpu = 0; cpu < 4; cpu++) { 587 writel_relaxed(0, mvchip->percpu_membase + 588 GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu)); 589 writel_relaxed(0, mvchip->percpu_membase + 590 GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)); 591 writel_relaxed(0, mvchip->percpu_membase + 592 GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu)); 593 } 594 break; 595 default: 596 BUG(); 597 } 598 599 gpiochip_add(&mvchip->chip); 600 601 /* Some gpio controllers do not provide irq support */ 602 if (!of_irq_count(np)) 603 return 0; 604 605 /* Setup the interrupt handlers. Each chip can have up to 4 606 * interrupt handlers, with each handler dealing with 8 GPIO 607 * pins. */ 608 for (i = 0; i < 4; i++) { 609 int irq; 610 irq = platform_get_irq(pdev, i); 611 if (irq < 0) 612 continue; 613 irq_set_handler_data(irq, mvchip); 614 irq_set_chained_handler(irq, mvebu_gpio_irq_handler); 615 } 616 617 mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1); 618 if (mvchip->irqbase < 0) { 619 dev_err(&pdev->dev, "no irqs\n"); 620 kfree(mvchip->chip.label); 621 return -ENOMEM; 622 } 623 624 gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase, 625 mvchip->membase, handle_level_irq); 626 if (! gc) { 627 dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n"); 628 kfree(mvchip->chip.label); 629 return -ENOMEM; 630 } 631 632 gc->private = mvchip; 633 ct = &gc->chip_types[0]; 634 ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW; 635 ct->chip.irq_mask = mvebu_gpio_level_irq_mask; 636 ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask; 637 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 638 ct->chip.name = mvchip->chip.label; 639 640 ct = &gc->chip_types[1]; 641 ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 642 ct->chip.irq_ack = mvebu_gpio_irq_ack; 643 ct->chip.irq_mask = mvebu_gpio_edge_irq_mask; 644 ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask; 645 ct->chip.irq_set_type = mvebu_gpio_irq_set_type; 646 ct->handler = handle_edge_irq; 647 ct->chip.name = mvchip->chip.label; 648 649 irq_setup_generic_chip(gc, IRQ_MSK(ngpios), 0, 650 IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE); 651 652 /* Setup irq domain on top of the generic chip. */ 653 mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio, 654 mvchip->irqbase, 0, 655 &irq_domain_simple_ops, 656 mvchip); 657 if (!mvchip->domain) { 658 dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n", 659 mvchip->chip.label); 660 irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST, 661 IRQ_LEVEL | IRQ_NOPROBE); 662 kfree(gc); 663 kfree(mvchip->chip.label); 664 return -ENODEV; 665 } 666 667 return 0; 668 } 669 670 static struct platform_driver mvebu_gpio_driver = { 671 .driver = { 672 .name = "mvebu-gpio", 673 .owner = THIS_MODULE, 674 .of_match_table = mvebu_gpio_of_match, 675 }, 676 .probe = mvebu_gpio_probe, 677 .id_table = mvebu_gpio_ids, 678 }; 679 680 static int __init mvebu_gpio_init(void) 681 { 682 return platform_driver_register(&mvebu_gpio_driver); 683 } 684 postcore_initcall(mvebu_gpio_init); 685