1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2009-2011 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (C) 2013 John Crispin <blogic@openwrt.org> 5 */ 6 7 #include <linux/err.h> 8 #include <linux/gpio/driver.h> 9 #include <linux/gpio/generic.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 15 #define MTK_BANK_CNT 3 16 #define MTK_BANK_WIDTH 32 17 18 #define GPIO_BANK_STRIDE 0x04 19 #define GPIO_REG_CTRL 0x00 20 #define GPIO_REG_POL 0x10 21 #define GPIO_REG_DATA 0x20 22 #define GPIO_REG_DSET 0x30 23 #define GPIO_REG_DCLR 0x40 24 #define GPIO_REG_REDGE 0x50 25 #define GPIO_REG_FEDGE 0x60 26 #define GPIO_REG_HLVL 0x70 27 #define GPIO_REG_LLVL 0x80 28 #define GPIO_REG_STAT 0x90 29 #define GPIO_REG_EDGE 0xA0 30 31 struct mtk_gc { 32 struct irq_chip irq_chip; 33 struct gpio_generic_chip chip; 34 int bank; 35 u32 rising; 36 u32 falling; 37 u32 hlevel; 38 u32 llevel; 39 }; 40 41 /** 42 * struct mtk - state container for 43 * data of the platform driver. It is 3 44 * separate gpio-chip each one with its 45 * own irq_chip. 46 * @dev: device instance 47 * @base: memory base address 48 * @gpio_irq: irq number from the device tree 49 * @gc_map: array of the gpio chips 50 */ 51 struct mtk { 52 struct device *dev; 53 void __iomem *base; 54 int gpio_irq; 55 struct mtk_gc gc_map[MTK_BANK_CNT]; 56 }; 57 58 static inline struct mtk_gc * 59 to_mediatek_gpio(struct gpio_chip *chip) 60 { 61 struct gpio_generic_chip *gen_gc = to_gpio_generic_chip(chip); 62 63 return container_of(gen_gc, struct mtk_gc, chip); 64 } 65 66 static inline void 67 mtk_gpio_w32(struct mtk_gc *rg, u32 offset, u32 val) 68 { 69 struct gpio_chip *gc = &rg->chip.gc; 70 struct mtk *mtk = gpiochip_get_data(gc); 71 72 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 73 gpio_generic_write_reg(&rg->chip, mtk->base + offset, val); 74 } 75 76 static inline u32 77 mtk_gpio_r32(struct mtk_gc *rg, u32 offset) 78 { 79 struct gpio_chip *gc = &rg->chip.gc; 80 struct mtk *mtk = gpiochip_get_data(gc); 81 82 offset = (rg->bank * GPIO_BANK_STRIDE) + offset; 83 return gpio_generic_read_reg(&rg->chip, mtk->base + offset); 84 } 85 86 static irqreturn_t 87 mediatek_gpio_irq_handler(int irq, void *data) 88 { 89 struct gpio_chip *gc = data; 90 struct mtk_gc *rg = to_mediatek_gpio(gc); 91 irqreturn_t ret = IRQ_NONE; 92 unsigned long pending; 93 int bit; 94 95 pending = mtk_gpio_r32(rg, GPIO_REG_STAT); 96 97 for_each_set_bit(bit, &pending, MTK_BANK_WIDTH) { 98 generic_handle_domain_irq(gc->irq.domain, bit); 99 mtk_gpio_w32(rg, GPIO_REG_STAT, BIT(bit)); 100 ret |= IRQ_HANDLED; 101 } 102 103 return ret; 104 } 105 106 static void 107 mediatek_gpio_irq_unmask(struct irq_data *d) 108 { 109 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 110 struct mtk_gc *rg = to_mediatek_gpio(gc); 111 int pin = d->hwirq; 112 u32 rise, fall, high, low; 113 114 gpiochip_enable_irq(gc, d->hwirq); 115 116 guard(gpio_generic_lock_irqsave)(&rg->chip); 117 118 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 119 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 120 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 121 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 122 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise | (BIT(pin) & rg->rising)); 123 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall | (BIT(pin) & rg->falling)); 124 mtk_gpio_w32(rg, GPIO_REG_HLVL, high | (BIT(pin) & rg->hlevel)); 125 mtk_gpio_w32(rg, GPIO_REG_LLVL, low | (BIT(pin) & rg->llevel)); 126 } 127 128 static void 129 mediatek_gpio_irq_mask(struct irq_data *d) 130 { 131 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 132 struct mtk_gc *rg = to_mediatek_gpio(gc); 133 int pin = d->hwirq; 134 u32 rise, fall, high, low; 135 136 scoped_guard(gpio_generic_lock_irqsave, &rg->chip) { 137 rise = mtk_gpio_r32(rg, GPIO_REG_REDGE); 138 fall = mtk_gpio_r32(rg, GPIO_REG_FEDGE); 139 high = mtk_gpio_r32(rg, GPIO_REG_HLVL); 140 low = mtk_gpio_r32(rg, GPIO_REG_LLVL); 141 mtk_gpio_w32(rg, GPIO_REG_FEDGE, fall & ~BIT(pin)); 142 mtk_gpio_w32(rg, GPIO_REG_REDGE, rise & ~BIT(pin)); 143 mtk_gpio_w32(rg, GPIO_REG_HLVL, high & ~BIT(pin)); 144 mtk_gpio_w32(rg, GPIO_REG_LLVL, low & ~BIT(pin)); 145 } 146 147 gpiochip_disable_irq(gc, d->hwirq); 148 } 149 150 static int 151 mediatek_gpio_irq_type(struct irq_data *d, unsigned int type) 152 { 153 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 154 struct mtk_gc *rg = to_mediatek_gpio(gc); 155 int pin = d->hwirq; 156 u32 mask = BIT(pin); 157 158 if (type == IRQ_TYPE_PROBE) { 159 if ((rg->rising | rg->falling | 160 rg->hlevel | rg->llevel) & mask) 161 return 0; 162 163 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; 164 } 165 166 rg->rising &= ~mask; 167 rg->falling &= ~mask; 168 rg->hlevel &= ~mask; 169 rg->llevel &= ~mask; 170 171 switch (type & IRQ_TYPE_SENSE_MASK) { 172 case IRQ_TYPE_EDGE_BOTH: 173 rg->rising |= mask; 174 rg->falling |= mask; 175 break; 176 case IRQ_TYPE_EDGE_RISING: 177 rg->rising |= mask; 178 break; 179 case IRQ_TYPE_EDGE_FALLING: 180 rg->falling |= mask; 181 break; 182 case IRQ_TYPE_LEVEL_HIGH: 183 rg->hlevel |= mask; 184 break; 185 case IRQ_TYPE_LEVEL_LOW: 186 rg->llevel |= mask; 187 break; 188 } 189 190 return 0; 191 } 192 193 static int 194 mediatek_gpio_xlate(struct gpio_chip *chip, 195 const struct of_phandle_args *spec, u32 *flags) 196 { 197 int gpio = spec->args[0]; 198 struct mtk_gc *rg = to_mediatek_gpio(chip); 199 200 if (rg->bank != gpio / MTK_BANK_WIDTH) 201 return -EINVAL; 202 203 if (flags) 204 *flags = spec->args[1]; 205 206 return gpio % MTK_BANK_WIDTH; 207 } 208 209 static const struct irq_chip mt7621_irq_chip = { 210 .name = "mt7621-gpio", 211 .irq_mask_ack = mediatek_gpio_irq_mask, 212 .irq_mask = mediatek_gpio_irq_mask, 213 .irq_unmask = mediatek_gpio_irq_unmask, 214 .irq_set_type = mediatek_gpio_irq_type, 215 .flags = IRQCHIP_IMMUTABLE, 216 GPIOCHIP_IRQ_RESOURCE_HELPERS, 217 }; 218 219 static int 220 mediatek_gpio_bank_probe(struct device *dev, int bank) 221 { 222 struct gpio_generic_chip_config config; 223 struct mtk *mtk = dev_get_drvdata(dev); 224 struct mtk_gc *rg; 225 void __iomem *dat, *set, *ctrl, *diro; 226 int ret; 227 228 rg = &mtk->gc_map[bank]; 229 memset(rg, 0, sizeof(*rg)); 230 231 rg->bank = bank; 232 233 dat = mtk->base + GPIO_REG_DATA + (rg->bank * GPIO_BANK_STRIDE); 234 set = mtk->base + GPIO_REG_DSET + (rg->bank * GPIO_BANK_STRIDE); 235 ctrl = mtk->base + GPIO_REG_DCLR + (rg->bank * GPIO_BANK_STRIDE); 236 diro = mtk->base + GPIO_REG_CTRL + (rg->bank * GPIO_BANK_STRIDE); 237 238 config = (struct gpio_generic_chip_config) { 239 .dev = dev, 240 .sz = 4, 241 .dat = dat, 242 .set = set, 243 .clr = ctrl, 244 .dirout = diro, 245 .flags = GPIO_GENERIC_NO_SET_ON_INPUT, 246 }; 247 248 ret = gpio_generic_chip_init(&rg->chip, &config); 249 if (ret) { 250 dev_err(dev, "failed to initialize generic GPIO chip\n"); 251 return ret; 252 } 253 254 rg->chip.gc.of_gpio_n_cells = 2; 255 rg->chip.gc.of_xlate = mediatek_gpio_xlate; 256 rg->chip.gc.label = devm_kasprintf(dev, GFP_KERNEL, "%s-bank%d", 257 dev_name(dev), bank); 258 if (!rg->chip.gc.label) 259 return -ENOMEM; 260 261 rg->chip.gc.offset = bank * MTK_BANK_WIDTH; 262 263 if (mtk->gpio_irq) { 264 struct gpio_irq_chip *girq; 265 266 /* 267 * Directly request the irq here instead of passing 268 * a flow-handler because the irq is shared. 269 */ 270 ret = devm_request_irq(dev, mtk->gpio_irq, 271 mediatek_gpio_irq_handler, IRQF_SHARED, 272 rg->chip.gc.label, &rg->chip.gc); 273 274 if (ret) { 275 dev_err(dev, "Error requesting IRQ %d: %d\n", 276 mtk->gpio_irq, ret); 277 return ret; 278 } 279 280 girq = &rg->chip.gc.irq; 281 gpio_irq_chip_set_chip(girq, &mt7621_irq_chip); 282 /* This will let us handle the parent IRQ in the driver */ 283 girq->parent_handler = NULL; 284 girq->num_parents = 0; 285 girq->parents = NULL; 286 girq->default_type = IRQ_TYPE_NONE; 287 girq->handler = handle_simple_irq; 288 } 289 290 ret = devm_gpiochip_add_data(dev, &rg->chip.gc, mtk); 291 if (ret < 0) { 292 dev_err(dev, "Could not register gpio %d, ret=%d\n", 293 rg->chip.gc.ngpio, ret); 294 return ret; 295 } 296 297 /* set polarity to low for all gpios */ 298 mtk_gpio_w32(rg, GPIO_REG_POL, 0); 299 300 dev_info(dev, "registering %d gpios\n", rg->chip.gc.ngpio); 301 302 return 0; 303 } 304 305 static int 306 mediatek_gpio_probe(struct platform_device *pdev) 307 { 308 struct device *dev = &pdev->dev; 309 struct mtk *mtk; 310 int i; 311 int ret; 312 313 mtk = devm_kzalloc(dev, sizeof(*mtk), GFP_KERNEL); 314 if (!mtk) 315 return -ENOMEM; 316 317 mtk->base = devm_platform_ioremap_resource(pdev, 0); 318 if (IS_ERR(mtk->base)) 319 return PTR_ERR(mtk->base); 320 321 mtk->gpio_irq = platform_get_irq(pdev, 0); 322 if (mtk->gpio_irq < 0) 323 return mtk->gpio_irq; 324 325 mtk->dev = dev; 326 platform_set_drvdata(pdev, mtk); 327 328 for (i = 0; i < MTK_BANK_CNT; i++) { 329 ret = mediatek_gpio_bank_probe(dev, i); 330 if (ret) 331 return ret; 332 } 333 334 return 0; 335 } 336 337 static const struct of_device_id mediatek_gpio_match[] = { 338 { .compatible = "mediatek,mt7621-gpio" }, 339 {}, 340 }; 341 MODULE_DEVICE_TABLE(of, mediatek_gpio_match); 342 343 static struct platform_driver mediatek_gpio_driver = { 344 .probe = mediatek_gpio_probe, 345 .driver = { 346 .name = "mt7621_gpio", 347 .of_match_table = mediatek_gpio_match, 348 }, 349 }; 350 351 builtin_platform_driver(mediatek_gpio_driver); 352