1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * FTDI MPSSE GPIO support 4 * 5 * Based on code by Anatolij Gustschin 6 * 7 * Copyright (C) 2024 Mary Strodl <mstrodl@csh.rit.edu> 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/mutex.h> 13 #include <linux/usb.h> 14 15 struct mpsse_priv { 16 struct gpio_chip gpio; 17 struct usb_device *udev; /* USB device encompassing all MPSSEs */ 18 struct usb_interface *intf; /* USB interface for this MPSSE */ 19 u8 intf_id; /* USB interface number for this MPSSE */ 20 struct work_struct irq_work; /* polling work thread */ 21 struct mutex irq_mutex; /* lock over irq_data */ 22 atomic_t irq_type[16]; /* pin -> edge detection type */ 23 atomic_t irq_enabled; 24 int id; 25 26 u8 gpio_outputs[2]; /* Output states for GPIOs [L, H] */ 27 u8 gpio_dir[2]; /* Directions for GPIOs [L, H] */ 28 29 u8 *bulk_in_buf; /* Extra recv buffer to grab status bytes */ 30 31 struct usb_endpoint_descriptor *bulk_in; 32 struct usb_endpoint_descriptor *bulk_out; 33 34 struct mutex io_mutex; /* sync I/O with disconnect */ 35 }; 36 37 struct bulk_desc { 38 bool tx; /* direction of bulk transfer */ 39 u8 *data; /* input (tx) or output (rx) */ 40 int len; /* Length of `data` if tx, or length of */ 41 /* Data to read if rx */ 42 int len_actual; /* Length successfully transferred */ 43 int timeout; 44 }; 45 46 static const struct usb_device_id gpio_mpsse_table[] = { 47 { USB_DEVICE(0x0c52, 0xa064) }, /* SeaLevel Systems, Inc. */ 48 { } /* Terminating entry */ 49 }; 50 51 MODULE_DEVICE_TABLE(usb, gpio_mpsse_table); 52 53 static DEFINE_IDA(gpio_mpsse_ida); 54 55 /* MPSSE commands */ 56 #define SET_BITS_CMD 0x80 57 #define GET_BITS_CMD 0x81 58 59 #define SET_BITMODE_REQUEST 0x0B 60 #define MODE_MPSSE (2 << 8) 61 #define MODE_RESET 0 62 63 /* Arbitrarily decided. This could probably be much less */ 64 #define MPSSE_WRITE_TIMEOUT 5000 65 #define MPSSE_READ_TIMEOUT 5000 66 67 /* 1 millisecond, also pretty arbitrary */ 68 #define MPSSE_POLL_INTERVAL 1000 69 70 static int mpsse_bulk_xfer(struct usb_interface *intf, struct bulk_desc *desc) 71 { 72 struct mpsse_priv *priv = usb_get_intfdata(intf); 73 struct usb_device *udev = priv->udev; 74 unsigned int pipe; 75 int ret; 76 77 if (desc->tx) 78 pipe = usb_sndbulkpipe(udev, priv->bulk_out->bEndpointAddress); 79 else 80 pipe = usb_rcvbulkpipe(udev, priv->bulk_in->bEndpointAddress); 81 82 ret = usb_bulk_msg(udev, pipe, desc->data, desc->len, 83 &desc->len_actual, desc->timeout); 84 if (ret) 85 dev_dbg(&udev->dev, "mpsse: bulk transfer failed: %d\n", ret); 86 87 return ret; 88 } 89 90 static int mpsse_write(struct usb_interface *intf, 91 u8 *buf, size_t len) 92 { 93 int ret; 94 struct bulk_desc desc; 95 96 desc.len_actual = 0; 97 desc.tx = true; 98 desc.data = buf; 99 desc.len = len; 100 desc.timeout = MPSSE_WRITE_TIMEOUT; 101 102 ret = mpsse_bulk_xfer(intf, &desc); 103 104 return ret; 105 } 106 107 static int mpsse_read(struct usb_interface *intf, u8 *buf, size_t len) 108 { 109 int ret; 110 struct bulk_desc desc; 111 struct mpsse_priv *priv = usb_get_intfdata(intf); 112 113 desc.len_actual = 0; 114 desc.tx = false; 115 desc.data = priv->bulk_in_buf; 116 /* Device sends 2 additional status bytes, read len + 2 */ 117 desc.len = min_t(size_t, len + 2, usb_endpoint_maxp(priv->bulk_in)); 118 desc.timeout = MPSSE_READ_TIMEOUT; 119 120 ret = mpsse_bulk_xfer(intf, &desc); 121 if (ret) 122 return ret; 123 124 /* Did we get enough data? */ 125 if (desc.len_actual < desc.len) 126 return -EIO; 127 128 memcpy(buf, desc.data + 2, desc.len_actual - 2); 129 130 return ret; 131 } 132 133 static int gpio_mpsse_set_bank(struct mpsse_priv *priv, u8 bank) 134 { 135 int ret; 136 u8 tx_buf[3] = { 137 SET_BITS_CMD | (bank << 1), 138 priv->gpio_outputs[bank], 139 priv->gpio_dir[bank], 140 }; 141 142 ret = mpsse_write(priv->intf, tx_buf, 3); 143 144 return ret; 145 } 146 147 static int gpio_mpsse_get_bank(struct mpsse_priv *priv, u8 bank) 148 { 149 int ret; 150 u8 buf = GET_BITS_CMD | (bank << 1); 151 152 ret = mpsse_write(priv->intf, &buf, 1); 153 if (ret) 154 return ret; 155 156 ret = mpsse_read(priv->intf, &buf, 1); 157 if (ret) 158 return ret; 159 160 return buf; 161 } 162 163 static int gpio_mpsse_set_multiple(struct gpio_chip *chip, unsigned long *mask, 164 unsigned long *bits) 165 { 166 unsigned long i, bank, bank_mask, bank_bits; 167 int ret; 168 struct mpsse_priv *priv = gpiochip_get_data(chip); 169 170 guard(mutex)(&priv->io_mutex); 171 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { 172 bank = i / 8; 173 174 if (bank_mask) { 175 bank_bits = bitmap_get_value8(bits, i); 176 /* Zero out pins we want to change */ 177 priv->gpio_outputs[bank] &= ~bank_mask; 178 /* Set pins we care about */ 179 priv->gpio_outputs[bank] |= bank_bits & bank_mask; 180 181 ret = gpio_mpsse_set_bank(priv, bank); 182 if (ret) 183 return ret; 184 } 185 } 186 187 return 0; 188 } 189 190 static int gpio_mpsse_get_multiple(struct gpio_chip *chip, unsigned long *mask, 191 unsigned long *bits) 192 { 193 unsigned long i, bank, bank_mask; 194 int ret; 195 struct mpsse_priv *priv = gpiochip_get_data(chip); 196 197 guard(mutex)(&priv->io_mutex); 198 for_each_set_clump8(i, bank_mask, mask, chip->ngpio) { 199 bank = i / 8; 200 201 if (bank_mask) { 202 ret = gpio_mpsse_get_bank(priv, bank); 203 if (ret < 0) 204 return ret; 205 206 bitmap_set_value8(bits, ret & bank_mask, i); 207 } 208 } 209 210 return 0; 211 } 212 213 static int gpio_mpsse_gpio_get(struct gpio_chip *chip, unsigned int offset) 214 { 215 int err; 216 unsigned long mask = 0, bits = 0; 217 218 __set_bit(offset, &mask); 219 err = gpio_mpsse_get_multiple(chip, &mask, &bits); 220 if (err) 221 return err; 222 223 /* == is not guaranteed to give 1 if true */ 224 if (bits) 225 return 1; 226 else 227 return 0; 228 } 229 230 static int gpio_mpsse_gpio_set(struct gpio_chip *chip, unsigned int offset, 231 int value) 232 { 233 unsigned long mask = 0, bits = 0; 234 235 __set_bit(offset, &mask); 236 if (value) 237 __set_bit(offset, &bits); 238 239 return gpio_mpsse_set_multiple(chip, &mask, &bits); 240 } 241 242 static int gpio_mpsse_direction_output(struct gpio_chip *chip, 243 unsigned int offset, int value) 244 { 245 struct mpsse_priv *priv = gpiochip_get_data(chip); 246 int bank = (offset & 8) >> 3; 247 int bank_offset = offset & 7; 248 249 scoped_guard(mutex, &priv->io_mutex) 250 priv->gpio_dir[bank] |= BIT(bank_offset); 251 252 return gpio_mpsse_gpio_set(chip, offset, value); 253 } 254 255 static int gpio_mpsse_direction_input(struct gpio_chip *chip, 256 unsigned int offset) 257 { 258 struct mpsse_priv *priv = gpiochip_get_data(chip); 259 int bank = (offset & 8) >> 3; 260 int bank_offset = offset & 7; 261 262 guard(mutex)(&priv->io_mutex); 263 priv->gpio_dir[bank] &= ~BIT(bank_offset); 264 gpio_mpsse_set_bank(priv, bank); 265 266 return 0; 267 } 268 269 static int gpio_mpsse_get_direction(struct gpio_chip *chip, 270 unsigned int offset) 271 { 272 int ret; 273 int bank = (offset & 8) >> 3; 274 int bank_offset = offset & 7; 275 struct mpsse_priv *priv = gpiochip_get_data(chip); 276 277 guard(mutex)(&priv->io_mutex); 278 /* MPSSE directions are inverted */ 279 if (priv->gpio_dir[bank] & BIT(bank_offset)) 280 ret = GPIO_LINE_DIRECTION_OUT; 281 else 282 ret = GPIO_LINE_DIRECTION_IN; 283 284 return ret; 285 } 286 287 static void gpio_mpsse_poll(struct work_struct *work) 288 { 289 unsigned long pin_mask, pin_states, flags; 290 int irq_enabled, offset, err, value, fire_irq, 291 irq, old_value[16], irq_type[16]; 292 struct mpsse_priv *priv = container_of(work, struct mpsse_priv, 293 irq_work); 294 295 for (offset = 0; offset < priv->gpio.ngpio; ++offset) 296 old_value[offset] = -1; 297 298 while ((irq_enabled = atomic_read(&priv->irq_enabled))) { 299 usleep_range(MPSSE_POLL_INTERVAL, MPSSE_POLL_INTERVAL + 1000); 300 /* Cleanup will trigger at the end of the loop */ 301 guard(mutex)(&priv->irq_mutex); 302 303 pin_mask = 0; 304 pin_states = 0; 305 for (offset = 0; offset < priv->gpio.ngpio; ++offset) { 306 irq_type[offset] = atomic_read(&priv->irq_type[offset]); 307 if (irq_type[offset] != IRQ_TYPE_NONE && 308 irq_enabled & BIT(offset)) 309 pin_mask |= BIT(offset); 310 else 311 old_value[offset] = -1; 312 } 313 314 err = gpio_mpsse_get_multiple(&priv->gpio, &pin_mask, 315 &pin_states); 316 if (err) { 317 dev_err_ratelimited(&priv->intf->dev, 318 "Error polling!\n"); 319 continue; 320 } 321 322 /* Check each value */ 323 for (offset = 0; offset < priv->gpio.ngpio; ++offset) { 324 if (old_value[offset] == -1) 325 continue; 326 327 fire_irq = 0; 328 value = pin_states & BIT(offset); 329 330 switch (irq_type[offset]) { 331 case IRQ_TYPE_EDGE_RISING: 332 fire_irq = value > old_value[offset]; 333 break; 334 case IRQ_TYPE_EDGE_FALLING: 335 fire_irq = value < old_value[offset]; 336 break; 337 case IRQ_TYPE_EDGE_BOTH: 338 fire_irq = value != old_value[offset]; 339 break; 340 } 341 if (!fire_irq) 342 continue; 343 344 irq = irq_find_mapping(priv->gpio.irq.domain, 345 offset); 346 local_irq_save(flags); 347 generic_handle_irq(irq); 348 local_irq_disable(); 349 local_irq_restore(flags); 350 } 351 352 /* Sync back values so we can refer to them next tick */ 353 for (offset = 0; offset < priv->gpio.ngpio; ++offset) 354 if (irq_type[offset] != IRQ_TYPE_NONE && 355 irq_enabled & BIT(offset)) 356 old_value[offset] = pin_states & BIT(offset); 357 } 358 } 359 360 static int gpio_mpsse_set_irq_type(struct irq_data *irqd, unsigned int type) 361 { 362 int offset; 363 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd); 364 365 offset = irqd->hwirq; 366 atomic_set(&priv->irq_type[offset], type & IRQ_TYPE_EDGE_BOTH); 367 368 return 0; 369 } 370 371 static void gpio_mpsse_irq_disable(struct irq_data *irqd) 372 { 373 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd); 374 375 atomic_and(~BIT(irqd->hwirq), &priv->irq_enabled); 376 gpiochip_disable_irq(&priv->gpio, irqd->hwirq); 377 } 378 379 static void gpio_mpsse_irq_enable(struct irq_data *irqd) 380 { 381 struct mpsse_priv *priv = irq_data_get_irq_chip_data(irqd); 382 383 gpiochip_enable_irq(&priv->gpio, irqd->hwirq); 384 /* If no-one else was using the IRQ, enable it */ 385 if (!atomic_fetch_or(BIT(irqd->hwirq), &priv->irq_enabled)) { 386 INIT_WORK(&priv->irq_work, gpio_mpsse_poll); 387 schedule_work(&priv->irq_work); 388 } 389 } 390 391 static const struct irq_chip gpio_mpsse_irq_chip = { 392 .name = "gpio-mpsse-irq", 393 .irq_enable = gpio_mpsse_irq_enable, 394 .irq_disable = gpio_mpsse_irq_disable, 395 .irq_set_type = gpio_mpsse_set_irq_type, 396 .flags = IRQCHIP_IMMUTABLE, 397 GPIOCHIP_IRQ_RESOURCE_HELPERS, 398 }; 399 400 static void gpio_mpsse_ida_remove(void *data) 401 { 402 struct mpsse_priv *priv = data; 403 404 ida_free(&gpio_mpsse_ida, priv->id); 405 } 406 407 static int gpio_mpsse_probe(struct usb_interface *interface, 408 const struct usb_device_id *id) 409 { 410 struct mpsse_priv *priv; 411 struct device *dev; 412 int err; 413 414 dev = &interface->dev; 415 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 416 if (!priv) 417 return -ENOMEM; 418 419 priv->udev = usb_get_dev(interface_to_usbdev(interface)); 420 priv->intf = interface; 421 priv->intf_id = interface->cur_altsetting->desc.bInterfaceNumber; 422 423 priv->id = ida_alloc(&gpio_mpsse_ida, GFP_KERNEL); 424 if (priv->id < 0) 425 return priv->id; 426 427 err = devm_add_action_or_reset(dev, gpio_mpsse_ida_remove, priv); 428 if (err) 429 return err; 430 431 err = devm_mutex_init(dev, &priv->io_mutex); 432 if (err) 433 return err; 434 435 err = devm_mutex_init(dev, &priv->irq_mutex); 436 if (err) 437 return err; 438 439 priv->gpio.label = devm_kasprintf(dev, GFP_KERNEL, 440 "gpio-mpsse.%d.%d", 441 priv->id, priv->intf_id); 442 if (!priv->gpio.label) 443 return -ENOMEM; 444 445 priv->gpio.owner = THIS_MODULE; 446 priv->gpio.parent = interface->usb_dev; 447 priv->gpio.get_direction = gpio_mpsse_get_direction; 448 priv->gpio.direction_input = gpio_mpsse_direction_input; 449 priv->gpio.direction_output = gpio_mpsse_direction_output; 450 priv->gpio.get = gpio_mpsse_gpio_get; 451 priv->gpio.set = gpio_mpsse_gpio_set; 452 priv->gpio.get_multiple = gpio_mpsse_get_multiple; 453 priv->gpio.set_multiple = gpio_mpsse_set_multiple; 454 priv->gpio.base = -1; 455 priv->gpio.ngpio = 16; 456 priv->gpio.offset = priv->intf_id * priv->gpio.ngpio; 457 priv->gpio.can_sleep = 1; 458 459 err = usb_find_common_endpoints(interface->cur_altsetting, 460 &priv->bulk_in, &priv->bulk_out, 461 NULL, NULL); 462 if (err) 463 return err; 464 465 priv->bulk_in_buf = devm_kmalloc(dev, usb_endpoint_maxp(priv->bulk_in), 466 GFP_KERNEL); 467 if (!priv->bulk_in_buf) 468 return -ENOMEM; 469 470 usb_set_intfdata(interface, priv); 471 472 /* Reset mode, needed to correctly enter MPSSE mode */ 473 err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), 474 SET_BITMODE_REQUEST, 475 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, 476 MODE_RESET, priv->intf_id + 1, NULL, 0, 477 USB_CTRL_SET_TIMEOUT); 478 if (err) 479 return err; 480 481 /* Enter MPSSE mode */ 482 err = usb_control_msg(priv->udev, usb_sndctrlpipe(priv->udev, 0), 483 SET_BITMODE_REQUEST, 484 USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT, 485 MODE_MPSSE, priv->intf_id + 1, NULL, 0, 486 USB_CTRL_SET_TIMEOUT); 487 if (err) 488 return err; 489 490 gpio_irq_chip_set_chip(&priv->gpio.irq, &gpio_mpsse_irq_chip); 491 492 priv->gpio.irq.parent_handler = NULL; 493 priv->gpio.irq.num_parents = 0; 494 priv->gpio.irq.parents = NULL; 495 priv->gpio.irq.default_type = IRQ_TYPE_NONE; 496 priv->gpio.irq.handler = handle_simple_irq; 497 498 err = devm_gpiochip_add_data(dev, &priv->gpio, priv); 499 if (err) 500 return err; 501 502 return 0; 503 } 504 505 static void gpio_mpsse_disconnect(struct usb_interface *intf) 506 { 507 struct mpsse_priv *priv = usb_get_intfdata(intf); 508 509 priv->intf = NULL; 510 usb_set_intfdata(intf, NULL); 511 usb_put_dev(priv->udev); 512 } 513 514 static struct usb_driver gpio_mpsse_driver = { 515 .name = "gpio-mpsse", 516 .probe = gpio_mpsse_probe, 517 .disconnect = gpio_mpsse_disconnect, 518 .id_table = gpio_mpsse_table, 519 }; 520 521 module_usb_driver(gpio_mpsse_driver); 522 523 MODULE_AUTHOR("Mary Strodl <mstrodl@csh.rit.edu>"); 524 MODULE_DESCRIPTION("MPSSE GPIO driver"); 525 MODULE_LICENSE("GPL"); 526