1 // SPDX-License-Identifier: (GPL-2.0) 2 /* 3 * Microchip PolarFire SoC (MPFS) GPIO controller driver 4 * 5 * Copyright (c) 2018-2024 Microchip Technology Inc. and its subsidiaries 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/device.h> 10 #include <linux/errno.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/of_irq.h> 14 #include <linux/platform_device.h> 15 #include <linux/property.h> 16 #include <linux/regmap.h> 17 #include <linux/spinlock.h> 18 19 #define MPFS_GPIO_CTRL(i) (0x4 * (i)) 20 #define MPFS_MAX_NUM_GPIO 32 21 #define MPFS_GPIO_EN_INT BIT(3) 22 #define MPFS_GPIO_EN_OUT_BUF BIT(2) 23 #define MPFS_GPIO_EN_IN BIT(1) 24 #define MPFS_GPIO_EN_OUT BIT(0) 25 #define MPFS_GPIO_DIR_MASK GENMASK(2, 0) 26 27 #define MPFS_GPIO_TYPE_INT_EDGE_BOTH 0x80 28 #define MPFS_GPIO_TYPE_INT_EDGE_NEG 0x60 29 #define MPFS_GPIO_TYPE_INT_EDGE_POS 0x40 30 #define MPFS_GPIO_TYPE_INT_LEVEL_LOW 0x20 31 #define MPFS_GPIO_TYPE_INT_LEVEL_HIGH 0x00 32 #define MPFS_GPIO_TYPE_INT_MASK GENMASK(7, 5) 33 #define MPFS_IRQ_REG 0x80 34 35 #define MPFS_INP_REG 0x84 36 #define COREGPIO_INP_REG 0x90 37 #define MPFS_OUTP_REG 0x88 38 #define COREGPIO_OUTP_REG 0xA0 39 40 struct mpfs_gpio_reg_offsets { 41 u8 inp; 42 u8 outp; 43 }; 44 45 struct mpfs_gpio_chip { 46 struct regmap *regs; 47 const struct mpfs_gpio_reg_offsets *offsets; 48 struct gpio_chip gc; 49 }; 50 51 static const struct regmap_config mpfs_gpio_regmap_config = { 52 .reg_bits = 32, 53 .reg_stride = 4, 54 .val_bits = 32, 55 .use_raw_spinlock = true, 56 }; 57 58 static int mpfs_gpio_direction_input(struct gpio_chip *gc, unsigned int gpio_index) 59 { 60 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 61 62 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 63 MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_IN); 64 65 return 0; 66 } 67 68 static int mpfs_gpio_direction_output(struct gpio_chip *gc, unsigned int gpio_index, int value) 69 { 70 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 71 72 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 73 MPFS_GPIO_DIR_MASK, MPFS_GPIO_EN_OUT | MPFS_GPIO_EN_OUT_BUF); 74 regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index), 75 value << gpio_index); 76 77 return 0; 78 } 79 80 static int mpfs_gpio_get_direction(struct gpio_chip *gc, 81 unsigned int gpio_index) 82 { 83 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 84 unsigned int gpio_cfg; 85 86 regmap_read(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), &gpio_cfg); 87 if (gpio_cfg & MPFS_GPIO_EN_IN) 88 return GPIO_LINE_DIRECTION_IN; 89 90 return GPIO_LINE_DIRECTION_OUT; 91 } 92 93 static int mpfs_gpio_get(struct gpio_chip *gc, unsigned int gpio_index) 94 { 95 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 96 97 if (mpfs_gpio_get_direction(gc, gpio_index) == GPIO_LINE_DIRECTION_OUT) 98 return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, BIT(gpio_index)); 99 else 100 return regmap_test_bits(mpfs_gpio->regs, mpfs_gpio->offsets->inp, BIT(gpio_index)); 101 } 102 103 static int mpfs_gpio_set(struct gpio_chip *gc, unsigned int gpio_index, int value) 104 { 105 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 106 int ret; 107 108 mpfs_gpio_get(gc, gpio_index); 109 110 ret = regmap_update_bits(mpfs_gpio->regs, mpfs_gpio->offsets->outp, 111 BIT(gpio_index), value << gpio_index); 112 113 mpfs_gpio_get(gc, gpio_index); 114 115 return ret; 116 } 117 118 static int mpfs_gpio_irq_set_type(struct irq_data *data, unsigned int type) 119 { 120 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 121 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 122 int gpio_index = irqd_to_hwirq(data) % 32; 123 u32 interrupt_type; 124 125 switch (type) { 126 case IRQ_TYPE_EDGE_BOTH: 127 interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_BOTH; 128 break; 129 case IRQ_TYPE_EDGE_FALLING: 130 interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_NEG; 131 break; 132 case IRQ_TYPE_EDGE_RISING: 133 interrupt_type = MPFS_GPIO_TYPE_INT_EDGE_POS; 134 break; 135 case IRQ_TYPE_LEVEL_HIGH: 136 interrupt_type = MPFS_GPIO_TYPE_INT_LEVEL_HIGH; 137 break; 138 case IRQ_TYPE_LEVEL_LOW: 139 interrupt_type = MPFS_GPIO_TYPE_INT_LEVEL_LOW; 140 break; 141 } 142 143 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 144 MPFS_GPIO_TYPE_INT_MASK, interrupt_type); 145 146 return 0; 147 } 148 149 static void mpfs_gpio_irq_unmask(struct irq_data *data) 150 { 151 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 152 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 153 int gpio_index = irqd_to_hwirq(data) % 32; 154 155 gpiochip_enable_irq(gc, gpio_index); 156 mpfs_gpio_direction_input(gc, gpio_index); 157 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 158 MPFS_GPIO_EN_INT, MPFS_GPIO_EN_INT); 159 } 160 161 static void mpfs_gpio_irq_mask(struct irq_data *data) 162 { 163 struct gpio_chip *gc = irq_data_get_irq_chip_data(data); 164 struct mpfs_gpio_chip *mpfs_gpio = gpiochip_get_data(gc); 165 int gpio_index = irqd_to_hwirq(data) % 32; 166 167 regmap_update_bits(mpfs_gpio->regs, MPFS_GPIO_CTRL(gpio_index), 168 MPFS_GPIO_EN_INT, 0); 169 gpiochip_disable_irq(gc, gpio_index); 170 } 171 172 static const struct irq_chip mpfs_gpio_irqchip = { 173 .name = "MPFS GPIO", 174 .irq_set_type = mpfs_gpio_irq_set_type, 175 .irq_mask = mpfs_gpio_irq_mask, 176 .irq_unmask = mpfs_gpio_irq_unmask, 177 .flags = IRQCHIP_IMMUTABLE | IRQCHIP_MASK_ON_SUSPEND, 178 GPIOCHIP_IRQ_RESOURCE_HELPERS, 179 }; 180 181 static void mpfs_gpio_irq_handler(struct irq_desc *desc) 182 { 183 struct irq_chip *irqchip = irq_desc_get_chip(desc); 184 struct mpfs_gpio_chip *mpfs_gpio = irq_desc_get_handler_data(desc); 185 unsigned long status; 186 u32 val; 187 int i; 188 189 chained_irq_enter(irqchip, desc); 190 191 regmap_read(mpfs_gpio->regs, MPFS_IRQ_REG, &val); 192 status = val; 193 for_each_set_bit(i, &status, MPFS_MAX_NUM_GPIO) { 194 regmap_write(mpfs_gpio->regs, MPFS_IRQ_REG, BIT(i)); 195 generic_handle_domain_irq(mpfs_gpio->gc.irq.domain, i); 196 } 197 198 chained_irq_exit(irqchip, desc); 199 } 200 201 static int mpfs_gpio_probe(struct platform_device *pdev) 202 { 203 struct device *dev = &pdev->dev; 204 struct device_node *node = dev->of_node; 205 struct mpfs_gpio_chip *mpfs_gpio; 206 struct gpio_irq_chip *girq; 207 struct clk *clk; 208 void __iomem *base; 209 int ngpios, nirqs, ret; 210 211 mpfs_gpio = devm_kzalloc(dev, sizeof(*mpfs_gpio), GFP_KERNEL); 212 if (!mpfs_gpio) 213 return -ENOMEM; 214 215 mpfs_gpio->offsets = device_get_match_data(&pdev->dev); 216 217 base = devm_platform_ioremap_resource(pdev, 0); 218 if (IS_ERR(base)) 219 return dev_err_probe(dev, PTR_ERR(base), "failed to ioremap memory resource\n"); 220 221 mpfs_gpio->regs = devm_regmap_init_mmio(dev, base, &mpfs_gpio_regmap_config); 222 if (IS_ERR(mpfs_gpio->regs)) 223 return dev_err_probe(dev, PTR_ERR(mpfs_gpio->regs), 224 "failed to initialise regmap\n"); 225 226 clk = devm_clk_get_enabled(dev, NULL); 227 if (IS_ERR(clk)) 228 return dev_err_probe(dev, PTR_ERR(clk), "failed to get and enable clock\n"); 229 230 ngpios = MPFS_MAX_NUM_GPIO; 231 device_property_read_u32(dev, "ngpios", &ngpios); 232 if (ngpios > MPFS_MAX_NUM_GPIO) 233 ngpios = MPFS_MAX_NUM_GPIO; 234 235 mpfs_gpio->gc.direction_input = mpfs_gpio_direction_input; 236 mpfs_gpio->gc.direction_output = mpfs_gpio_direction_output; 237 mpfs_gpio->gc.get_direction = mpfs_gpio_get_direction; 238 mpfs_gpio->gc.get = mpfs_gpio_get; 239 mpfs_gpio->gc.set = mpfs_gpio_set; 240 mpfs_gpio->gc.base = -1; 241 mpfs_gpio->gc.ngpio = ngpios; 242 mpfs_gpio->gc.label = dev_name(dev); 243 mpfs_gpio->gc.parent = dev; 244 mpfs_gpio->gc.owner = THIS_MODULE; 245 246 nirqs = of_irq_count(node); 247 if (nirqs > MPFS_MAX_NUM_GPIO) 248 return -ENXIO; 249 250 if (nirqs) { 251 girq = &mpfs_gpio->gc.irq; 252 253 gpio_irq_chip_set_chip(girq, &mpfs_gpio_irqchip); 254 255 girq->num_parents = nirqs; 256 girq->parents = devm_kcalloc(&pdev->dev, girq->num_parents, 257 sizeof(*girq->parents), GFP_KERNEL); 258 if (!girq->parents) 259 return -ENOMEM; 260 261 for (int i = 0; i < nirqs; i++) { 262 ret = platform_get_irq(pdev, i); 263 if (ret < 0) 264 return ret; 265 266 girq->parents[i] = ret; 267 girq->parent_handler_data = mpfs_gpio; 268 girq->parent_handler = mpfs_gpio_irq_handler; 269 } 270 271 girq->handler = handle_level_irq; 272 girq->default_type = IRQ_TYPE_NONE; 273 } 274 275 return devm_gpiochip_add_data(dev, &mpfs_gpio->gc, mpfs_gpio); 276 } 277 278 static const struct mpfs_gpio_reg_offsets mpfs_reg_offsets = { 279 .inp = MPFS_INP_REG, 280 .outp = MPFS_OUTP_REG, 281 }; 282 283 static const struct mpfs_gpio_reg_offsets coregpio_reg_offsets = { 284 .inp = COREGPIO_INP_REG, 285 .outp = COREGPIO_OUTP_REG, 286 }; 287 288 static const struct of_device_id mpfs_gpio_of_ids[] = { 289 { 290 .compatible = "microchip,mpfs-gpio", 291 .data = &mpfs_reg_offsets, 292 }, { 293 .compatible = "microchip,coregpio-rtl-v3", 294 .data = &coregpio_reg_offsets, 295 }, 296 { /* end of list */ } 297 }; 298 299 static struct platform_driver mpfs_gpio_driver = { 300 .probe = mpfs_gpio_probe, 301 .driver = { 302 .name = "microchip,mpfs-gpio", 303 .of_match_table = mpfs_gpio_of_ids, 304 }, 305 }; 306 builtin_platform_driver(mpfs_gpio_driver); 307