1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible 4 * 5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2016 Freescale Semiconductor Inc. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #define MPC8XXX_GPIO_PINS 32 26 27 #define GPIO_DIR 0x00 28 #define GPIO_ODR 0x04 29 #define GPIO_DAT 0x08 30 #define GPIO_IER 0x0c 31 #define GPIO_IMR 0x10 32 #define GPIO_ICR 0x14 33 #define GPIO_ICR2 0x18 34 #define GPIO_IBE 0x18 35 36 struct mpc8xxx_gpio_chip { 37 struct gpio_chip gc; 38 void __iomem *regs; 39 raw_spinlock_t lock; 40 41 int (*direction_output)(struct gpio_chip *chip, 42 unsigned offset, int value); 43 44 struct irq_domain *irq; 45 int irqn; 46 }; 47 48 /* 49 * This hardware has a big endian bit assignment such that GPIO line 0 is 50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. 51 * This inline helper give the right bitmask for a certain line. 52 */ 53 static inline u32 mpc_pin2mask(unsigned int offset) 54 { 55 return BIT(31 - offset); 56 } 57 58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 59 * defined as output cannot be determined by reading GPDAT register, 60 * so we use shadow data register instead. The status of input pins 61 * is determined by reading GPDAT register. 62 */ 63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 64 { 65 u32 val; 66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 67 u32 out_mask, out_shadow; 68 69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 71 out_shadow = gc->bgpio_data & out_mask; 72 73 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 74 } 75 76 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, 77 unsigned int gpio, int val) 78 { 79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 80 /* GPIO 28..31 are input only on MPC5121 */ 81 if (gpio >= 28) 82 return -EINVAL; 83 84 return mpc8xxx_gc->direction_output(gc, gpio, val); 85 } 86 87 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, 88 unsigned int gpio, int val) 89 { 90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 91 /* GPIO 0..3 are input only on MPC5125 */ 92 if (gpio <= 3) 93 return -EINVAL; 94 95 return mpc8xxx_gc->direction_output(gc, gpio, val); 96 } 97 98 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 99 { 100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 101 102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 103 return irq_create_mapping(mpc8xxx_gc->irq, offset); 104 else 105 return -ENXIO; 106 } 107 108 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) 109 { 110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; 111 struct gpio_chip *gc = &mpc8xxx_gc->gc; 112 unsigned long mask; 113 int i; 114 115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) 116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); 117 for_each_set_bit(i, &mask, 32) 118 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); 119 120 return IRQ_HANDLED; 121 } 122 123 static void mpc8xxx_irq_unmask(struct irq_data *d) 124 { 125 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 126 struct gpio_chip *gc = &mpc8xxx_gc->gc; 127 unsigned long flags; 128 129 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 130 131 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 132 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 133 | mpc_pin2mask(irqd_to_hwirq(d))); 134 135 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 136 } 137 138 static void mpc8xxx_irq_mask(struct irq_data *d) 139 { 140 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 141 struct gpio_chip *gc = &mpc8xxx_gc->gc; 142 unsigned long flags; 143 144 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 145 146 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 147 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 148 & ~mpc_pin2mask(irqd_to_hwirq(d))); 149 150 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 151 } 152 153 static void mpc8xxx_irq_ack(struct irq_data *d) 154 { 155 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 156 struct gpio_chip *gc = &mpc8xxx_gc->gc; 157 158 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 159 mpc_pin2mask(irqd_to_hwirq(d))); 160 } 161 162 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 163 { 164 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 165 struct gpio_chip *gc = &mpc8xxx_gc->gc; 166 unsigned long flags; 167 168 switch (flow_type) { 169 case IRQ_TYPE_EDGE_FALLING: 170 case IRQ_TYPE_LEVEL_LOW: 171 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 172 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 173 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 174 | mpc_pin2mask(irqd_to_hwirq(d))); 175 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 176 break; 177 178 case IRQ_TYPE_EDGE_BOTH: 179 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 180 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 181 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 182 & ~mpc_pin2mask(irqd_to_hwirq(d))); 183 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 184 break; 185 186 default: 187 return -EINVAL; 188 } 189 190 return 0; 191 } 192 193 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 194 { 195 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 196 struct gpio_chip *gc = &mpc8xxx_gc->gc; 197 unsigned long gpio = irqd_to_hwirq(d); 198 void __iomem *reg; 199 unsigned int shift; 200 unsigned long flags; 201 202 if (gpio < 16) { 203 reg = mpc8xxx_gc->regs + GPIO_ICR; 204 shift = (15 - gpio) * 2; 205 } else { 206 reg = mpc8xxx_gc->regs + GPIO_ICR2; 207 shift = (15 - (gpio % 16)) * 2; 208 } 209 210 switch (flow_type) { 211 case IRQ_TYPE_EDGE_FALLING: 212 case IRQ_TYPE_LEVEL_LOW: 213 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 214 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 215 | (2 << shift)); 216 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 217 break; 218 219 case IRQ_TYPE_EDGE_RISING: 220 case IRQ_TYPE_LEVEL_HIGH: 221 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 222 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 223 | (1 << shift)); 224 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 225 break; 226 227 case IRQ_TYPE_EDGE_BOTH: 228 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 229 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); 230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 231 break; 232 233 default: 234 return -EINVAL; 235 } 236 237 return 0; 238 } 239 240 static struct irq_chip mpc8xxx_irq_chip = { 241 .name = "mpc8xxx-gpio", 242 .irq_unmask = mpc8xxx_irq_unmask, 243 .irq_mask = mpc8xxx_irq_mask, 244 .irq_ack = mpc8xxx_irq_ack, 245 /* this might get overwritten in mpc8xxx_probe() */ 246 .irq_set_type = mpc8xxx_irq_set_type, 247 }; 248 249 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, 250 irq_hw_number_t hwirq) 251 { 252 irq_set_chip_data(irq, h->host_data); 253 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); 254 255 return 0; 256 } 257 258 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 259 .map = mpc8xxx_gpio_irq_map, 260 .xlate = irq_domain_xlate_twocell, 261 }; 262 263 struct mpc8xxx_gpio_devtype { 264 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); 265 int (*gpio_get)(struct gpio_chip *, unsigned int); 266 int (*irq_set_type)(struct irq_data *, unsigned int); 267 }; 268 269 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { 270 .gpio_dir_out = mpc5121_gpio_dir_out, 271 .irq_set_type = mpc512x_irq_set_type, 272 }; 273 274 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { 275 .gpio_dir_out = mpc5125_gpio_dir_out, 276 .irq_set_type = mpc512x_irq_set_type, 277 }; 278 279 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { 280 .gpio_get = mpc8572_gpio_get, 281 }; 282 283 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { 284 .irq_set_type = mpc8xxx_irq_set_type, 285 }; 286 287 static const struct of_device_id mpc8xxx_gpio_ids[] = { 288 { .compatible = "fsl,mpc8314-gpio", }, 289 { .compatible = "fsl,mpc8349-gpio", }, 290 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, 291 { .compatible = "fsl,mpc8610-gpio", }, 292 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, 293 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, 294 { .compatible = "fsl,pq3-gpio", }, 295 { .compatible = "fsl,ls1028a-gpio", }, 296 { .compatible = "fsl,ls1088a-gpio", }, 297 { .compatible = "fsl,qoriq-gpio", }, 298 {} 299 }; 300 301 static int mpc8xxx_probe(struct platform_device *pdev) 302 { 303 const struct mpc8xxx_gpio_devtype *devtype = NULL; 304 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 305 struct device *dev = &pdev->dev; 306 struct fwnode_handle *fwnode; 307 struct gpio_chip *gc; 308 int ret; 309 310 mpc8xxx_gc = devm_kzalloc(dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); 311 if (!mpc8xxx_gc) 312 return -ENOMEM; 313 314 platform_set_drvdata(pdev, mpc8xxx_gc); 315 316 raw_spin_lock_init(&mpc8xxx_gc->lock); 317 318 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); 319 if (IS_ERR(mpc8xxx_gc->regs)) 320 return PTR_ERR(mpc8xxx_gc->regs); 321 322 gc = &mpc8xxx_gc->gc; 323 gc->parent = dev; 324 325 if (device_property_read_bool(dev, "little-endian")) { 326 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 327 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 328 NULL, BGPIOF_BIG_ENDIAN); 329 if (ret) 330 return ret; 331 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); 332 } else { 333 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 334 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 335 NULL, BGPIOF_BIG_ENDIAN 336 | BGPIOF_BIG_ENDIAN_BYTE_ORDER); 337 if (ret) 338 return ret; 339 dev_dbg(dev, "GPIO registers are BIG endian\n"); 340 } 341 342 mpc8xxx_gc->direction_output = gc->direction_output; 343 344 devtype = device_get_match_data(dev); 345 if (!devtype) 346 devtype = &mpc8xxx_gpio_devtype_default; 347 348 /* 349 * It's assumed that only a single type of gpio controller is available 350 * on the current machine, so overwriting global data is fine. 351 */ 352 if (devtype->irq_set_type) 353 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; 354 355 if (devtype->gpio_dir_out) 356 gc->direction_output = devtype->gpio_dir_out; 357 if (devtype->gpio_get) 358 gc->get = devtype->gpio_get; 359 360 gc->to_irq = mpc8xxx_gpio_to_irq; 361 362 /* 363 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control 364 * the input enable of each individual GPIO port. When an individual 365 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the 366 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate 367 * the port value to the GPIO Data Register. 368 */ 369 fwnode = dev_fwnode(dev); 370 if (device_is_compatible(dev, "fsl,qoriq-gpio") || 371 device_is_compatible(dev, "fsl,ls1028a-gpio") || 372 device_is_compatible(dev, "fsl,ls1088a-gpio") || 373 is_acpi_node(fwnode)) { 374 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 375 /* Also, latch state of GPIOs configured as output by bootloader. */ 376 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & 377 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 378 } 379 380 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc); 381 if (ret) { 382 dev_err(dev, 383 "GPIO chip registration failed with status %d\n", ret); 384 return ret; 385 } 386 387 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); 388 if (mpc8xxx_gc->irqn < 0) 389 return mpc8xxx_gc->irqn; 390 391 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, 392 MPC8XXX_GPIO_PINS, 393 &mpc8xxx_gpio_irq_ops, 394 mpc8xxx_gc); 395 396 if (!mpc8xxx_gc->irq) 397 return 0; 398 399 /* ack and mask all irqs */ 400 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 401 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); 402 403 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, 404 mpc8xxx_gpio_irq_cascade, 405 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", 406 mpc8xxx_gc); 407 if (ret) { 408 dev_err(dev, "failed to devm_request_irq(%d), ret = %d\n", 409 mpc8xxx_gc->irqn, ret); 410 goto err; 411 } 412 413 device_init_wakeup(dev, true); 414 415 return 0; 416 err: 417 irq_domain_remove(mpc8xxx_gc->irq); 418 return ret; 419 } 420 421 static void mpc8xxx_remove(struct platform_device *pdev) 422 { 423 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); 424 425 if (mpc8xxx_gc->irq) { 426 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); 427 irq_domain_remove(mpc8xxx_gc->irq); 428 } 429 } 430 431 static int mpc8xxx_suspend(struct device *dev) 432 { 433 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 434 435 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 436 enable_irq_wake(mpc8xxx_gc->irqn); 437 438 return 0; 439 } 440 441 static int mpc8xxx_resume(struct device *dev) 442 { 443 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 444 445 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 446 disable_irq_wake(mpc8xxx_gc->irqn); 447 448 return 0; 449 } 450 451 static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops, 452 mpc8xxx_suspend, mpc8xxx_resume, NULL); 453 454 #ifdef CONFIG_ACPI 455 static const struct acpi_device_id gpio_acpi_ids[] = { 456 {"NXP0031",}, 457 { } 458 }; 459 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids); 460 #endif 461 462 static struct platform_driver mpc8xxx_plat_driver = { 463 .probe = mpc8xxx_probe, 464 .remove = mpc8xxx_remove, 465 .driver = { 466 .name = "gpio-mpc8xxx", 467 .of_match_table = mpc8xxx_gpio_ids, 468 .acpi_match_table = ACPI_PTR(gpio_acpi_ids), 469 .pm = pm_ptr(&mpc8xx_pm_ops), 470 }, 471 }; 472 473 static int __init mpc8xxx_init(void) 474 { 475 return platform_driver_register(&mpc8xxx_plat_driver); 476 } 477 478 arch_initcall(mpc8xxx_init); 479