1 /* 2 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible 3 * 4 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 5 * Copyright (C) 2016 Freescale Semiconductor Inc. 6 * 7 * This file is licensed under the terms of the GNU General Public License 8 * version 2. This program is licensed "as is" without any warranty of any 9 * kind, whether express or implied. 10 */ 11 12 #include <linux/kernel.h> 13 #include <linux/init.h> 14 #include <linux/spinlock.h> 15 #include <linux/io.h> 16 #include <linux/of.h> 17 #include <linux/of_gpio.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/slab.h> 22 #include <linux/irq.h> 23 #include <linux/gpio/driver.h> 24 #include <linux/bitops.h> 25 26 #define MPC8XXX_GPIO_PINS 32 27 28 #define GPIO_DIR 0x00 29 #define GPIO_ODR 0x04 30 #define GPIO_DAT 0x08 31 #define GPIO_IER 0x0c 32 #define GPIO_IMR 0x10 33 #define GPIO_ICR 0x14 34 #define GPIO_ICR2 0x18 35 #define GPIO_IBE 0x18 36 37 struct mpc8xxx_gpio_chip { 38 struct gpio_chip gc; 39 void __iomem *regs; 40 raw_spinlock_t lock; 41 42 int (*direction_output)(struct gpio_chip *chip, 43 unsigned offset, int value); 44 45 struct irq_domain *irq; 46 unsigned int irqn; 47 }; 48 49 /* The GPIO Input Buffer Enable register(GPIO_IBE) is used to 50 * control the input enable of each individual GPIO port. 51 * When an individual GPIO port’s direction is set to 52 * input (GPIO_GPDIR[DRn=0]), the associated input enable must be 53 * set (GPIOxGPIE[IEn]=1) to propagate the port value to the GPIO 54 * Data Register. 55 */ 56 static int ls1028a_gpio_dir_in_init(struct gpio_chip *gc) 57 { 58 unsigned long flags; 59 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 60 61 spin_lock_irqsave(&gc->bgpio_lock, flags); 62 63 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 64 65 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 66 67 return 0; 68 } 69 70 /* 71 * This hardware has a big endian bit assignment such that GPIO line 0 is 72 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. 73 * This inline helper give the right bitmask for a certain line. 74 */ 75 static inline u32 mpc_pin2mask(unsigned int offset) 76 { 77 return BIT(31 - offset); 78 } 79 80 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 81 * defined as output cannot be determined by reading GPDAT register, 82 * so we use shadow data register instead. The status of input pins 83 * is determined by reading GPDAT register. 84 */ 85 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 86 { 87 u32 val; 88 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 89 u32 out_mask, out_shadow; 90 91 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 92 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 93 out_shadow = gc->bgpio_data & out_mask; 94 95 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 96 } 97 98 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, 99 unsigned int gpio, int val) 100 { 101 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 102 /* GPIO 28..31 are input only on MPC5121 */ 103 if (gpio >= 28) 104 return -EINVAL; 105 106 return mpc8xxx_gc->direction_output(gc, gpio, val); 107 } 108 109 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, 110 unsigned int gpio, int val) 111 { 112 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 113 /* GPIO 0..3 are input only on MPC5125 */ 114 if (gpio <= 3) 115 return -EINVAL; 116 117 return mpc8xxx_gc->direction_output(gc, gpio, val); 118 } 119 120 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 121 { 122 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 123 124 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 125 return irq_create_mapping(mpc8xxx_gc->irq, offset); 126 else 127 return -ENXIO; 128 } 129 130 static void mpc8xxx_gpio_irq_cascade(struct irq_desc *desc) 131 { 132 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_desc_get_handler_data(desc); 133 struct irq_chip *chip = irq_desc_get_chip(desc); 134 struct gpio_chip *gc = &mpc8xxx_gc->gc; 135 unsigned int mask; 136 137 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) 138 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); 139 if (mask) 140 generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq, 141 32 - ffs(mask))); 142 if (chip->irq_eoi) 143 chip->irq_eoi(&desc->irq_data); 144 } 145 146 static void mpc8xxx_irq_unmask(struct irq_data *d) 147 { 148 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 149 struct gpio_chip *gc = &mpc8xxx_gc->gc; 150 unsigned long flags; 151 152 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 153 154 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 155 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 156 | mpc_pin2mask(irqd_to_hwirq(d))); 157 158 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 159 } 160 161 static void mpc8xxx_irq_mask(struct irq_data *d) 162 { 163 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 164 struct gpio_chip *gc = &mpc8xxx_gc->gc; 165 unsigned long flags; 166 167 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 168 169 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 170 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 171 & ~mpc_pin2mask(irqd_to_hwirq(d))); 172 173 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 174 } 175 176 static void mpc8xxx_irq_ack(struct irq_data *d) 177 { 178 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 179 struct gpio_chip *gc = &mpc8xxx_gc->gc; 180 181 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 182 mpc_pin2mask(irqd_to_hwirq(d))); 183 } 184 185 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 186 { 187 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 188 struct gpio_chip *gc = &mpc8xxx_gc->gc; 189 unsigned long flags; 190 191 switch (flow_type) { 192 case IRQ_TYPE_EDGE_FALLING: 193 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 194 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 195 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 196 | mpc_pin2mask(irqd_to_hwirq(d))); 197 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 198 break; 199 200 case IRQ_TYPE_EDGE_BOTH: 201 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 202 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 203 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 204 & ~mpc_pin2mask(irqd_to_hwirq(d))); 205 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 206 break; 207 208 default: 209 return -EINVAL; 210 } 211 212 return 0; 213 } 214 215 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 216 { 217 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 218 struct gpio_chip *gc = &mpc8xxx_gc->gc; 219 unsigned long gpio = irqd_to_hwirq(d); 220 void __iomem *reg; 221 unsigned int shift; 222 unsigned long flags; 223 224 if (gpio < 16) { 225 reg = mpc8xxx_gc->regs + GPIO_ICR; 226 shift = (15 - gpio) * 2; 227 } else { 228 reg = mpc8xxx_gc->regs + GPIO_ICR2; 229 shift = (15 - (gpio % 16)) * 2; 230 } 231 232 switch (flow_type) { 233 case IRQ_TYPE_EDGE_FALLING: 234 case IRQ_TYPE_LEVEL_LOW: 235 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 236 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 237 | (2 << shift)); 238 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 239 break; 240 241 case IRQ_TYPE_EDGE_RISING: 242 case IRQ_TYPE_LEVEL_HIGH: 243 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 244 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 245 | (1 << shift)); 246 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 247 break; 248 249 case IRQ_TYPE_EDGE_BOTH: 250 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 251 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); 252 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 253 break; 254 255 default: 256 return -EINVAL; 257 } 258 259 return 0; 260 } 261 262 static struct irq_chip mpc8xxx_irq_chip = { 263 .name = "mpc8xxx-gpio", 264 .irq_unmask = mpc8xxx_irq_unmask, 265 .irq_mask = mpc8xxx_irq_mask, 266 .irq_ack = mpc8xxx_irq_ack, 267 /* this might get overwritten in mpc8xxx_probe() */ 268 .irq_set_type = mpc8xxx_irq_set_type, 269 }; 270 271 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, 272 irq_hw_number_t hwirq) 273 { 274 irq_set_chip_data(irq, h->host_data); 275 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); 276 277 return 0; 278 } 279 280 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 281 .map = mpc8xxx_gpio_irq_map, 282 .xlate = irq_domain_xlate_twocell, 283 }; 284 285 struct mpc8xxx_gpio_devtype { 286 int (*gpio_dir_in_init)(struct gpio_chip *chip); 287 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); 288 int (*gpio_get)(struct gpio_chip *, unsigned int); 289 int (*irq_set_type)(struct irq_data *, unsigned int); 290 }; 291 292 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { 293 .gpio_dir_out = mpc5121_gpio_dir_out, 294 .irq_set_type = mpc512x_irq_set_type, 295 }; 296 297 static const struct mpc8xxx_gpio_devtype ls1028a_gpio_devtype = { 298 .gpio_dir_in_init = ls1028a_gpio_dir_in_init, 299 }; 300 301 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { 302 .gpio_dir_out = mpc5125_gpio_dir_out, 303 .irq_set_type = mpc512x_irq_set_type, 304 }; 305 306 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { 307 .gpio_get = mpc8572_gpio_get, 308 }; 309 310 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { 311 .irq_set_type = mpc8xxx_irq_set_type, 312 }; 313 314 static const struct of_device_id mpc8xxx_gpio_ids[] = { 315 { .compatible = "fsl,mpc8349-gpio", }, 316 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, 317 { .compatible = "fsl,mpc8610-gpio", }, 318 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, 319 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, 320 { .compatible = "fsl,pq3-gpio", }, 321 { .compatible = "fsl,ls1028a-gpio", .data = &ls1028a_gpio_devtype, }, 322 { .compatible = "fsl,ls1088a-gpio", .data = &ls1028a_gpio_devtype, }, 323 { .compatible = "fsl,qoriq-gpio", }, 324 {} 325 }; 326 327 static int mpc8xxx_probe(struct platform_device *pdev) 328 { 329 struct device_node *np = pdev->dev.of_node; 330 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 331 struct gpio_chip *gc; 332 const struct mpc8xxx_gpio_devtype *devtype = 333 of_device_get_match_data(&pdev->dev); 334 int ret; 335 336 mpc8xxx_gc = devm_kzalloc(&pdev->dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); 337 if (!mpc8xxx_gc) 338 return -ENOMEM; 339 340 platform_set_drvdata(pdev, mpc8xxx_gc); 341 342 raw_spin_lock_init(&mpc8xxx_gc->lock); 343 344 mpc8xxx_gc->regs = of_iomap(np, 0); 345 if (!mpc8xxx_gc->regs) 346 return -ENOMEM; 347 348 gc = &mpc8xxx_gc->gc; 349 350 if (of_property_read_bool(np, "little-endian")) { 351 ret = bgpio_init(gc, &pdev->dev, 4, 352 mpc8xxx_gc->regs + GPIO_DAT, 353 NULL, NULL, 354 mpc8xxx_gc->regs + GPIO_DIR, NULL, 355 BGPIOF_BIG_ENDIAN); 356 if (ret) 357 goto err; 358 dev_dbg(&pdev->dev, "GPIO registers are LITTLE endian\n"); 359 } else { 360 ret = bgpio_init(gc, &pdev->dev, 4, 361 mpc8xxx_gc->regs + GPIO_DAT, 362 NULL, NULL, 363 mpc8xxx_gc->regs + GPIO_DIR, NULL, 364 BGPIOF_BIG_ENDIAN 365 | BGPIOF_BIG_ENDIAN_BYTE_ORDER); 366 if (ret) 367 goto err; 368 dev_dbg(&pdev->dev, "GPIO registers are BIG endian\n"); 369 } 370 371 mpc8xxx_gc->direction_output = gc->direction_output; 372 373 if (!devtype) 374 devtype = &mpc8xxx_gpio_devtype_default; 375 376 /* 377 * It's assumed that only a single type of gpio controller is available 378 * on the current machine, so overwriting global data is fine. 379 */ 380 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; 381 382 if (devtype->gpio_dir_out) 383 gc->direction_output = devtype->gpio_dir_out; 384 if (devtype->gpio_get) 385 gc->get = devtype->gpio_get; 386 387 gc->to_irq = mpc8xxx_gpio_to_irq; 388 389 ret = gpiochip_add_data(gc, mpc8xxx_gc); 390 if (ret) { 391 pr_err("%pOF: GPIO chip registration failed with status %d\n", 392 np, ret); 393 goto err; 394 } 395 396 mpc8xxx_gc->irqn = irq_of_parse_and_map(np, 0); 397 if (!mpc8xxx_gc->irqn) 398 return 0; 399 400 mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS, 401 &mpc8xxx_gpio_irq_ops, mpc8xxx_gc); 402 if (!mpc8xxx_gc->irq) 403 return 0; 404 405 /* ack and mask all irqs */ 406 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 407 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); 408 /* enable input buffer */ 409 if (devtype->gpio_dir_in_init) 410 devtype->gpio_dir_in_init(gc); 411 412 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, 413 mpc8xxx_gpio_irq_cascade, mpc8xxx_gc); 414 return 0; 415 err: 416 iounmap(mpc8xxx_gc->regs); 417 return ret; 418 } 419 420 static int mpc8xxx_remove(struct platform_device *pdev) 421 { 422 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); 423 424 if (mpc8xxx_gc->irq) { 425 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); 426 irq_domain_remove(mpc8xxx_gc->irq); 427 } 428 429 gpiochip_remove(&mpc8xxx_gc->gc); 430 iounmap(mpc8xxx_gc->regs); 431 432 return 0; 433 } 434 435 static struct platform_driver mpc8xxx_plat_driver = { 436 .probe = mpc8xxx_probe, 437 .remove = mpc8xxx_remove, 438 .driver = { 439 .name = "gpio-mpc8xxx", 440 .of_match_table = mpc8xxx_gpio_ids, 441 }, 442 }; 443 444 static int __init mpc8xxx_init(void) 445 { 446 return platform_driver_register(&mpc8xxx_plat_driver); 447 } 448 449 arch_initcall(mpc8xxx_init); 450