1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible 4 * 5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2016 Freescale Semiconductor Inc. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/irq.h> 16 #include <linux/kernel.h> 17 #include <linux/mod_devicetable.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/property.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 25 #define MPC8XXX_GPIO_PINS 32 26 27 #define GPIO_DIR 0x00 28 #define GPIO_ODR 0x04 29 #define GPIO_DAT 0x08 30 #define GPIO_IER 0x0c 31 #define GPIO_IMR 0x10 32 #define GPIO_ICR 0x14 33 #define GPIO_ICR2 0x18 34 #define GPIO_IBE 0x18 35 36 struct mpc8xxx_gpio_chip { 37 struct gpio_chip gc; 38 void __iomem *regs; 39 raw_spinlock_t lock; 40 41 int (*direction_output)(struct gpio_chip *chip, 42 unsigned offset, int value); 43 44 struct irq_domain *irq; 45 int irqn; 46 }; 47 48 /* 49 * This hardware has a big endian bit assignment such that GPIO line 0 is 50 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. 51 * This inline helper give the right bitmask for a certain line. 52 */ 53 static inline u32 mpc_pin2mask(unsigned int offset) 54 { 55 return BIT(31 - offset); 56 } 57 58 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 59 * defined as output cannot be determined by reading GPDAT register, 60 * so we use shadow data register instead. The status of input pins 61 * is determined by reading GPDAT register. 62 */ 63 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 64 { 65 u32 val; 66 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 67 u32 out_mask, out_shadow; 68 69 out_mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 70 val = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 71 out_shadow = gc->bgpio_data & out_mask; 72 73 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 74 } 75 76 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, 77 unsigned int gpio, int val) 78 { 79 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 80 /* GPIO 28..31 are input only on MPC5121 */ 81 if (gpio >= 28) 82 return -EINVAL; 83 84 return mpc8xxx_gc->direction_output(gc, gpio, val); 85 } 86 87 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, 88 unsigned int gpio, int val) 89 { 90 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 91 /* GPIO 0..3 are input only on MPC5125 */ 92 if (gpio <= 3) 93 return -EINVAL; 94 95 return mpc8xxx_gc->direction_output(gc, gpio, val); 96 } 97 98 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 99 { 100 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 101 102 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 103 return irq_create_mapping(mpc8xxx_gc->irq, offset); 104 else 105 return -ENXIO; 106 } 107 108 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) 109 { 110 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; 111 struct gpio_chip *gc = &mpc8xxx_gc->gc; 112 unsigned long mask; 113 int i; 114 115 mask = gc->read_reg(mpc8xxx_gc->regs + GPIO_IER) 116 & gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR); 117 for_each_set_bit(i, &mask, 32) 118 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); 119 120 return IRQ_HANDLED; 121 } 122 123 static void mpc8xxx_irq_unmask(struct irq_data *d) 124 { 125 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 126 irq_hw_number_t hwirq = irqd_to_hwirq(d); 127 struct gpio_chip *gc = &mpc8xxx_gc->gc; 128 unsigned long flags; 129 130 gpiochip_enable_irq(gc, hwirq); 131 132 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 133 134 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 135 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 136 | mpc_pin2mask(irqd_to_hwirq(d))); 137 138 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 139 } 140 141 static void mpc8xxx_irq_mask(struct irq_data *d) 142 { 143 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 144 irq_hw_number_t hwirq = irqd_to_hwirq(d); 145 struct gpio_chip *gc = &mpc8xxx_gc->gc; 146 unsigned long flags; 147 148 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 149 150 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 151 gc->read_reg(mpc8xxx_gc->regs + GPIO_IMR) 152 & ~mpc_pin2mask(irqd_to_hwirq(d))); 153 154 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 155 156 gpiochip_disable_irq(gc, hwirq); 157 } 158 159 static void mpc8xxx_irq_ack(struct irq_data *d) 160 { 161 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 162 struct gpio_chip *gc = &mpc8xxx_gc->gc; 163 164 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 165 mpc_pin2mask(irqd_to_hwirq(d))); 166 } 167 168 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 169 { 170 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 171 struct gpio_chip *gc = &mpc8xxx_gc->gc; 172 unsigned long flags; 173 174 switch (flow_type) { 175 case IRQ_TYPE_EDGE_FALLING: 176 case IRQ_TYPE_LEVEL_LOW: 177 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 178 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 179 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 180 | mpc_pin2mask(irqd_to_hwirq(d))); 181 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 182 break; 183 184 case IRQ_TYPE_EDGE_BOTH: 185 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 186 gc->write_reg(mpc8xxx_gc->regs + GPIO_ICR, 187 gc->read_reg(mpc8xxx_gc->regs + GPIO_ICR) 188 & ~mpc_pin2mask(irqd_to_hwirq(d))); 189 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 190 break; 191 192 default: 193 return -EINVAL; 194 } 195 196 return 0; 197 } 198 199 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 200 { 201 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 202 struct gpio_chip *gc = &mpc8xxx_gc->gc; 203 unsigned long gpio = irqd_to_hwirq(d); 204 void __iomem *reg; 205 unsigned int shift; 206 unsigned long flags; 207 208 if (gpio < 16) { 209 reg = mpc8xxx_gc->regs + GPIO_ICR; 210 shift = (15 - gpio) * 2; 211 } else { 212 reg = mpc8xxx_gc->regs + GPIO_ICR2; 213 shift = (15 - (gpio % 16)) * 2; 214 } 215 216 switch (flow_type) { 217 case IRQ_TYPE_EDGE_FALLING: 218 case IRQ_TYPE_LEVEL_LOW: 219 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 220 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 221 | (2 << shift)); 222 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 223 break; 224 225 case IRQ_TYPE_EDGE_RISING: 226 case IRQ_TYPE_LEVEL_HIGH: 227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 228 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift)) 229 | (1 << shift)); 230 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 231 break; 232 233 case IRQ_TYPE_EDGE_BOTH: 234 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 235 gc->write_reg(reg, (gc->read_reg(reg) & ~(3 << shift))); 236 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 237 break; 238 239 default: 240 return -EINVAL; 241 } 242 243 return 0; 244 } 245 246 static struct irq_chip mpc8xxx_irq_chip = { 247 .name = "mpc8xxx-gpio", 248 .irq_unmask = mpc8xxx_irq_unmask, 249 .irq_mask = mpc8xxx_irq_mask, 250 .irq_ack = mpc8xxx_irq_ack, 251 /* this might get overwritten in mpc8xxx_probe() */ 252 .irq_set_type = mpc8xxx_irq_set_type, 253 .flags = IRQCHIP_IMMUTABLE, 254 GPIOCHIP_IRQ_RESOURCE_HELPERS, 255 }; 256 257 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, 258 irq_hw_number_t hwirq) 259 { 260 irq_set_chip_data(irq, h->host_data); 261 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); 262 263 return 0; 264 } 265 266 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 267 .map = mpc8xxx_gpio_irq_map, 268 .xlate = irq_domain_xlate_twocell, 269 }; 270 271 struct mpc8xxx_gpio_devtype { 272 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); 273 int (*gpio_get)(struct gpio_chip *, unsigned int); 274 int (*irq_set_type)(struct irq_data *, unsigned int); 275 }; 276 277 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { 278 .gpio_dir_out = mpc5121_gpio_dir_out, 279 .irq_set_type = mpc512x_irq_set_type, 280 }; 281 282 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { 283 .gpio_dir_out = mpc5125_gpio_dir_out, 284 .irq_set_type = mpc512x_irq_set_type, 285 }; 286 287 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { 288 .gpio_get = mpc8572_gpio_get, 289 }; 290 291 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { 292 .irq_set_type = mpc8xxx_irq_set_type, 293 }; 294 295 static const struct of_device_id mpc8xxx_gpio_ids[] = { 296 { .compatible = "fsl,mpc8314-gpio", }, 297 { .compatible = "fsl,mpc8349-gpio", }, 298 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, 299 { .compatible = "fsl,mpc8610-gpio", }, 300 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, 301 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, 302 { .compatible = "fsl,pq3-gpio", }, 303 { .compatible = "fsl,ls1028a-gpio", }, 304 { .compatible = "fsl,ls1088a-gpio", }, 305 { .compatible = "fsl,qoriq-gpio", }, 306 {} 307 }; 308 309 static int mpc8xxx_probe(struct platform_device *pdev) 310 { 311 const struct mpc8xxx_gpio_devtype *devtype = NULL; 312 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 313 struct device *dev = &pdev->dev; 314 struct fwnode_handle *fwnode; 315 struct gpio_chip *gc; 316 int ret; 317 318 mpc8xxx_gc = devm_kzalloc(dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); 319 if (!mpc8xxx_gc) 320 return -ENOMEM; 321 322 platform_set_drvdata(pdev, mpc8xxx_gc); 323 324 raw_spin_lock_init(&mpc8xxx_gc->lock); 325 326 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); 327 if (IS_ERR(mpc8xxx_gc->regs)) 328 return PTR_ERR(mpc8xxx_gc->regs); 329 330 gc = &mpc8xxx_gc->gc; 331 gc->parent = dev; 332 333 if (device_property_read_bool(dev, "little-endian")) { 334 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 335 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 336 NULL, BGPIOF_BIG_ENDIAN); 337 if (ret) 338 return ret; 339 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); 340 } else { 341 ret = bgpio_init(gc, dev, 4, mpc8xxx_gc->regs + GPIO_DAT, 342 NULL, NULL, mpc8xxx_gc->regs + GPIO_DIR, 343 NULL, BGPIOF_BIG_ENDIAN 344 | BGPIOF_BIG_ENDIAN_BYTE_ORDER); 345 if (ret) 346 return ret; 347 dev_dbg(dev, "GPIO registers are BIG endian\n"); 348 } 349 350 mpc8xxx_gc->direction_output = gc->direction_output; 351 352 devtype = device_get_match_data(dev); 353 if (!devtype) 354 devtype = &mpc8xxx_gpio_devtype_default; 355 356 /* 357 * It's assumed that only a single type of gpio controller is available 358 * on the current machine, so overwriting global data is fine. 359 */ 360 if (devtype->irq_set_type) 361 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; 362 363 if (devtype->gpio_dir_out) 364 gc->direction_output = devtype->gpio_dir_out; 365 if (devtype->gpio_get) 366 gc->get = devtype->gpio_get; 367 368 gc->to_irq = mpc8xxx_gpio_to_irq; 369 370 /* 371 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control 372 * the input enable of each individual GPIO port. When an individual 373 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the 374 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate 375 * the port value to the GPIO Data Register. 376 */ 377 fwnode = dev_fwnode(dev); 378 if (device_is_compatible(dev, "fsl,qoriq-gpio") || 379 device_is_compatible(dev, "fsl,ls1028a-gpio") || 380 device_is_compatible(dev, "fsl,ls1088a-gpio") || 381 is_acpi_node(fwnode)) { 382 gc->write_reg(mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 383 /* Also, latch state of GPIOs configured as output by bootloader. */ 384 gc->bgpio_data = gc->read_reg(mpc8xxx_gc->regs + GPIO_DAT) & 385 gc->read_reg(mpc8xxx_gc->regs + GPIO_DIR); 386 } 387 388 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc); 389 if (ret) { 390 dev_err(dev, 391 "GPIO chip registration failed with status %d\n", ret); 392 return ret; 393 } 394 395 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); 396 if (mpc8xxx_gc->irqn < 0) 397 return mpc8xxx_gc->irqn; 398 399 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, 400 MPC8XXX_GPIO_PINS, 401 &mpc8xxx_gpio_irq_ops, 402 mpc8xxx_gc); 403 404 if (!mpc8xxx_gc->irq) 405 return 0; 406 407 /* ack and mask all irqs */ 408 gc->write_reg(mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 409 gc->write_reg(mpc8xxx_gc->regs + GPIO_IMR, 0); 410 411 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, 412 mpc8xxx_gpio_irq_cascade, 413 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", 414 mpc8xxx_gc); 415 if (ret) { 416 dev_err(dev, "failed to devm_request_irq(%d), ret = %d\n", 417 mpc8xxx_gc->irqn, ret); 418 goto err; 419 } 420 421 ret = devm_device_init_wakeup(dev); 422 if (ret) 423 return dev_err_probe(dev, ret, "Failed to init wakeup\n"); 424 425 return 0; 426 err: 427 irq_domain_remove(mpc8xxx_gc->irq); 428 return ret; 429 } 430 431 static void mpc8xxx_remove(struct platform_device *pdev) 432 { 433 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); 434 435 if (mpc8xxx_gc->irq) { 436 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); 437 irq_domain_remove(mpc8xxx_gc->irq); 438 } 439 } 440 441 static int mpc8xxx_suspend(struct device *dev) 442 { 443 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 444 445 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 446 enable_irq_wake(mpc8xxx_gc->irqn); 447 448 return 0; 449 } 450 451 static int mpc8xxx_resume(struct device *dev) 452 { 453 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 454 455 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 456 disable_irq_wake(mpc8xxx_gc->irqn); 457 458 return 0; 459 } 460 461 static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops, 462 mpc8xxx_suspend, mpc8xxx_resume, NULL); 463 464 #ifdef CONFIG_ACPI 465 static const struct acpi_device_id gpio_acpi_ids[] = { 466 {"NXP0031",}, 467 { } 468 }; 469 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids); 470 #endif 471 472 static struct platform_driver mpc8xxx_plat_driver = { 473 .probe = mpc8xxx_probe, 474 .remove = mpc8xxx_remove, 475 .driver = { 476 .name = "gpio-mpc8xxx", 477 .of_match_table = mpc8xxx_gpio_ids, 478 .acpi_match_table = ACPI_PTR(gpio_acpi_ids), 479 .pm = pm_ptr(&mpc8xx_pm_ops), 480 }, 481 }; 482 483 static int __init mpc8xxx_init(void) 484 { 485 return platform_driver_register(&mpc8xxx_plat_driver); 486 } 487 488 arch_initcall(mpc8xxx_init); 489