1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * GPIOs on MPC512x/8349/8572/8610/QorIQ and compatible 4 * 5 * Copyright (C) 2008 Peter Korsgaard <jacmet@sunsite.dk> 6 * Copyright (C) 2016 Freescale Semiconductor Inc. 7 */ 8 9 #include <linux/acpi.h> 10 #include <linux/bitops.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/gpio/generic.h> 13 #include <linux/init.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/irq.h> 17 #include <linux/kernel.h> 18 #include <linux/mod_devicetable.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/property.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 26 #define MPC8XXX_GPIO_PINS 32 27 28 #define GPIO_DIR 0x00 29 #define GPIO_ODR 0x04 30 #define GPIO_DAT 0x08 31 #define GPIO_IER 0x0c 32 #define GPIO_IMR 0x10 33 #define GPIO_ICR 0x14 34 #define GPIO_ICR2 0x18 35 #define GPIO_IBE 0x18 36 37 struct mpc8xxx_gpio_chip { 38 struct gpio_generic_chip chip; 39 void __iomem *regs; 40 raw_spinlock_t lock; 41 42 int (*direction_output)(struct gpio_chip *chip, 43 unsigned offset, int value); 44 45 struct irq_domain *irq; 46 int irqn; 47 }; 48 49 /* 50 * This hardware has a big endian bit assignment such that GPIO line 0 is 51 * connected to bit 31, line 1 to bit 30 ... line 31 to bit 0. 52 * This inline helper give the right bitmask for a certain line. 53 */ 54 static inline u32 mpc_pin2mask(unsigned int offset) 55 { 56 return BIT(31 - offset); 57 } 58 59 /* Workaround GPIO 1 errata on MPC8572/MPC8536. The status of GPIOs 60 * defined as output cannot be determined by reading GPDAT register, 61 * so we use shadow data register instead. The status of input pins 62 * is determined by reading GPDAT register. 63 */ 64 static int mpc8572_gpio_get(struct gpio_chip *gc, unsigned int gpio) 65 { 66 u32 val; 67 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 68 u32 out_mask, out_shadow; 69 70 out_mask = gpio_generic_read_reg(&mpc8xxx_gc->chip, 71 mpc8xxx_gc->regs + GPIO_DIR); 72 val = gpio_generic_read_reg(&mpc8xxx_gc->chip, 73 mpc8xxx_gc->regs + GPIO_DAT) & ~out_mask; 74 out_shadow = mpc8xxx_gc->chip.sdata & out_mask; 75 76 return !!((val | out_shadow) & mpc_pin2mask(gpio)); 77 } 78 79 static int mpc5121_gpio_dir_out(struct gpio_chip *gc, 80 unsigned int gpio, int val) 81 { 82 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 83 /* GPIO 28..31 are input only on MPC5121 */ 84 if (gpio >= 28) 85 return -EINVAL; 86 87 return mpc8xxx_gc->direction_output(gc, gpio, val); 88 } 89 90 static int mpc5125_gpio_dir_out(struct gpio_chip *gc, 91 unsigned int gpio, int val) 92 { 93 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 94 /* GPIO 0..3 are input only on MPC5125 */ 95 if (gpio <= 3) 96 return -EINVAL; 97 98 return mpc8xxx_gc->direction_output(gc, gpio, val); 99 } 100 101 static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset) 102 { 103 struct mpc8xxx_gpio_chip *mpc8xxx_gc = gpiochip_get_data(gc); 104 105 if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS) 106 return irq_create_mapping(mpc8xxx_gc->irq, offset); 107 else 108 return -ENXIO; 109 } 110 111 static irqreturn_t mpc8xxx_gpio_irq_cascade(int irq, void *data) 112 { 113 struct mpc8xxx_gpio_chip *mpc8xxx_gc = data; 114 unsigned long mask; 115 int i; 116 117 mask = gpio_generic_read_reg(&mpc8xxx_gc->chip, 118 mpc8xxx_gc->regs + GPIO_IER) & 119 gpio_generic_read_reg(&mpc8xxx_gc->chip, 120 mpc8xxx_gc->regs + GPIO_IMR); 121 for_each_set_bit(i, &mask, 32) 122 generic_handle_domain_irq(mpc8xxx_gc->irq, 31 - i); 123 124 return IRQ_HANDLED; 125 } 126 127 static void mpc8xxx_irq_unmask(struct irq_data *d) 128 { 129 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 130 irq_hw_number_t hwirq = irqd_to_hwirq(d); 131 struct gpio_chip *gc = &mpc8xxx_gc->chip.gc; 132 unsigned long flags; 133 134 gpiochip_enable_irq(gc, hwirq); 135 136 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 137 138 gpio_generic_write_reg(&mpc8xxx_gc->chip, 139 mpc8xxx_gc->regs + GPIO_IMR, 140 gpio_generic_read_reg(&mpc8xxx_gc->chip, 141 mpc8xxx_gc->regs + GPIO_IMR) 142 | mpc_pin2mask(irqd_to_hwirq(d))); 143 144 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 145 } 146 147 static void mpc8xxx_irq_mask(struct irq_data *d) 148 { 149 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 150 irq_hw_number_t hwirq = irqd_to_hwirq(d); 151 struct gpio_chip *gc = &mpc8xxx_gc->chip.gc; 152 unsigned long flags; 153 154 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 155 156 gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IMR, 157 gpio_generic_read_reg(&mpc8xxx_gc->chip, 158 mpc8xxx_gc->regs + GPIO_IMR) 159 & ~mpc_pin2mask(irqd_to_hwirq(d))); 160 161 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 162 163 gpiochip_disable_irq(gc, hwirq); 164 } 165 166 static void mpc8xxx_irq_ack(struct irq_data *d) 167 { 168 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 169 170 gpio_generic_write_reg(&mpc8xxx_gc->chip, mpc8xxx_gc->regs + GPIO_IER, 171 mpc_pin2mask(irqd_to_hwirq(d))); 172 } 173 174 static int mpc8xxx_irq_set_type(struct irq_data *d, unsigned int flow_type) 175 { 176 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 177 unsigned long flags; 178 179 switch (flow_type) { 180 case IRQ_TYPE_EDGE_FALLING: 181 case IRQ_TYPE_LEVEL_LOW: 182 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 183 gpio_generic_write_reg(&mpc8xxx_gc->chip, 184 mpc8xxx_gc->regs + GPIO_ICR, 185 gpio_generic_read_reg(&mpc8xxx_gc->chip, 186 mpc8xxx_gc->regs + GPIO_ICR) 187 | mpc_pin2mask(irqd_to_hwirq(d))); 188 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 189 break; 190 191 case IRQ_TYPE_EDGE_BOTH: 192 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 193 gpio_generic_write_reg(&mpc8xxx_gc->chip, 194 mpc8xxx_gc->regs + GPIO_ICR, 195 gpio_generic_read_reg(&mpc8xxx_gc->chip, 196 mpc8xxx_gc->regs + GPIO_ICR) 197 & ~mpc_pin2mask(irqd_to_hwirq(d))); 198 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 199 break; 200 201 default: 202 return -EINVAL; 203 } 204 205 return 0; 206 } 207 208 static int mpc512x_irq_set_type(struct irq_data *d, unsigned int flow_type) 209 { 210 struct mpc8xxx_gpio_chip *mpc8xxx_gc = irq_data_get_irq_chip_data(d); 211 unsigned long gpio = irqd_to_hwirq(d); 212 void __iomem *reg; 213 unsigned int shift; 214 unsigned long flags; 215 216 if (gpio < 16) { 217 reg = mpc8xxx_gc->regs + GPIO_ICR; 218 shift = (15 - gpio) * 2; 219 } else { 220 reg = mpc8xxx_gc->regs + GPIO_ICR2; 221 shift = (15 - (gpio % 16)) * 2; 222 } 223 224 switch (flow_type) { 225 case IRQ_TYPE_EDGE_FALLING: 226 case IRQ_TYPE_LEVEL_LOW: 227 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 228 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 229 (gpio_generic_read_reg(&mpc8xxx_gc->chip, 230 reg) & ~(3 << shift)) 231 | (2 << shift)); 232 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 233 break; 234 235 case IRQ_TYPE_EDGE_RISING: 236 case IRQ_TYPE_LEVEL_HIGH: 237 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 238 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 239 (gpio_generic_read_reg(&mpc8xxx_gc->chip, 240 reg) & ~(3 << shift)) 241 | (1 << shift)); 242 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 243 break; 244 245 case IRQ_TYPE_EDGE_BOTH: 246 raw_spin_lock_irqsave(&mpc8xxx_gc->lock, flags); 247 gpio_generic_write_reg(&mpc8xxx_gc->chip, reg, 248 (gpio_generic_read_reg(&mpc8xxx_gc->chip, 249 reg) & ~(3 << shift))); 250 raw_spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags); 251 break; 252 253 default: 254 return -EINVAL; 255 } 256 257 return 0; 258 } 259 260 static struct irq_chip mpc8xxx_irq_chip = { 261 .name = "mpc8xxx-gpio", 262 .irq_unmask = mpc8xxx_irq_unmask, 263 .irq_mask = mpc8xxx_irq_mask, 264 .irq_ack = mpc8xxx_irq_ack, 265 /* this might get overwritten in mpc8xxx_probe() */ 266 .irq_set_type = mpc8xxx_irq_set_type, 267 .flags = IRQCHIP_IMMUTABLE, 268 GPIOCHIP_IRQ_RESOURCE_HELPERS, 269 }; 270 271 static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq, 272 irq_hw_number_t hwirq) 273 { 274 irq_set_chip_data(irq, h->host_data); 275 irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_edge_irq); 276 277 return 0; 278 } 279 280 static const struct irq_domain_ops mpc8xxx_gpio_irq_ops = { 281 .map = mpc8xxx_gpio_irq_map, 282 .xlate = irq_domain_xlate_twocell, 283 }; 284 285 struct mpc8xxx_gpio_devtype { 286 int (*gpio_dir_out)(struct gpio_chip *, unsigned int, int); 287 int (*gpio_get)(struct gpio_chip *, unsigned int); 288 int (*irq_set_type)(struct irq_data *, unsigned int); 289 }; 290 291 static const struct mpc8xxx_gpio_devtype mpc512x_gpio_devtype = { 292 .gpio_dir_out = mpc5121_gpio_dir_out, 293 .irq_set_type = mpc512x_irq_set_type, 294 }; 295 296 static const struct mpc8xxx_gpio_devtype mpc5125_gpio_devtype = { 297 .gpio_dir_out = mpc5125_gpio_dir_out, 298 .irq_set_type = mpc512x_irq_set_type, 299 }; 300 301 static const struct mpc8xxx_gpio_devtype mpc8572_gpio_devtype = { 302 .gpio_get = mpc8572_gpio_get, 303 }; 304 305 static const struct mpc8xxx_gpio_devtype mpc8xxx_gpio_devtype_default = { 306 .irq_set_type = mpc8xxx_irq_set_type, 307 }; 308 309 static const struct of_device_id mpc8xxx_gpio_ids[] = { 310 { .compatible = "fsl,mpc8314-gpio", }, 311 { .compatible = "fsl,mpc8349-gpio", }, 312 { .compatible = "fsl,mpc8572-gpio", .data = &mpc8572_gpio_devtype, }, 313 { .compatible = "fsl,mpc8610-gpio", }, 314 { .compatible = "fsl,mpc5121-gpio", .data = &mpc512x_gpio_devtype, }, 315 { .compatible = "fsl,mpc5125-gpio", .data = &mpc5125_gpio_devtype, }, 316 { .compatible = "fsl,pq3-gpio", }, 317 { .compatible = "fsl,ls1028a-gpio", }, 318 { .compatible = "fsl,ls1088a-gpio", }, 319 { .compatible = "fsl,qoriq-gpio", }, 320 {} 321 }; 322 323 static int mpc8xxx_probe(struct platform_device *pdev) 324 { 325 const struct mpc8xxx_gpio_devtype *devtype = NULL; 326 struct gpio_generic_chip_config config; 327 struct mpc8xxx_gpio_chip *mpc8xxx_gc; 328 struct device *dev = &pdev->dev; 329 struct fwnode_handle *fwnode; 330 struct gpio_chip *gc; 331 int ret; 332 333 mpc8xxx_gc = devm_kzalloc(dev, sizeof(*mpc8xxx_gc), GFP_KERNEL); 334 if (!mpc8xxx_gc) 335 return -ENOMEM; 336 337 platform_set_drvdata(pdev, mpc8xxx_gc); 338 339 raw_spin_lock_init(&mpc8xxx_gc->lock); 340 341 mpc8xxx_gc->regs = devm_platform_ioremap_resource(pdev, 0); 342 if (IS_ERR(mpc8xxx_gc->regs)) 343 return PTR_ERR(mpc8xxx_gc->regs); 344 345 gc = &mpc8xxx_gc->chip.gc; 346 gc->parent = dev; 347 348 config = (struct gpio_generic_chip_config) { 349 .dev = dev, 350 .sz = 4, 351 .dat = mpc8xxx_gc->regs + GPIO_DAT, 352 .dirout = mpc8xxx_gc->regs + GPIO_DIR, 353 .flags = GPIO_GENERIC_BIG_ENDIAN 354 }; 355 356 if (device_property_read_bool(dev, "little-endian")) { 357 dev_dbg(dev, "GPIO registers are LITTLE endian\n"); 358 } else { 359 config.flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 360 dev_dbg(dev, "GPIO registers are BIG endian\n"); 361 } 362 363 ret = gpio_generic_chip_init(&mpc8xxx_gc->chip, &config); 364 if (ret) 365 return ret; 366 367 mpc8xxx_gc->direction_output = gc->direction_output; 368 369 devtype = device_get_match_data(dev); 370 if (!devtype) 371 devtype = &mpc8xxx_gpio_devtype_default; 372 373 /* 374 * It's assumed that only a single type of gpio controller is available 375 * on the current machine, so overwriting global data is fine. 376 */ 377 if (devtype->irq_set_type) 378 mpc8xxx_irq_chip.irq_set_type = devtype->irq_set_type; 379 380 if (devtype->gpio_dir_out) 381 gc->direction_output = devtype->gpio_dir_out; 382 if (devtype->gpio_get) 383 gc->get = devtype->gpio_get; 384 385 gc->to_irq = mpc8xxx_gpio_to_irq; 386 387 /* 388 * The GPIO Input Buffer Enable register(GPIO_IBE) is used to control 389 * the input enable of each individual GPIO port. When an individual 390 * GPIO port’s direction is set to input (GPIO_GPDIR[DRn=0]), the 391 * associated input enable must be set (GPIOxGPIE[IEn]=1) to propagate 392 * the port value to the GPIO Data Register. 393 */ 394 fwnode = dev_fwnode(dev); 395 if (device_is_compatible(dev, "fsl,qoriq-gpio") || 396 device_is_compatible(dev, "fsl,ls1028a-gpio") || 397 device_is_compatible(dev, "fsl,ls1088a-gpio") || 398 is_acpi_node(fwnode)) { 399 gpio_generic_write_reg(&mpc8xxx_gc->chip, 400 mpc8xxx_gc->regs + GPIO_IBE, 0xffffffff); 401 /* Also, latch state of GPIOs configured as output by bootloader. */ 402 mpc8xxx_gc->chip.sdata = 403 gpio_generic_read_reg(&mpc8xxx_gc->chip, 404 mpc8xxx_gc->regs + GPIO_DAT) & 405 gpio_generic_read_reg(&mpc8xxx_gc->chip, 406 mpc8xxx_gc->regs + GPIO_DIR); 407 } 408 409 ret = devm_gpiochip_add_data(dev, gc, mpc8xxx_gc); 410 if (ret) { 411 dev_err(dev, 412 "GPIO chip registration failed with status %d\n", ret); 413 return ret; 414 } 415 416 mpc8xxx_gc->irqn = platform_get_irq(pdev, 0); 417 if (mpc8xxx_gc->irqn < 0) 418 return mpc8xxx_gc->irqn; 419 420 mpc8xxx_gc->irq = irq_domain_create_linear(fwnode, 421 MPC8XXX_GPIO_PINS, 422 &mpc8xxx_gpio_irq_ops, 423 mpc8xxx_gc); 424 425 if (!mpc8xxx_gc->irq) 426 return 0; 427 428 /* ack and mask all irqs */ 429 gpio_generic_write_reg(&mpc8xxx_gc->chip, 430 mpc8xxx_gc->regs + GPIO_IER, 0xffffffff); 431 gpio_generic_write_reg(&mpc8xxx_gc->chip, 432 mpc8xxx_gc->regs + GPIO_IMR, 0); 433 434 ret = devm_request_irq(dev, mpc8xxx_gc->irqn, 435 mpc8xxx_gpio_irq_cascade, 436 IRQF_NO_THREAD | IRQF_SHARED, "gpio-cascade", 437 mpc8xxx_gc); 438 if (ret) { 439 dev_err(dev, "failed to devm_request_irq(%d), ret = %d\n", 440 mpc8xxx_gc->irqn, ret); 441 goto err; 442 } 443 444 ret = devm_device_init_wakeup(dev); 445 if (ret) 446 return dev_err_probe(dev, ret, "Failed to init wakeup\n"); 447 448 return 0; 449 err: 450 irq_domain_remove(mpc8xxx_gc->irq); 451 return ret; 452 } 453 454 static void mpc8xxx_remove(struct platform_device *pdev) 455 { 456 struct mpc8xxx_gpio_chip *mpc8xxx_gc = platform_get_drvdata(pdev); 457 458 if (mpc8xxx_gc->irq) { 459 irq_set_chained_handler_and_data(mpc8xxx_gc->irqn, NULL, NULL); 460 irq_domain_remove(mpc8xxx_gc->irq); 461 } 462 } 463 464 static int mpc8xxx_suspend(struct device *dev) 465 { 466 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 467 468 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 469 enable_irq_wake(mpc8xxx_gc->irqn); 470 471 return 0; 472 } 473 474 static int mpc8xxx_resume(struct device *dev) 475 { 476 struct mpc8xxx_gpio_chip *mpc8xxx_gc = dev_get_drvdata(dev); 477 478 if (mpc8xxx_gc->irqn && device_may_wakeup(dev)) 479 disable_irq_wake(mpc8xxx_gc->irqn); 480 481 return 0; 482 } 483 484 static DEFINE_RUNTIME_DEV_PM_OPS(mpc8xx_pm_ops, 485 mpc8xxx_suspend, mpc8xxx_resume, NULL); 486 487 #ifdef CONFIG_ACPI 488 static const struct acpi_device_id gpio_acpi_ids[] = { 489 {"NXP0031",}, 490 { } 491 }; 492 MODULE_DEVICE_TABLE(acpi, gpio_acpi_ids); 493 #endif 494 495 static struct platform_driver mpc8xxx_plat_driver = { 496 .probe = mpc8xxx_probe, 497 .remove = mpc8xxx_remove, 498 .driver = { 499 .name = "gpio-mpc8xxx", 500 .of_match_table = mpc8xxx_gpio_ids, 501 .acpi_match_table = ACPI_PTR(gpio_acpi_ids), 502 .pm = pm_ptr(&mpc8xx_pm_ops), 503 }, 504 }; 505 506 static int __init mpc8xxx_init(void) 507 { 508 return platform_driver_register(&mpc8xxx_plat_driver); 509 } 510 511 arch_initcall(mpc8xxx_init); 512