1 /* 2 * Generic driver for memory-mapped GPIO controllers. 3 * 4 * Copyright 2008 MontaVista Software, Inc. 5 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 * 12 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 13 * ...`` ```````.. 14 * ..The simplest form of a GPIO controller that the driver supports is`` 15 * `.just a single "data" register, where GPIO state can be read and/or ` 16 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 17 * ````````` 18 ___ 19 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 20 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 21 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 22 `....trivial..'~`.```.``` 23 * ``````` 24 * .```````~~~~`..`.``.``. 25 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 26 * . big-endian notation, just`. .. A bit more sophisticated controllers , 27 * . register the device with -be`. .with a pair of set/clear-bit registers , 28 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 29 * ``.`.``...``` ```.. output pins are also supported.` 30 * ^^ `````.`````````.,``~``~``~~`````` 31 * . ^^ 32 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 33 * .. The expectation is that in at least some cases . ,-~~~-, 34 * .this will be used with roll-your-own ASIC/FPGA .` \ / 35 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 36 * ..````````......``````````` \o_ 37 * | 38 * ^^ / \ 39 * 40 * ...`````~~`.....``.`..........``````.`.``.```........``. 41 * ` 8, 16, 32 and 64 bits registers are supported, and``. 42 * . the number of GPIOs is determined by the width of ~ 43 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 44 * `.......````.``` 45 */ 46 47 #include <linux/init.h> 48 #include <linux/err.h> 49 #include <linux/bug.h> 50 #include <linux/kernel.h> 51 #include <linux/module.h> 52 #include <linux/spinlock.h> 53 #include <linux/compiler.h> 54 #include <linux/types.h> 55 #include <linux/errno.h> 56 #include <linux/log2.h> 57 #include <linux/ioport.h> 58 #include <linux/io.h> 59 #include <linux/gpio/driver.h> 60 #include <linux/slab.h> 61 #include <linux/bitops.h> 62 #include <linux/platform_device.h> 63 #include <linux/mod_devicetable.h> 64 #include <linux/of.h> 65 #include <linux/of_device.h> 66 67 static void bgpio_write8(void __iomem *reg, unsigned long data) 68 { 69 writeb(data, reg); 70 } 71 72 static unsigned long bgpio_read8(void __iomem *reg) 73 { 74 return readb(reg); 75 } 76 77 static void bgpio_write16(void __iomem *reg, unsigned long data) 78 { 79 writew(data, reg); 80 } 81 82 static unsigned long bgpio_read16(void __iomem *reg) 83 { 84 return readw(reg); 85 } 86 87 static void bgpio_write32(void __iomem *reg, unsigned long data) 88 { 89 writel(data, reg); 90 } 91 92 static unsigned long bgpio_read32(void __iomem *reg) 93 { 94 return readl(reg); 95 } 96 97 #if BITS_PER_LONG >= 64 98 static void bgpio_write64(void __iomem *reg, unsigned long data) 99 { 100 writeq(data, reg); 101 } 102 103 static unsigned long bgpio_read64(void __iomem *reg) 104 { 105 return readq(reg); 106 } 107 #endif /* BITS_PER_LONG >= 64 */ 108 109 static void bgpio_write16be(void __iomem *reg, unsigned long data) 110 { 111 iowrite16be(data, reg); 112 } 113 114 static unsigned long bgpio_read16be(void __iomem *reg) 115 { 116 return ioread16be(reg); 117 } 118 119 static void bgpio_write32be(void __iomem *reg, unsigned long data) 120 { 121 iowrite32be(data, reg); 122 } 123 124 static unsigned long bgpio_read32be(void __iomem *reg) 125 { 126 return ioread32be(reg); 127 } 128 129 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 130 { 131 if (gc->be_bits) 132 return BIT(gc->bgpio_bits - 1 - line); 133 return BIT(line); 134 } 135 136 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 137 { 138 unsigned long pinmask = bgpio_line2mask(gc, gpio); 139 140 if (gc->bgpio_dir & pinmask) 141 return !!(gc->read_reg(gc->reg_set) & pinmask); 142 else 143 return !!(gc->read_reg(gc->reg_dat) & pinmask); 144 } 145 146 /* 147 * This assumes that the bits in the GPIO register are in native endianness. 148 * We only assign the function pointer if we have that. 149 */ 150 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 151 unsigned long *bits) 152 { 153 unsigned long get_mask = 0; 154 unsigned long set_mask = 0; 155 int bit = 0; 156 157 while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) { 158 if (gc->bgpio_dir & BIT(bit)) 159 set_mask |= BIT(bit); 160 else 161 get_mask |= BIT(bit); 162 } 163 164 if (set_mask) 165 *bits |= gc->read_reg(gc->reg_set) & set_mask; 166 if (get_mask) 167 *bits |= gc->read_reg(gc->reg_dat) & get_mask; 168 169 return 0; 170 } 171 172 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 173 { 174 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 175 } 176 177 /* 178 * This only works if the bits in the GPIO register are in native endianness. 179 * It is dirt simple and fast in this case. (Also the most common case.) 180 */ 181 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 182 unsigned long *bits) 183 { 184 185 *bits = gc->read_reg(gc->reg_dat) & *mask; 186 return 0; 187 } 188 189 /* 190 * With big endian mirrored bit order it becomes more tedious. 191 */ 192 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 193 unsigned long *bits) 194 { 195 unsigned long readmask = 0; 196 unsigned long val; 197 int bit; 198 199 /* Create a mirrored mask */ 200 bit = 0; 201 while ((bit = find_next_bit(mask, gc->ngpio, bit)) != gc->ngpio) 202 readmask |= bgpio_line2mask(gc, bit); 203 204 /* Read the register */ 205 val = gc->read_reg(gc->reg_dat) & readmask; 206 207 /* 208 * Mirror the result into the "bits" result, this will give line 0 209 * in bit 0 ... line 31 in bit 31 for a 32bit register. 210 */ 211 bit = 0; 212 while ((bit = find_next_bit(&val, gc->ngpio, bit)) != gc->ngpio) 213 *bits |= bgpio_line2mask(gc, bit); 214 215 return 0; 216 } 217 218 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 219 { 220 } 221 222 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 223 { 224 unsigned long mask = bgpio_line2mask(gc, gpio); 225 unsigned long flags; 226 227 spin_lock_irqsave(&gc->bgpio_lock, flags); 228 229 if (val) 230 gc->bgpio_data |= mask; 231 else 232 gc->bgpio_data &= ~mask; 233 234 gc->write_reg(gc->reg_dat, gc->bgpio_data); 235 236 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 237 } 238 239 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 240 int val) 241 { 242 unsigned long mask = bgpio_line2mask(gc, gpio); 243 244 if (val) 245 gc->write_reg(gc->reg_set, mask); 246 else 247 gc->write_reg(gc->reg_clr, mask); 248 } 249 250 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 251 { 252 unsigned long mask = bgpio_line2mask(gc, gpio); 253 unsigned long flags; 254 255 spin_lock_irqsave(&gc->bgpio_lock, flags); 256 257 if (val) 258 gc->bgpio_data |= mask; 259 else 260 gc->bgpio_data &= ~mask; 261 262 gc->write_reg(gc->reg_set, gc->bgpio_data); 263 264 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 265 } 266 267 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 268 unsigned long *mask, unsigned long *bits, 269 unsigned long *set_mask, 270 unsigned long *clear_mask) 271 { 272 int i; 273 274 *set_mask = 0; 275 *clear_mask = 0; 276 277 for (i = 0; i < gc->bgpio_bits; i++) { 278 if (*mask == 0) 279 break; 280 if (__test_and_clear_bit(i, mask)) { 281 if (test_bit(i, bits)) 282 *set_mask |= bgpio_line2mask(gc, i); 283 else 284 *clear_mask |= bgpio_line2mask(gc, i); 285 } 286 } 287 } 288 289 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 290 unsigned long *mask, 291 unsigned long *bits, 292 void __iomem *reg) 293 { 294 unsigned long flags; 295 unsigned long set_mask, clear_mask; 296 297 spin_lock_irqsave(&gc->bgpio_lock, flags); 298 299 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 300 301 gc->bgpio_data |= set_mask; 302 gc->bgpio_data &= ~clear_mask; 303 304 gc->write_reg(reg, gc->bgpio_data); 305 306 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 307 } 308 309 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 310 unsigned long *bits) 311 { 312 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 313 } 314 315 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 316 unsigned long *bits) 317 { 318 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 319 } 320 321 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, 322 unsigned long *mask, 323 unsigned long *bits) 324 { 325 unsigned long set_mask, clear_mask; 326 327 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 328 329 if (set_mask) 330 gc->write_reg(gc->reg_set, set_mask); 331 if (clear_mask) 332 gc->write_reg(gc->reg_clr, clear_mask); 333 } 334 335 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 336 { 337 return 0; 338 } 339 340 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 341 int val) 342 { 343 return -EINVAL; 344 } 345 346 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 347 int val) 348 { 349 gc->set(gc, gpio, val); 350 351 return 0; 352 } 353 354 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 355 { 356 unsigned long flags; 357 358 spin_lock_irqsave(&gc->bgpio_lock, flags); 359 360 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 361 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 362 363 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 364 365 return 0; 366 } 367 368 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 369 { 370 /* Return 0 if output, 1 of input */ 371 return !(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); 372 } 373 374 static int bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 375 { 376 unsigned long flags; 377 378 gc->set(gc, gpio, val); 379 380 spin_lock_irqsave(&gc->bgpio_lock, flags); 381 382 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 383 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 384 385 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 386 387 return 0; 388 } 389 390 static int bgpio_dir_in_inv(struct gpio_chip *gc, unsigned int gpio) 391 { 392 unsigned long flags; 393 394 spin_lock_irqsave(&gc->bgpio_lock, flags); 395 396 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 397 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 398 399 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 400 401 return 0; 402 } 403 404 static int bgpio_dir_out_inv(struct gpio_chip *gc, unsigned int gpio, int val) 405 { 406 unsigned long flags; 407 408 gc->set(gc, gpio, val); 409 410 spin_lock_irqsave(&gc->bgpio_lock, flags); 411 412 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 413 gc->write_reg(gc->reg_dir, gc->bgpio_dir); 414 415 spin_unlock_irqrestore(&gc->bgpio_lock, flags); 416 417 return 0; 418 } 419 420 static int bgpio_get_dir_inv(struct gpio_chip *gc, unsigned int gpio) 421 { 422 /* Return 0 if output, 1 if input */ 423 return !!(gc->read_reg(gc->reg_dir) & bgpio_line2mask(gc, gpio)); 424 } 425 426 static int bgpio_setup_accessors(struct device *dev, 427 struct gpio_chip *gc, 428 bool byte_be) 429 { 430 431 switch (gc->bgpio_bits) { 432 case 8: 433 gc->read_reg = bgpio_read8; 434 gc->write_reg = bgpio_write8; 435 break; 436 case 16: 437 if (byte_be) { 438 gc->read_reg = bgpio_read16be; 439 gc->write_reg = bgpio_write16be; 440 } else { 441 gc->read_reg = bgpio_read16; 442 gc->write_reg = bgpio_write16; 443 } 444 break; 445 case 32: 446 if (byte_be) { 447 gc->read_reg = bgpio_read32be; 448 gc->write_reg = bgpio_write32be; 449 } else { 450 gc->read_reg = bgpio_read32; 451 gc->write_reg = bgpio_write32; 452 } 453 break; 454 #if BITS_PER_LONG >= 64 455 case 64: 456 if (byte_be) { 457 dev_err(dev, 458 "64 bit big endian byte order unsupported\n"); 459 return -EINVAL; 460 } else { 461 gc->read_reg = bgpio_read64; 462 gc->write_reg = bgpio_write64; 463 } 464 break; 465 #endif /* BITS_PER_LONG >= 64 */ 466 default: 467 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 468 return -EINVAL; 469 } 470 471 return 0; 472 } 473 474 /* 475 * Create the device and allocate the resources. For setting GPIO's there are 476 * three supported configurations: 477 * 478 * - single input/output register resource (named "dat"). 479 * - set/clear pair (named "set" and "clr"). 480 * - single output register resource and single input resource ("set" and 481 * dat"). 482 * 483 * For the single output register, this drives a 1 by setting a bit and a zero 484 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 485 * in the set register and clears it by setting a bit in the clear register. 486 * The configuration is detected by which resources are present. 487 * 488 * For setting the GPIO direction, there are three supported configurations: 489 * 490 * - simple bidirection GPIO that requires no configuration. 491 * - an output direction register (named "dirout") where a 1 bit 492 * indicates the GPIO is an output. 493 * - an input direction register (named "dirin") where a 1 bit indicates 494 * the GPIO is an input. 495 */ 496 static int bgpio_setup_io(struct gpio_chip *gc, 497 void __iomem *dat, 498 void __iomem *set, 499 void __iomem *clr, 500 unsigned long flags) 501 { 502 503 gc->reg_dat = dat; 504 if (!gc->reg_dat) 505 return -EINVAL; 506 507 if (set && clr) { 508 gc->reg_set = set; 509 gc->reg_clr = clr; 510 gc->set = bgpio_set_with_clear; 511 gc->set_multiple = bgpio_set_multiple_with_clear; 512 } else if (set && !clr) { 513 gc->reg_set = set; 514 gc->set = bgpio_set_set; 515 gc->set_multiple = bgpio_set_multiple_set; 516 } else if (flags & BGPIOF_NO_OUTPUT) { 517 gc->set = bgpio_set_none; 518 gc->set_multiple = NULL; 519 } else { 520 gc->set = bgpio_set; 521 gc->set_multiple = bgpio_set_multiple; 522 } 523 524 if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 525 (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 526 gc->get = bgpio_get_set; 527 if (!gc->be_bits) 528 gc->get_multiple = bgpio_get_set_multiple; 529 /* 530 * We deliberately avoid assigning the ->get_multiple() call 531 * for big endian mirrored registers which are ALSO reflecting 532 * their value in the set register when used as output. It is 533 * simply too much complexity, let the GPIO core fall back to 534 * reading each line individually in that fringe case. 535 */ 536 } else { 537 gc->get = bgpio_get; 538 if (gc->be_bits) 539 gc->get_multiple = bgpio_get_multiple_be; 540 else 541 gc->get_multiple = bgpio_get_multiple; 542 } 543 544 return 0; 545 } 546 547 static int bgpio_setup_direction(struct gpio_chip *gc, 548 void __iomem *dirout, 549 void __iomem *dirin, 550 unsigned long flags) 551 { 552 if (dirout && dirin) { 553 return -EINVAL; 554 } else if (dirout) { 555 gc->reg_dir = dirout; 556 gc->direction_output = bgpio_dir_out; 557 gc->direction_input = bgpio_dir_in; 558 gc->get_direction = bgpio_get_dir; 559 } else if (dirin) { 560 gc->reg_dir = dirin; 561 gc->direction_output = bgpio_dir_out_inv; 562 gc->direction_input = bgpio_dir_in_inv; 563 gc->get_direction = bgpio_get_dir_inv; 564 } else { 565 if (flags & BGPIOF_NO_OUTPUT) 566 gc->direction_output = bgpio_dir_out_err; 567 else 568 gc->direction_output = bgpio_simple_dir_out; 569 gc->direction_input = bgpio_simple_dir_in; 570 } 571 572 return 0; 573 } 574 575 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 576 { 577 if (gpio_pin < chip->ngpio) 578 return 0; 579 580 return -EINVAL; 581 } 582 583 int bgpio_init(struct gpio_chip *gc, struct device *dev, 584 unsigned long sz, void __iomem *dat, void __iomem *set, 585 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 586 unsigned long flags) 587 { 588 int ret; 589 590 if (!is_power_of_2(sz)) 591 return -EINVAL; 592 593 gc->bgpio_bits = sz * 8; 594 if (gc->bgpio_bits > BITS_PER_LONG) 595 return -EINVAL; 596 597 spin_lock_init(&gc->bgpio_lock); 598 gc->parent = dev; 599 gc->label = dev_name(dev); 600 gc->base = -1; 601 gc->ngpio = gc->bgpio_bits; 602 gc->request = bgpio_request; 603 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 604 605 ret = bgpio_setup_io(gc, dat, set, clr, flags); 606 if (ret) 607 return ret; 608 609 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 610 if (ret) 611 return ret; 612 613 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 614 if (ret) 615 return ret; 616 617 gc->bgpio_data = gc->read_reg(gc->reg_dat); 618 if (gc->set == bgpio_set_set && 619 !(flags & BGPIOF_UNREADABLE_REG_SET)) 620 gc->bgpio_data = gc->read_reg(gc->reg_set); 621 if (gc->reg_dir && !(flags & BGPIOF_UNREADABLE_REG_DIR)) 622 gc->bgpio_dir = gc->read_reg(gc->reg_dir); 623 624 return ret; 625 } 626 EXPORT_SYMBOL_GPL(bgpio_init); 627 628 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 629 630 static void __iomem *bgpio_map(struct platform_device *pdev, 631 const char *name, 632 resource_size_t sane_sz) 633 { 634 struct resource *r; 635 resource_size_t sz; 636 637 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 638 if (!r) 639 return NULL; 640 641 sz = resource_size(r); 642 if (sz != sane_sz) 643 return IOMEM_ERR_PTR(-EINVAL); 644 645 return devm_ioremap_resource(&pdev->dev, r); 646 } 647 648 #ifdef CONFIG_OF 649 static const struct of_device_id bgpio_of_match[] = { 650 { .compatible = "brcm,bcm6345-gpio" }, 651 { .compatible = "wd,mbl-gpio" }, 652 { .compatible = "ni,169445-nand-gpio" }, 653 { } 654 }; 655 MODULE_DEVICE_TABLE(of, bgpio_of_match); 656 657 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 658 unsigned long *flags) 659 { 660 struct bgpio_pdata *pdata; 661 662 if (!of_match_device(bgpio_of_match, &pdev->dev)) 663 return NULL; 664 665 pdata = devm_kzalloc(&pdev->dev, sizeof(struct bgpio_pdata), 666 GFP_KERNEL); 667 if (!pdata) 668 return ERR_PTR(-ENOMEM); 669 670 pdata->base = -1; 671 672 if (of_device_is_big_endian(pdev->dev.of_node)) 673 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 674 675 if (of_property_read_bool(pdev->dev.of_node, "no-output")) 676 *flags |= BGPIOF_NO_OUTPUT; 677 678 return pdata; 679 } 680 #else 681 static struct bgpio_pdata *bgpio_parse_dt(struct platform_device *pdev, 682 unsigned long *flags) 683 { 684 return NULL; 685 } 686 #endif /* CONFIG_OF */ 687 688 static int bgpio_pdev_probe(struct platform_device *pdev) 689 { 690 struct device *dev = &pdev->dev; 691 struct resource *r; 692 void __iomem *dat; 693 void __iomem *set; 694 void __iomem *clr; 695 void __iomem *dirout; 696 void __iomem *dirin; 697 unsigned long sz; 698 unsigned long flags = 0; 699 int err; 700 struct gpio_chip *gc; 701 struct bgpio_pdata *pdata; 702 703 pdata = bgpio_parse_dt(pdev, &flags); 704 if (IS_ERR(pdata)) 705 return PTR_ERR(pdata); 706 707 if (!pdata) { 708 pdata = dev_get_platdata(dev); 709 flags = pdev->id_entry->driver_data; 710 } 711 712 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 713 if (!r) 714 return -EINVAL; 715 716 sz = resource_size(r); 717 718 dat = bgpio_map(pdev, "dat", sz); 719 if (IS_ERR(dat)) 720 return PTR_ERR(dat); 721 722 set = bgpio_map(pdev, "set", sz); 723 if (IS_ERR(set)) 724 return PTR_ERR(set); 725 726 clr = bgpio_map(pdev, "clr", sz); 727 if (IS_ERR(clr)) 728 return PTR_ERR(clr); 729 730 dirout = bgpio_map(pdev, "dirout", sz); 731 if (IS_ERR(dirout)) 732 return PTR_ERR(dirout); 733 734 dirin = bgpio_map(pdev, "dirin", sz); 735 if (IS_ERR(dirin)) 736 return PTR_ERR(dirin); 737 738 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 739 if (!gc) 740 return -ENOMEM; 741 742 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 743 if (err) 744 return err; 745 746 if (pdata) { 747 if (pdata->label) 748 gc->label = pdata->label; 749 gc->base = pdata->base; 750 if (pdata->ngpio > 0) 751 gc->ngpio = pdata->ngpio; 752 } 753 754 platform_set_drvdata(pdev, gc); 755 756 return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 757 } 758 759 static const struct platform_device_id bgpio_id_table[] = { 760 { 761 .name = "basic-mmio-gpio", 762 .driver_data = 0, 763 }, { 764 .name = "basic-mmio-gpio-be", 765 .driver_data = BGPIOF_BIG_ENDIAN, 766 }, 767 { } 768 }; 769 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 770 771 static struct platform_driver bgpio_driver = { 772 .driver = { 773 .name = "basic-mmio-gpio", 774 .of_match_table = of_match_ptr(bgpio_of_match), 775 }, 776 .id_table = bgpio_id_table, 777 .probe = bgpio_pdev_probe, 778 }; 779 780 module_platform_driver(bgpio_driver); 781 782 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 783 784 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 785 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 786 MODULE_LICENSE("GPL"); 787