1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/compiler.h> 45 #include <linux/err.h> 46 #include <linux/init.h> 47 #include <linux/io.h> 48 #include <linux/ioport.h> 49 #include <linux/log2.h> 50 #include <linux/mod_devicetable.h> 51 #include <linux/module.h> 52 #include <linux/pinctrl/consumer.h> 53 #include <linux/platform_device.h> 54 #include <linux/property.h> 55 #include <linux/slab.h> 56 #include <linux/spinlock.h> 57 #include <linux/types.h> 58 59 #include <linux/gpio/driver.h> 60 61 #include "gpiolib.h" 62 63 static void bgpio_write8(void __iomem *reg, unsigned long data) 64 { 65 writeb(data, reg); 66 } 67 68 static unsigned long bgpio_read8(void __iomem *reg) 69 { 70 return readb(reg); 71 } 72 73 static void bgpio_write16(void __iomem *reg, unsigned long data) 74 { 75 writew(data, reg); 76 } 77 78 static unsigned long bgpio_read16(void __iomem *reg) 79 { 80 return readw(reg); 81 } 82 83 static void bgpio_write32(void __iomem *reg, unsigned long data) 84 { 85 writel(data, reg); 86 } 87 88 static unsigned long bgpio_read32(void __iomem *reg) 89 { 90 return readl(reg); 91 } 92 93 #if BITS_PER_LONG >= 64 94 static void bgpio_write64(void __iomem *reg, unsigned long data) 95 { 96 writeq(data, reg); 97 } 98 99 static unsigned long bgpio_read64(void __iomem *reg) 100 { 101 return readq(reg); 102 } 103 #endif /* BITS_PER_LONG >= 64 */ 104 105 static void bgpio_write16be(void __iomem *reg, unsigned long data) 106 { 107 iowrite16be(data, reg); 108 } 109 110 static unsigned long bgpio_read16be(void __iomem *reg) 111 { 112 return ioread16be(reg); 113 } 114 115 static void bgpio_write32be(void __iomem *reg, unsigned long data) 116 { 117 iowrite32be(data, reg); 118 } 119 120 static unsigned long bgpio_read32be(void __iomem *reg) 121 { 122 return ioread32be(reg); 123 } 124 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 126 { 127 if (gc->be_bits) 128 return BIT(gc->bgpio_bits - 1 - line); 129 return BIT(line); 130 } 131 132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 133 { 134 unsigned long pinmask = bgpio_line2mask(gc, gpio); 135 bool dir = !!(gc->bgpio_dir & pinmask); 136 137 if (dir) 138 return !!(gc->read_reg(gc->reg_set) & pinmask); 139 else 140 return !!(gc->read_reg(gc->reg_dat) & pinmask); 141 } 142 143 /* 144 * This assumes that the bits in the GPIO register are in native endianness. 145 * We only assign the function pointer if we have that. 146 */ 147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 148 unsigned long *bits) 149 { 150 unsigned long get_mask = 0; 151 unsigned long set_mask = 0; 152 153 /* Make sure we first clear any bits that are zero when we read the register */ 154 *bits &= ~*mask; 155 156 set_mask = *mask & gc->bgpio_dir; 157 get_mask = *mask & ~gc->bgpio_dir; 158 159 if (set_mask) 160 *bits |= gc->read_reg(gc->reg_set) & set_mask; 161 if (get_mask) 162 *bits |= gc->read_reg(gc->reg_dat) & get_mask; 163 164 return 0; 165 } 166 167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 168 { 169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 170 } 171 172 /* 173 * This only works if the bits in the GPIO register are in native endianness. 174 */ 175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 176 unsigned long *bits) 177 { 178 /* Make sure we first clear any bits that are zero when we read the register */ 179 *bits &= ~*mask; 180 *bits |= gc->read_reg(gc->reg_dat) & *mask; 181 return 0; 182 } 183 184 /* 185 * With big endian mirrored bit order it becomes more tedious. 186 */ 187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 188 unsigned long *bits) 189 { 190 unsigned long readmask = 0; 191 unsigned long val; 192 int bit; 193 194 /* Make sure we first clear any bits that are zero when we read the register */ 195 *bits &= ~*mask; 196 197 /* Create a mirrored mask */ 198 for_each_set_bit(bit, mask, gc->ngpio) 199 readmask |= bgpio_line2mask(gc, bit); 200 201 /* Read the register */ 202 val = gc->read_reg(gc->reg_dat) & readmask; 203 204 /* 205 * Mirror the result into the "bits" result, this will give line 0 206 * in bit 0 ... line 31 in bit 31 for a 32bit register. 207 */ 208 for_each_set_bit(bit, &val, gc->ngpio) 209 *bits |= bgpio_line2mask(gc, bit); 210 211 return 0; 212 } 213 214 static int bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 215 { 216 return 0; 217 } 218 219 static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 220 { 221 unsigned long mask = bgpio_line2mask(gc, gpio); 222 unsigned long flags; 223 224 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 225 226 if (val) 227 gc->bgpio_data |= mask; 228 else 229 gc->bgpio_data &= ~mask; 230 231 gc->write_reg(gc->reg_dat, gc->bgpio_data); 232 233 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 234 235 return 0; 236 } 237 238 static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 239 int val) 240 { 241 unsigned long mask = bgpio_line2mask(gc, gpio); 242 243 if (val) 244 gc->write_reg(gc->reg_set, mask); 245 else 246 gc->write_reg(gc->reg_clr, mask); 247 248 return 0; 249 } 250 251 static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 252 { 253 unsigned long mask = bgpio_line2mask(gc, gpio); 254 unsigned long flags; 255 256 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 257 258 if (val) 259 gc->bgpio_data |= mask; 260 else 261 gc->bgpio_data &= ~mask; 262 263 gc->write_reg(gc->reg_set, gc->bgpio_data); 264 265 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 266 267 return 0; 268 } 269 270 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 271 unsigned long *mask, unsigned long *bits, 272 unsigned long *set_mask, 273 unsigned long *clear_mask) 274 { 275 int i; 276 277 *set_mask = 0; 278 *clear_mask = 0; 279 280 for_each_set_bit(i, mask, gc->bgpio_bits) { 281 if (test_bit(i, bits)) 282 *set_mask |= bgpio_line2mask(gc, i); 283 else 284 *clear_mask |= bgpio_line2mask(gc, i); 285 } 286 } 287 288 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 289 unsigned long *mask, 290 unsigned long *bits, 291 void __iomem *reg) 292 { 293 unsigned long flags; 294 unsigned long set_mask, clear_mask; 295 296 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 297 298 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 299 300 gc->bgpio_data |= set_mask; 301 gc->bgpio_data &= ~clear_mask; 302 303 gc->write_reg(reg, gc->bgpio_data); 304 305 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 306 } 307 308 static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 309 unsigned long *bits) 310 { 311 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 312 313 return 0; 314 } 315 316 static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 317 unsigned long *bits) 318 { 319 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 320 321 return 0; 322 } 323 324 static int bgpio_set_multiple_with_clear(struct gpio_chip *gc, 325 unsigned long *mask, 326 unsigned long *bits) 327 { 328 unsigned long set_mask, clear_mask; 329 330 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 331 332 if (set_mask) 333 gc->write_reg(gc->reg_set, set_mask); 334 if (clear_mask) 335 gc->write_reg(gc->reg_clr, clear_mask); 336 337 return 0; 338 } 339 340 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out) 341 { 342 if (!gc->bgpio_pinctrl) 343 return 0; 344 345 if (dir_out) 346 return pinctrl_gpio_direction_output(gc, gpio); 347 else 348 return pinctrl_gpio_direction_input(gc, gpio); 349 } 350 351 static int bgpio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) 352 { 353 return -EINVAL; 354 } 355 356 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 357 { 358 return bgpio_dir_return(gc, gpio, false); 359 } 360 361 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 362 int val) 363 { 364 return -EINVAL; 365 } 366 367 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 368 int val) 369 { 370 gc->set(gc, gpio, val); 371 372 return bgpio_dir_return(gc, gpio, true); 373 } 374 375 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 376 { 377 unsigned long flags; 378 379 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 380 381 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 382 383 if (gc->reg_dir_in) 384 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 385 if (gc->reg_dir_out) 386 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 387 388 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 389 390 return bgpio_dir_return(gc, gpio, false); 391 } 392 393 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 394 { 395 /* Return 0 if output, 1 if input */ 396 if (gc->bgpio_dir_unreadable) { 397 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) 398 return GPIO_LINE_DIRECTION_OUT; 399 return GPIO_LINE_DIRECTION_IN; 400 } 401 402 if (gc->reg_dir_out) { 403 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) 404 return GPIO_LINE_DIRECTION_OUT; 405 return GPIO_LINE_DIRECTION_IN; 406 } 407 408 if (gc->reg_dir_in) 409 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) 410 return GPIO_LINE_DIRECTION_OUT; 411 412 return GPIO_LINE_DIRECTION_IN; 413 } 414 415 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 416 { 417 unsigned long flags; 418 419 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 420 421 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 422 423 if (gc->reg_dir_in) 424 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 425 if (gc->reg_dir_out) 426 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 427 428 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 429 } 430 431 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 432 int val) 433 { 434 bgpio_dir_out(gc, gpio, val); 435 gc->set(gc, gpio, val); 436 return bgpio_dir_return(gc, gpio, true); 437 } 438 439 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 440 int val) 441 { 442 gc->set(gc, gpio, val); 443 bgpio_dir_out(gc, gpio, val); 444 return bgpio_dir_return(gc, gpio, true); 445 } 446 447 static int bgpio_setup_accessors(struct device *dev, 448 struct gpio_chip *gc, 449 bool byte_be) 450 { 451 452 switch (gc->bgpio_bits) { 453 case 8: 454 gc->read_reg = bgpio_read8; 455 gc->write_reg = bgpio_write8; 456 break; 457 case 16: 458 if (byte_be) { 459 gc->read_reg = bgpio_read16be; 460 gc->write_reg = bgpio_write16be; 461 } else { 462 gc->read_reg = bgpio_read16; 463 gc->write_reg = bgpio_write16; 464 } 465 break; 466 case 32: 467 if (byte_be) { 468 gc->read_reg = bgpio_read32be; 469 gc->write_reg = bgpio_write32be; 470 } else { 471 gc->read_reg = bgpio_read32; 472 gc->write_reg = bgpio_write32; 473 } 474 break; 475 #if BITS_PER_LONG >= 64 476 case 64: 477 if (byte_be) { 478 dev_err(dev, 479 "64 bit big endian byte order unsupported\n"); 480 return -EINVAL; 481 } else { 482 gc->read_reg = bgpio_read64; 483 gc->write_reg = bgpio_write64; 484 } 485 break; 486 #endif /* BITS_PER_LONG >= 64 */ 487 default: 488 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 489 return -EINVAL; 490 } 491 492 return 0; 493 } 494 495 /* 496 * Create the device and allocate the resources. For setting GPIO's there are 497 * three supported configurations: 498 * 499 * - single input/output register resource (named "dat"). 500 * - set/clear pair (named "set" and "clr"). 501 * - single output register resource and single input resource ("set" and 502 * dat"). 503 * 504 * For the single output register, this drives a 1 by setting a bit and a zero 505 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 506 * in the set register and clears it by setting a bit in the clear register. 507 * The configuration is detected by which resources are present. 508 * 509 * For setting the GPIO direction, there are three supported configurations: 510 * 511 * - simple bidirection GPIO that requires no configuration. 512 * - an output direction register (named "dirout") where a 1 bit 513 * indicates the GPIO is an output. 514 * - an input direction register (named "dirin") where a 1 bit indicates 515 * the GPIO is an input. 516 */ 517 static int bgpio_setup_io(struct gpio_chip *gc, 518 void __iomem *dat, 519 void __iomem *set, 520 void __iomem *clr, 521 unsigned long flags) 522 { 523 524 gc->reg_dat = dat; 525 if (!gc->reg_dat) 526 return -EINVAL; 527 528 if (set && clr) { 529 gc->reg_set = set; 530 gc->reg_clr = clr; 531 gc->set = bgpio_set_with_clear; 532 gc->set_multiple = bgpio_set_multiple_with_clear; 533 } else if (set && !clr) { 534 gc->reg_set = set; 535 gc->set = bgpio_set_set; 536 gc->set_multiple = bgpio_set_multiple_set; 537 } else if (flags & BGPIOF_NO_OUTPUT) { 538 gc->set = bgpio_set_none; 539 gc->set_multiple = NULL; 540 } else { 541 gc->set = bgpio_set; 542 gc->set_multiple = bgpio_set_multiple; 543 } 544 545 if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 546 (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 547 gc->get = bgpio_get_set; 548 if (!gc->be_bits) 549 gc->get_multiple = bgpio_get_set_multiple; 550 /* 551 * We deliberately avoid assigning the ->get_multiple() call 552 * for big endian mirrored registers which are ALSO reflecting 553 * their value in the set register when used as output. It is 554 * simply too much complexity, let the GPIO core fall back to 555 * reading each line individually in that fringe case. 556 */ 557 } else { 558 gc->get = bgpio_get; 559 if (gc->be_bits) 560 gc->get_multiple = bgpio_get_multiple_be; 561 else 562 gc->get_multiple = bgpio_get_multiple; 563 } 564 565 return 0; 566 } 567 568 static int bgpio_setup_direction(struct gpio_chip *gc, 569 void __iomem *dirout, 570 void __iomem *dirin, 571 unsigned long flags) 572 { 573 if (dirout || dirin) { 574 gc->reg_dir_out = dirout; 575 gc->reg_dir_in = dirin; 576 if (flags & BGPIOF_NO_SET_ON_INPUT) 577 gc->direction_output = bgpio_dir_out_dir_first; 578 else 579 gc->direction_output = bgpio_dir_out_val_first; 580 gc->direction_input = bgpio_dir_in; 581 gc->get_direction = bgpio_get_dir; 582 } else { 583 if (flags & BGPIOF_NO_OUTPUT) 584 gc->direction_output = bgpio_dir_out_err; 585 else 586 gc->direction_output = bgpio_simple_dir_out; 587 588 if (flags & BGPIOF_NO_INPUT) 589 gc->direction_input = bgpio_dir_in_err; 590 else 591 gc->direction_input = bgpio_simple_dir_in; 592 } 593 594 return 0; 595 } 596 597 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 598 { 599 if (gpio_pin >= chip->ngpio) 600 return -EINVAL; 601 602 if (chip->bgpio_pinctrl) 603 return gpiochip_generic_request(chip, gpio_pin); 604 605 return 0; 606 } 607 608 /** 609 * bgpio_init() - Initialize generic GPIO accessor functions 610 * @gc: the GPIO chip to set up 611 * @dev: the parent device of the new GPIO chip (compulsory) 612 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 613 * @dat: MMIO address for the register to READ the value of the GPIO lines, it 614 * is expected that a 1 in the corresponding bit in this register means the 615 * line is asserted 616 * @set: MMIO address for the register to SET the value of the GPIO lines, it is 617 * expected that we write the line with 1 in this register to drive the GPIO line 618 * high. 619 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is 620 * expected that we write the line with 1 in this register to drive the GPIO line 621 * low. It is allowed to leave this address as NULL, in that case the SET register 622 * will be assumed to also clear the GPIO lines, by actively writing the line 623 * with 0. 624 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed 625 * that setting a line to 1 in this register will turn that line into an 626 * output line. Conversely, setting the line to 0 will turn that line into 627 * an input. 628 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed 629 * that setting a line to 1 in this register will turn that line into an 630 * input line. Conversely, setting the line to 0 will turn that line into 631 * an output. 632 * @flags: Different flags that will affect the behaviour of the device, such as 633 * endianness etc. 634 */ 635 int bgpio_init(struct gpio_chip *gc, struct device *dev, 636 unsigned long sz, void __iomem *dat, void __iomem *set, 637 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 638 unsigned long flags) 639 { 640 int ret; 641 642 if (!is_power_of_2(sz)) 643 return -EINVAL; 644 645 gc->bgpio_bits = sz * 8; 646 if (gc->bgpio_bits > BITS_PER_LONG) 647 return -EINVAL; 648 649 raw_spin_lock_init(&gc->bgpio_lock); 650 gc->parent = dev; 651 gc->label = dev_name(dev); 652 gc->base = -1; 653 gc->request = bgpio_request; 654 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 655 656 ret = gpiochip_get_ngpios(gc, dev); 657 if (ret) 658 gc->ngpio = gc->bgpio_bits; 659 660 ret = bgpio_setup_io(gc, dat, set, clr, flags); 661 if (ret) 662 return ret; 663 664 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 665 if (ret) 666 return ret; 667 668 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 669 if (ret) 670 return ret; 671 672 if (flags & BGPIOF_PINCTRL_BACKEND) { 673 gc->bgpio_pinctrl = true; 674 /* Currently this callback is only used for pincontrol */ 675 gc->free = gpiochip_generic_free; 676 } 677 678 gc->bgpio_data = gc->read_reg(gc->reg_dat); 679 if (gc->set == bgpio_set_set && 680 !(flags & BGPIOF_UNREADABLE_REG_SET)) 681 gc->bgpio_data = gc->read_reg(gc->reg_set); 682 683 if (flags & BGPIOF_UNREADABLE_REG_DIR) 684 gc->bgpio_dir_unreadable = true; 685 686 /* 687 * Inspect hardware to find initial direction setting. 688 */ 689 if ((gc->reg_dir_out || gc->reg_dir_in) && 690 !(flags & BGPIOF_UNREADABLE_REG_DIR)) { 691 if (gc->reg_dir_out) 692 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); 693 else if (gc->reg_dir_in) 694 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); 695 /* 696 * If we have two direction registers, synchronise 697 * input setting to output setting, the library 698 * can not handle a line being input and output at 699 * the same time. 700 */ 701 if (gc->reg_dir_out && gc->reg_dir_in) 702 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 703 } 704 705 return ret; 706 } 707 EXPORT_SYMBOL_GPL(bgpio_init); 708 709 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 710 711 static void __iomem *bgpio_map(struct platform_device *pdev, 712 const char *name, 713 resource_size_t sane_sz) 714 { 715 struct resource *r; 716 resource_size_t sz; 717 718 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 719 if (!r) 720 return NULL; 721 722 sz = resource_size(r); 723 if (sz != sane_sz) 724 return IOMEM_ERR_PTR(-EINVAL); 725 726 return devm_ioremap_resource(&pdev->dev, r); 727 } 728 729 static const struct of_device_id bgpio_of_match[] = { 730 { .compatible = "brcm,bcm6345-gpio" }, 731 { .compatible = "wd,mbl-gpio" }, 732 { .compatible = "ni,169445-nand-gpio" }, 733 { } 734 }; 735 MODULE_DEVICE_TABLE(of, bgpio_of_match); 736 737 static int bgpio_pdev_probe(struct platform_device *pdev) 738 { 739 struct device *dev = &pdev->dev; 740 struct resource *r; 741 void __iomem *dat; 742 void __iomem *set; 743 void __iomem *clr; 744 void __iomem *dirout; 745 void __iomem *dirin; 746 unsigned long sz; 747 unsigned long flags = 0; 748 unsigned int base; 749 int err; 750 struct gpio_chip *gc; 751 const char *label; 752 753 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 754 if (!r) 755 return -EINVAL; 756 757 sz = resource_size(r); 758 759 dat = bgpio_map(pdev, "dat", sz); 760 if (IS_ERR(dat)) 761 return PTR_ERR(dat); 762 763 set = bgpio_map(pdev, "set", sz); 764 if (IS_ERR(set)) 765 return PTR_ERR(set); 766 767 clr = bgpio_map(pdev, "clr", sz); 768 if (IS_ERR(clr)) 769 return PTR_ERR(clr); 770 771 dirout = bgpio_map(pdev, "dirout", sz); 772 if (IS_ERR(dirout)) 773 return PTR_ERR(dirout); 774 775 dirin = bgpio_map(pdev, "dirin", sz); 776 if (IS_ERR(dirin)) 777 return PTR_ERR(dirin); 778 779 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 780 if (!gc) 781 return -ENOMEM; 782 783 if (device_is_big_endian(dev)) 784 flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 785 786 if (device_property_read_bool(dev, "no-output")) 787 flags |= BGPIOF_NO_OUTPUT; 788 789 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 790 if (err) 791 return err; 792 793 err = device_property_read_string(dev, "label", &label); 794 if (!err) 795 gc->label = label; 796 797 /* 798 * This property *must not* be used in device-tree sources, it's only 799 * meant to be passed to the driver from board files and MFD core. 800 */ 801 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 802 if (!err && base <= INT_MAX) 803 gc->base = base; 804 805 platform_set_drvdata(pdev, gc); 806 807 return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 808 } 809 810 static const struct platform_device_id bgpio_id_table[] = { 811 { 812 .name = "basic-mmio-gpio", 813 .driver_data = 0, 814 }, 815 { } 816 }; 817 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 818 819 static struct platform_driver bgpio_driver = { 820 .driver = { 821 .name = "basic-mmio-gpio", 822 .of_match_table = bgpio_of_match, 823 }, 824 .id_table = bgpio_id_table, 825 .probe = bgpio_pdev_probe, 826 }; 827 828 module_platform_driver(bgpio_driver); 829 830 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 831 832 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 833 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 834 MODULE_LICENSE("GPL"); 835