1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/compiler.h> 45 #include <linux/err.h> 46 #include <linux/init.h> 47 #include <linux/io.h> 48 #include <linux/ioport.h> 49 #include <linux/log2.h> 50 #include <linux/mod_devicetable.h> 51 #include <linux/module.h> 52 #include <linux/pinctrl/consumer.h> 53 #include <linux/platform_device.h> 54 #include <linux/property.h> 55 #include <linux/slab.h> 56 #include <linux/spinlock.h> 57 #include <linux/types.h> 58 59 #include <linux/gpio/driver.h> 60 61 #include "gpiolib.h" 62 63 static void bgpio_write8(void __iomem *reg, unsigned long data) 64 { 65 writeb(data, reg); 66 } 67 68 static unsigned long bgpio_read8(void __iomem *reg) 69 { 70 return readb(reg); 71 } 72 73 static void bgpio_write16(void __iomem *reg, unsigned long data) 74 { 75 writew(data, reg); 76 } 77 78 static unsigned long bgpio_read16(void __iomem *reg) 79 { 80 return readw(reg); 81 } 82 83 static void bgpio_write32(void __iomem *reg, unsigned long data) 84 { 85 writel(data, reg); 86 } 87 88 static unsigned long bgpio_read32(void __iomem *reg) 89 { 90 return readl(reg); 91 } 92 93 #if BITS_PER_LONG >= 64 94 static void bgpio_write64(void __iomem *reg, unsigned long data) 95 { 96 writeq(data, reg); 97 } 98 99 static unsigned long bgpio_read64(void __iomem *reg) 100 { 101 return readq(reg); 102 } 103 #endif /* BITS_PER_LONG >= 64 */ 104 105 static void bgpio_write16be(void __iomem *reg, unsigned long data) 106 { 107 iowrite16be(data, reg); 108 } 109 110 static unsigned long bgpio_read16be(void __iomem *reg) 111 { 112 return ioread16be(reg); 113 } 114 115 static void bgpio_write32be(void __iomem *reg, unsigned long data) 116 { 117 iowrite32be(data, reg); 118 } 119 120 static unsigned long bgpio_read32be(void __iomem *reg) 121 { 122 return ioread32be(reg); 123 } 124 125 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 126 { 127 if (gc->be_bits) 128 return BIT(gc->bgpio_bits - 1 - line); 129 return BIT(line); 130 } 131 132 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 133 { 134 unsigned long pinmask = bgpio_line2mask(gc, gpio); 135 bool dir = !!(gc->bgpio_dir & pinmask); 136 137 if (dir) 138 return !!(gc->read_reg(gc->reg_set) & pinmask); 139 else 140 return !!(gc->read_reg(gc->reg_dat) & pinmask); 141 } 142 143 /* 144 * This assumes that the bits in the GPIO register are in native endianness. 145 * We only assign the function pointer if we have that. 146 */ 147 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 148 unsigned long *bits) 149 { 150 unsigned long get_mask = 0; 151 unsigned long set_mask = 0; 152 153 /* Make sure we first clear any bits that are zero when we read the register */ 154 *bits &= ~*mask; 155 156 set_mask = *mask & gc->bgpio_dir; 157 get_mask = *mask & ~gc->bgpio_dir; 158 159 if (set_mask) 160 *bits |= gc->read_reg(gc->reg_set) & set_mask; 161 if (get_mask) 162 *bits |= gc->read_reg(gc->reg_dat) & get_mask; 163 164 return 0; 165 } 166 167 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 168 { 169 return !!(gc->read_reg(gc->reg_dat) & bgpio_line2mask(gc, gpio)); 170 } 171 172 /* 173 * This only works if the bits in the GPIO register are in native endianness. 174 */ 175 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 176 unsigned long *bits) 177 { 178 /* Make sure we first clear any bits that are zero when we read the register */ 179 *bits &= ~*mask; 180 *bits |= gc->read_reg(gc->reg_dat) & *mask; 181 return 0; 182 } 183 184 /* 185 * With big endian mirrored bit order it becomes more tedious. 186 */ 187 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 188 unsigned long *bits) 189 { 190 unsigned long readmask = 0; 191 unsigned long val; 192 int bit; 193 194 /* Make sure we first clear any bits that are zero when we read the register */ 195 *bits &= ~*mask; 196 197 /* Create a mirrored mask */ 198 for_each_set_bit(bit, mask, gc->ngpio) 199 readmask |= bgpio_line2mask(gc, bit); 200 201 /* Read the register */ 202 val = gc->read_reg(gc->reg_dat) & readmask; 203 204 /* 205 * Mirror the result into the "bits" result, this will give line 0 206 * in bit 0 ... line 31 in bit 31 for a 32bit register. 207 */ 208 for_each_set_bit(bit, &val, gc->ngpio) 209 *bits |= bgpio_line2mask(gc, bit); 210 211 return 0; 212 } 213 214 static void bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 215 { 216 } 217 218 static void bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 219 { 220 unsigned long mask = bgpio_line2mask(gc, gpio); 221 unsigned long flags; 222 223 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 224 225 if (val) 226 gc->bgpio_data |= mask; 227 else 228 gc->bgpio_data &= ~mask; 229 230 gc->write_reg(gc->reg_dat, gc->bgpio_data); 231 232 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 233 } 234 235 static void bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 236 int val) 237 { 238 unsigned long mask = bgpio_line2mask(gc, gpio); 239 240 if (val) 241 gc->write_reg(gc->reg_set, mask); 242 else 243 gc->write_reg(gc->reg_clr, mask); 244 } 245 246 static void bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 247 { 248 unsigned long mask = bgpio_line2mask(gc, gpio); 249 unsigned long flags; 250 251 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 252 253 if (val) 254 gc->bgpio_data |= mask; 255 else 256 gc->bgpio_data &= ~mask; 257 258 gc->write_reg(gc->reg_set, gc->bgpio_data); 259 260 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 261 } 262 263 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 264 unsigned long *mask, unsigned long *bits, 265 unsigned long *set_mask, 266 unsigned long *clear_mask) 267 { 268 int i; 269 270 *set_mask = 0; 271 *clear_mask = 0; 272 273 for_each_set_bit(i, mask, gc->bgpio_bits) { 274 if (test_bit(i, bits)) 275 *set_mask |= bgpio_line2mask(gc, i); 276 else 277 *clear_mask |= bgpio_line2mask(gc, i); 278 } 279 } 280 281 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 282 unsigned long *mask, 283 unsigned long *bits, 284 void __iomem *reg) 285 { 286 unsigned long flags; 287 unsigned long set_mask, clear_mask; 288 289 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 290 291 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 292 293 gc->bgpio_data |= set_mask; 294 gc->bgpio_data &= ~clear_mask; 295 296 gc->write_reg(reg, gc->bgpio_data); 297 298 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 299 } 300 301 static void bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 302 unsigned long *bits) 303 { 304 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_dat); 305 } 306 307 static void bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 308 unsigned long *bits) 309 { 310 bgpio_set_multiple_single_reg(gc, mask, bits, gc->reg_set); 311 } 312 313 static void bgpio_set_multiple_with_clear(struct gpio_chip *gc, 314 unsigned long *mask, 315 unsigned long *bits) 316 { 317 unsigned long set_mask, clear_mask; 318 319 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 320 321 if (set_mask) 322 gc->write_reg(gc->reg_set, set_mask); 323 if (clear_mask) 324 gc->write_reg(gc->reg_clr, clear_mask); 325 } 326 327 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out) 328 { 329 if (!gc->bgpio_pinctrl) 330 return 0; 331 332 if (dir_out) 333 return pinctrl_gpio_direction_output(gc, gpio); 334 else 335 return pinctrl_gpio_direction_input(gc, gpio); 336 } 337 338 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 339 { 340 return bgpio_dir_return(gc, gpio, false); 341 } 342 343 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 344 int val) 345 { 346 return -EINVAL; 347 } 348 349 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 350 int val) 351 { 352 gc->set(gc, gpio, val); 353 354 return bgpio_dir_return(gc, gpio, true); 355 } 356 357 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 358 { 359 unsigned long flags; 360 361 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 362 363 gc->bgpio_dir &= ~bgpio_line2mask(gc, gpio); 364 365 if (gc->reg_dir_in) 366 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 367 if (gc->reg_dir_out) 368 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 369 370 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 371 372 return bgpio_dir_return(gc, gpio, false); 373 } 374 375 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 376 { 377 /* Return 0 if output, 1 if input */ 378 if (gc->bgpio_dir_unreadable) { 379 if (gc->bgpio_dir & bgpio_line2mask(gc, gpio)) 380 return GPIO_LINE_DIRECTION_OUT; 381 return GPIO_LINE_DIRECTION_IN; 382 } 383 384 if (gc->reg_dir_out) { 385 if (gc->read_reg(gc->reg_dir_out) & bgpio_line2mask(gc, gpio)) 386 return GPIO_LINE_DIRECTION_OUT; 387 return GPIO_LINE_DIRECTION_IN; 388 } 389 390 if (gc->reg_dir_in) 391 if (!(gc->read_reg(gc->reg_dir_in) & bgpio_line2mask(gc, gpio))) 392 return GPIO_LINE_DIRECTION_OUT; 393 394 return GPIO_LINE_DIRECTION_IN; 395 } 396 397 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 398 { 399 unsigned long flags; 400 401 raw_spin_lock_irqsave(&gc->bgpio_lock, flags); 402 403 gc->bgpio_dir |= bgpio_line2mask(gc, gpio); 404 405 if (gc->reg_dir_in) 406 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 407 if (gc->reg_dir_out) 408 gc->write_reg(gc->reg_dir_out, gc->bgpio_dir); 409 410 raw_spin_unlock_irqrestore(&gc->bgpio_lock, flags); 411 } 412 413 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 414 int val) 415 { 416 bgpio_dir_out(gc, gpio, val); 417 gc->set(gc, gpio, val); 418 return bgpio_dir_return(gc, gpio, true); 419 } 420 421 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 422 int val) 423 { 424 gc->set(gc, gpio, val); 425 bgpio_dir_out(gc, gpio, val); 426 return bgpio_dir_return(gc, gpio, true); 427 } 428 429 static int bgpio_setup_accessors(struct device *dev, 430 struct gpio_chip *gc, 431 bool byte_be) 432 { 433 434 switch (gc->bgpio_bits) { 435 case 8: 436 gc->read_reg = bgpio_read8; 437 gc->write_reg = bgpio_write8; 438 break; 439 case 16: 440 if (byte_be) { 441 gc->read_reg = bgpio_read16be; 442 gc->write_reg = bgpio_write16be; 443 } else { 444 gc->read_reg = bgpio_read16; 445 gc->write_reg = bgpio_write16; 446 } 447 break; 448 case 32: 449 if (byte_be) { 450 gc->read_reg = bgpio_read32be; 451 gc->write_reg = bgpio_write32be; 452 } else { 453 gc->read_reg = bgpio_read32; 454 gc->write_reg = bgpio_write32; 455 } 456 break; 457 #if BITS_PER_LONG >= 64 458 case 64: 459 if (byte_be) { 460 dev_err(dev, 461 "64 bit big endian byte order unsupported\n"); 462 return -EINVAL; 463 } else { 464 gc->read_reg = bgpio_read64; 465 gc->write_reg = bgpio_write64; 466 } 467 break; 468 #endif /* BITS_PER_LONG >= 64 */ 469 default: 470 dev_err(dev, "unsupported data width %u bits\n", gc->bgpio_bits); 471 return -EINVAL; 472 } 473 474 return 0; 475 } 476 477 /* 478 * Create the device and allocate the resources. For setting GPIO's there are 479 * three supported configurations: 480 * 481 * - single input/output register resource (named "dat"). 482 * - set/clear pair (named "set" and "clr"). 483 * - single output register resource and single input resource ("set" and 484 * dat"). 485 * 486 * For the single output register, this drives a 1 by setting a bit and a zero 487 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 488 * in the set register and clears it by setting a bit in the clear register. 489 * The configuration is detected by which resources are present. 490 * 491 * For setting the GPIO direction, there are three supported configurations: 492 * 493 * - simple bidirection GPIO that requires no configuration. 494 * - an output direction register (named "dirout") where a 1 bit 495 * indicates the GPIO is an output. 496 * - an input direction register (named "dirin") where a 1 bit indicates 497 * the GPIO is an input. 498 */ 499 static int bgpio_setup_io(struct gpio_chip *gc, 500 void __iomem *dat, 501 void __iomem *set, 502 void __iomem *clr, 503 unsigned long flags) 504 { 505 506 gc->reg_dat = dat; 507 if (!gc->reg_dat) 508 return -EINVAL; 509 510 if (set && clr) { 511 gc->reg_set = set; 512 gc->reg_clr = clr; 513 gc->set = bgpio_set_with_clear; 514 gc->set_multiple = bgpio_set_multiple_with_clear; 515 } else if (set && !clr) { 516 gc->reg_set = set; 517 gc->set = bgpio_set_set; 518 gc->set_multiple = bgpio_set_multiple_set; 519 } else if (flags & BGPIOF_NO_OUTPUT) { 520 gc->set = bgpio_set_none; 521 gc->set_multiple = NULL; 522 } else { 523 gc->set = bgpio_set; 524 gc->set_multiple = bgpio_set_multiple; 525 } 526 527 if (!(flags & BGPIOF_UNREADABLE_REG_SET) && 528 (flags & BGPIOF_READ_OUTPUT_REG_SET)) { 529 gc->get = bgpio_get_set; 530 if (!gc->be_bits) 531 gc->get_multiple = bgpio_get_set_multiple; 532 /* 533 * We deliberately avoid assigning the ->get_multiple() call 534 * for big endian mirrored registers which are ALSO reflecting 535 * their value in the set register when used as output. It is 536 * simply too much complexity, let the GPIO core fall back to 537 * reading each line individually in that fringe case. 538 */ 539 } else { 540 gc->get = bgpio_get; 541 if (gc->be_bits) 542 gc->get_multiple = bgpio_get_multiple_be; 543 else 544 gc->get_multiple = bgpio_get_multiple; 545 } 546 547 return 0; 548 } 549 550 static int bgpio_setup_direction(struct gpio_chip *gc, 551 void __iomem *dirout, 552 void __iomem *dirin, 553 unsigned long flags) 554 { 555 if (dirout || dirin) { 556 gc->reg_dir_out = dirout; 557 gc->reg_dir_in = dirin; 558 if (flags & BGPIOF_NO_SET_ON_INPUT) 559 gc->direction_output = bgpio_dir_out_dir_first; 560 else 561 gc->direction_output = bgpio_dir_out_val_first; 562 gc->direction_input = bgpio_dir_in; 563 gc->get_direction = bgpio_get_dir; 564 } else { 565 if (flags & BGPIOF_NO_OUTPUT) 566 gc->direction_output = bgpio_dir_out_err; 567 else 568 gc->direction_output = bgpio_simple_dir_out; 569 gc->direction_input = bgpio_simple_dir_in; 570 } 571 572 return 0; 573 } 574 575 static int bgpio_request(struct gpio_chip *chip, unsigned gpio_pin) 576 { 577 if (gpio_pin >= chip->ngpio) 578 return -EINVAL; 579 580 if (chip->bgpio_pinctrl) 581 return gpiochip_generic_request(chip, gpio_pin); 582 583 return 0; 584 } 585 586 /** 587 * bgpio_init() - Initialize generic GPIO accessor functions 588 * @gc: the GPIO chip to set up 589 * @dev: the parent device of the new GPIO chip (compulsory) 590 * @sz: the size (width) of the MMIO registers in bytes, typically 1, 2 or 4 591 * @dat: MMIO address for the register to READ the value of the GPIO lines, it 592 * is expected that a 1 in the corresponding bit in this register means the 593 * line is asserted 594 * @set: MMIO address for the register to SET the value of the GPIO lines, it is 595 * expected that we write the line with 1 in this register to drive the GPIO line 596 * high. 597 * @clr: MMIO address for the register to CLEAR the value of the GPIO lines, it is 598 * expected that we write the line with 1 in this register to drive the GPIO line 599 * low. It is allowed to leave this address as NULL, in that case the SET register 600 * will be assumed to also clear the GPIO lines, by actively writing the line 601 * with 0. 602 * @dirout: MMIO address for the register to set the line as OUTPUT. It is assumed 603 * that setting a line to 1 in this register will turn that line into an 604 * output line. Conversely, setting the line to 0 will turn that line into 605 * an input. 606 * @dirin: MMIO address for the register to set this line as INPUT. It is assumed 607 * that setting a line to 1 in this register will turn that line into an 608 * input line. Conversely, setting the line to 0 will turn that line into 609 * an output. 610 * @flags: Different flags that will affect the behaviour of the device, such as 611 * endianness etc. 612 */ 613 int bgpio_init(struct gpio_chip *gc, struct device *dev, 614 unsigned long sz, void __iomem *dat, void __iomem *set, 615 void __iomem *clr, void __iomem *dirout, void __iomem *dirin, 616 unsigned long flags) 617 { 618 int ret; 619 620 if (!is_power_of_2(sz)) 621 return -EINVAL; 622 623 gc->bgpio_bits = sz * 8; 624 if (gc->bgpio_bits > BITS_PER_LONG) 625 return -EINVAL; 626 627 raw_spin_lock_init(&gc->bgpio_lock); 628 gc->parent = dev; 629 gc->label = dev_name(dev); 630 gc->base = -1; 631 gc->request = bgpio_request; 632 gc->be_bits = !!(flags & BGPIOF_BIG_ENDIAN); 633 634 ret = gpiochip_get_ngpios(gc, dev); 635 if (ret) 636 gc->ngpio = gc->bgpio_bits; 637 638 ret = bgpio_setup_io(gc, dat, set, clr, flags); 639 if (ret) 640 return ret; 641 642 ret = bgpio_setup_accessors(dev, gc, flags & BGPIOF_BIG_ENDIAN_BYTE_ORDER); 643 if (ret) 644 return ret; 645 646 ret = bgpio_setup_direction(gc, dirout, dirin, flags); 647 if (ret) 648 return ret; 649 650 if (flags & BGPIOF_PINCTRL_BACKEND) { 651 gc->bgpio_pinctrl = true; 652 /* Currently this callback is only used for pincontrol */ 653 gc->free = gpiochip_generic_free; 654 } 655 656 gc->bgpio_data = gc->read_reg(gc->reg_dat); 657 if (gc->set == bgpio_set_set && 658 !(flags & BGPIOF_UNREADABLE_REG_SET)) 659 gc->bgpio_data = gc->read_reg(gc->reg_set); 660 661 if (flags & BGPIOF_UNREADABLE_REG_DIR) 662 gc->bgpio_dir_unreadable = true; 663 664 /* 665 * Inspect hardware to find initial direction setting. 666 */ 667 if ((gc->reg_dir_out || gc->reg_dir_in) && 668 !(flags & BGPIOF_UNREADABLE_REG_DIR)) { 669 if (gc->reg_dir_out) 670 gc->bgpio_dir = gc->read_reg(gc->reg_dir_out); 671 else if (gc->reg_dir_in) 672 gc->bgpio_dir = ~gc->read_reg(gc->reg_dir_in); 673 /* 674 * If we have two direction registers, synchronise 675 * input setting to output setting, the library 676 * can not handle a line being input and output at 677 * the same time. 678 */ 679 if (gc->reg_dir_out && gc->reg_dir_in) 680 gc->write_reg(gc->reg_dir_in, ~gc->bgpio_dir); 681 } 682 683 return ret; 684 } 685 EXPORT_SYMBOL_GPL(bgpio_init); 686 687 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 688 689 static void __iomem *bgpio_map(struct platform_device *pdev, 690 const char *name, 691 resource_size_t sane_sz) 692 { 693 struct resource *r; 694 resource_size_t sz; 695 696 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 697 if (!r) 698 return NULL; 699 700 sz = resource_size(r); 701 if (sz != sane_sz) 702 return IOMEM_ERR_PTR(-EINVAL); 703 704 return devm_ioremap_resource(&pdev->dev, r); 705 } 706 707 static const struct of_device_id bgpio_of_match[] = { 708 { .compatible = "brcm,bcm6345-gpio" }, 709 { .compatible = "wd,mbl-gpio" }, 710 { .compatible = "ni,169445-nand-gpio" }, 711 { } 712 }; 713 MODULE_DEVICE_TABLE(of, bgpio_of_match); 714 715 static struct bgpio_pdata *bgpio_parse_fw(struct device *dev, unsigned long *flags) 716 { 717 struct bgpio_pdata *pdata; 718 719 if (!dev_fwnode(dev)) 720 return NULL; 721 722 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 723 if (!pdata) 724 return ERR_PTR(-ENOMEM); 725 726 pdata->base = -1; 727 728 if (device_is_big_endian(dev)) 729 *flags |= BGPIOF_BIG_ENDIAN_BYTE_ORDER; 730 731 if (device_property_read_bool(dev, "no-output")) 732 *flags |= BGPIOF_NO_OUTPUT; 733 734 return pdata; 735 } 736 737 static int bgpio_pdev_probe(struct platform_device *pdev) 738 { 739 struct device *dev = &pdev->dev; 740 struct resource *r; 741 void __iomem *dat; 742 void __iomem *set; 743 void __iomem *clr; 744 void __iomem *dirout; 745 void __iomem *dirin; 746 unsigned long sz; 747 unsigned long flags = 0; 748 int err; 749 struct gpio_chip *gc; 750 struct bgpio_pdata *pdata; 751 752 pdata = bgpio_parse_fw(dev, &flags); 753 if (IS_ERR(pdata)) 754 return PTR_ERR(pdata); 755 756 if (!pdata) { 757 pdata = dev_get_platdata(dev); 758 flags = pdev->id_entry->driver_data; 759 } 760 761 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 762 if (!r) 763 return -EINVAL; 764 765 sz = resource_size(r); 766 767 dat = bgpio_map(pdev, "dat", sz); 768 if (IS_ERR(dat)) 769 return PTR_ERR(dat); 770 771 set = bgpio_map(pdev, "set", sz); 772 if (IS_ERR(set)) 773 return PTR_ERR(set); 774 775 clr = bgpio_map(pdev, "clr", sz); 776 if (IS_ERR(clr)) 777 return PTR_ERR(clr); 778 779 dirout = bgpio_map(pdev, "dirout", sz); 780 if (IS_ERR(dirout)) 781 return PTR_ERR(dirout); 782 783 dirin = bgpio_map(pdev, "dirin", sz); 784 if (IS_ERR(dirin)) 785 return PTR_ERR(dirin); 786 787 gc = devm_kzalloc(&pdev->dev, sizeof(*gc), GFP_KERNEL); 788 if (!gc) 789 return -ENOMEM; 790 791 err = bgpio_init(gc, dev, sz, dat, set, clr, dirout, dirin, flags); 792 if (err) 793 return err; 794 795 if (pdata) { 796 if (pdata->label) 797 gc->label = pdata->label; 798 gc->base = pdata->base; 799 if (pdata->ngpio > 0) 800 gc->ngpio = pdata->ngpio; 801 } 802 803 platform_set_drvdata(pdev, gc); 804 805 return devm_gpiochip_add_data(&pdev->dev, gc, NULL); 806 } 807 808 static const struct platform_device_id bgpio_id_table[] = { 809 { 810 .name = "basic-mmio-gpio", 811 .driver_data = 0, 812 }, { 813 .name = "basic-mmio-gpio-be", 814 .driver_data = BGPIOF_BIG_ENDIAN, 815 }, 816 { } 817 }; 818 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 819 820 static struct platform_driver bgpio_driver = { 821 .driver = { 822 .name = "basic-mmio-gpio", 823 .of_match_table = bgpio_of_match, 824 }, 825 .id_table = bgpio_id_table, 826 .probe = bgpio_pdev_probe, 827 }; 828 829 module_platform_driver(bgpio_driver); 830 831 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 832 833 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 834 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 835 MODULE_LICENSE("GPL"); 836