1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/cleanup.h> 45 #include <linux/err.h> 46 #include <linux/io.h> 47 #include <linux/ioport.h> 48 #include <linux/limits.h> 49 #include <linux/log2.h> 50 #include <linux/mod_devicetable.h> 51 #include <linux/module.h> 52 #include <linux/pinctrl/consumer.h> 53 #include <linux/platform_device.h> 54 #include <linux/property.h> 55 #include <linux/spinlock.h> 56 #include <linux/types.h> 57 58 #include <linux/gpio/driver.h> 59 #include <linux/gpio/generic.h> 60 61 #include "gpiolib.h" 62 63 static void gpio_mmio_write8(void __iomem *reg, unsigned long data) 64 { 65 writeb(data, reg); 66 } 67 68 static unsigned long gpio_mmio_read8(void __iomem *reg) 69 { 70 return readb(reg); 71 } 72 73 static void gpio_mmio_write16(void __iomem *reg, unsigned long data) 74 { 75 writew(data, reg); 76 } 77 78 static unsigned long gpio_mmio_read16(void __iomem *reg) 79 { 80 return readw(reg); 81 } 82 83 static void gpio_mmio_write32(void __iomem *reg, unsigned long data) 84 { 85 writel(data, reg); 86 } 87 88 static unsigned long gpio_mmio_read32(void __iomem *reg) 89 { 90 return readl(reg); 91 } 92 93 #if BITS_PER_LONG >= 64 94 static void gpio_mmio_write64(void __iomem *reg, unsigned long data) 95 { 96 writeq(data, reg); 97 } 98 99 static unsigned long gpio_mmio_read64(void __iomem *reg) 100 { 101 return readq(reg); 102 } 103 #endif /* BITS_PER_LONG >= 64 */ 104 105 static void gpio_mmio_write16be(void __iomem *reg, unsigned long data) 106 { 107 iowrite16be(data, reg); 108 } 109 110 static unsigned long gpio_mmio_read16be(void __iomem *reg) 111 { 112 return ioread16be(reg); 113 } 114 115 static void gpio_mmio_write32be(void __iomem *reg, unsigned long data) 116 { 117 iowrite32be(data, reg); 118 } 119 120 static unsigned long gpio_mmio_read32be(void __iomem *reg) 121 { 122 return ioread32be(reg); 123 } 124 125 static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line) 126 { 127 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 128 129 if (chip->be_bits) 130 return BIT(chip->bits - 1 - line); 131 return BIT(line); 132 } 133 134 static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio) 135 { 136 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 137 unsigned long pinmask = gpio_mmio_line2mask(gc, gpio); 138 bool dir = !!(chip->sdir & pinmask); 139 140 if (dir) 141 return !!(chip->read_reg(chip->reg_set) & pinmask); 142 143 return !!(chip->read_reg(chip->reg_dat) & pinmask); 144 } 145 146 /* 147 * This assumes that the bits in the GPIO register are in native endianness. 148 * We only assign the function pointer if we have that. 149 */ 150 static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 151 unsigned long *bits) 152 { 153 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 154 unsigned long get_mask = 0, set_mask = 0; 155 156 /* Make sure we first clear any bits that are zero when we read the register */ 157 *bits &= ~*mask; 158 159 set_mask = *mask & chip->sdir; 160 get_mask = *mask & ~chip->sdir; 161 162 if (set_mask) 163 *bits |= chip->read_reg(chip->reg_set) & set_mask; 164 if (get_mask) 165 *bits |= chip->read_reg(chip->reg_dat) & get_mask; 166 167 return 0; 168 } 169 170 static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio) 171 { 172 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 173 174 return !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio)); 175 } 176 177 /* 178 * This only works if the bits in the GPIO register are in native endianness. 179 */ 180 static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 181 unsigned long *bits) 182 { 183 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 184 185 /* Make sure we first clear any bits that are zero when we read the register */ 186 *bits &= ~*mask; 187 *bits |= chip->read_reg(chip->reg_dat) & *mask; 188 return 0; 189 } 190 191 /* 192 * With big endian mirrored bit order it becomes more tedious. 193 */ 194 static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 195 unsigned long *bits) 196 { 197 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 198 unsigned long readmask = 0; 199 unsigned long val; 200 int bit; 201 202 /* Make sure we first clear any bits that are zero when we read the register */ 203 *bits &= ~*mask; 204 205 /* Create a mirrored mask */ 206 for_each_set_bit(bit, mask, gc->ngpio) 207 readmask |= gpio_mmio_line2mask(gc, bit); 208 209 /* Read the register */ 210 val = chip->read_reg(chip->reg_dat) & readmask; 211 212 /* 213 * Mirror the result into the "bits" result, this will give line 0 214 * in bit 0 ... line 31 in bit 31 for a 32bit register. 215 */ 216 for_each_set_bit(bit, &val, gc->ngpio) 217 *bits |= gpio_mmio_line2mask(gc, bit); 218 219 return 0; 220 } 221 222 static int gpio_mmio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 223 { 224 return 0; 225 } 226 227 static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val) 228 { 229 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 230 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 231 232 guard(raw_spinlock_irqsave)(&chip->lock); 233 234 if (val) 235 chip->sdata |= mask; 236 else 237 chip->sdata &= ~mask; 238 239 chip->write_reg(chip->reg_dat, chip->sdata); 240 241 return 0; 242 } 243 244 static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 245 int val) 246 { 247 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 248 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 249 250 if (val) 251 chip->write_reg(chip->reg_set, mask); 252 else 253 chip->write_reg(chip->reg_clr, mask); 254 255 return 0; 256 } 257 258 static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 259 { 260 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 261 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 262 263 guard(raw_spinlock_irqsave)(&chip->lock); 264 265 if (val) 266 chip->sdata |= mask; 267 else 268 chip->sdata &= ~mask; 269 270 chip->write_reg(chip->reg_set, chip->sdata); 271 272 return 0; 273 } 274 275 static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc, 276 unsigned long *mask, 277 unsigned long *bits, 278 unsigned long *set_mask, 279 unsigned long *clear_mask) 280 { 281 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 282 int i; 283 284 *set_mask = 0; 285 *clear_mask = 0; 286 287 for_each_set_bit(i, mask, chip->bits) { 288 if (test_bit(i, bits)) 289 *set_mask |= gpio_mmio_line2mask(gc, i); 290 else 291 *clear_mask |= gpio_mmio_line2mask(gc, i); 292 } 293 } 294 295 static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc, 296 unsigned long *mask, 297 unsigned long *bits, 298 void __iomem *reg) 299 { 300 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 301 unsigned long set_mask, clear_mask; 302 303 guard(raw_spinlock_irqsave)(&chip->lock); 304 305 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 306 307 chip->sdata |= set_mask; 308 chip->sdata &= ~clear_mask; 309 310 chip->write_reg(reg, chip->sdata); 311 } 312 313 static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 314 unsigned long *bits) 315 { 316 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 317 318 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); 319 320 return 0; 321 } 322 323 static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 324 unsigned long *bits) 325 { 326 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 327 328 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); 329 330 return 0; 331 } 332 333 static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc, 334 unsigned long *mask, 335 unsigned long *bits) 336 { 337 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 338 unsigned long set_mask, clear_mask; 339 340 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 341 342 if (set_mask) 343 chip->write_reg(chip->reg_set, set_mask); 344 if (clear_mask) 345 chip->write_reg(chip->reg_clr, clear_mask); 346 347 return 0; 348 } 349 350 static int gpio_mmio_dir_return(struct gpio_chip *gc, unsigned int gpio, 351 bool dir_out) 352 { 353 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 354 355 if (!chip->pinctrl) 356 return 0; 357 358 if (dir_out) 359 return pinctrl_gpio_direction_output(gc, gpio); 360 else 361 return pinctrl_gpio_direction_input(gc, gpio); 362 } 363 364 static int gpio_mmio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) 365 { 366 return -EINVAL; 367 } 368 369 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 370 { 371 return gpio_mmio_dir_return(gc, gpio, false); 372 } 373 374 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 375 int val) 376 { 377 return -EINVAL; 378 } 379 380 static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 381 int val) 382 { 383 gc->set(gc, gpio, val); 384 385 return gpio_mmio_dir_return(gc, gpio, true); 386 } 387 388 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) 389 { 390 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 391 392 scoped_guard(raw_spinlock_irqsave, &chip->lock) { 393 chip->sdir &= ~gpio_mmio_line2mask(gc, gpio); 394 395 if (chip->reg_dir_in) 396 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 397 if (chip->reg_dir_out) 398 chip->write_reg(chip->reg_dir_out, chip->sdir); 399 } 400 401 return gpio_mmio_dir_return(gc, gpio, false); 402 } 403 404 static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio) 405 { 406 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 407 408 /* Return 0 if output, 1 if input */ 409 if (chip->dir_unreadable) { 410 if (chip->sdir & gpio_mmio_line2mask(gc, gpio)) 411 return GPIO_LINE_DIRECTION_OUT; 412 return GPIO_LINE_DIRECTION_IN; 413 } 414 415 if (chip->reg_dir_out) { 416 if (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio)) 417 return GPIO_LINE_DIRECTION_OUT; 418 return GPIO_LINE_DIRECTION_IN; 419 } 420 421 if (chip->reg_dir_in) 422 if (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio))) 423 return GPIO_LINE_DIRECTION_OUT; 424 425 return GPIO_LINE_DIRECTION_IN; 426 } 427 428 static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 429 { 430 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 431 432 guard(raw_spinlock_irqsave)(&chip->lock); 433 434 chip->sdir |= gpio_mmio_line2mask(gc, gpio); 435 436 if (chip->reg_dir_in) 437 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 438 if (chip->reg_dir_out) 439 chip->write_reg(chip->reg_dir_out, chip->sdir); 440 } 441 442 static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 443 int val) 444 { 445 gpio_mmio_dir_out(gc, gpio, val); 446 gc->set(gc, gpio, val); 447 return gpio_mmio_dir_return(gc, gpio, true); 448 } 449 450 static int gpio_mmio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 451 int val) 452 { 453 gc->set(gc, gpio, val); 454 gpio_mmio_dir_out(gc, gpio, val); 455 return gpio_mmio_dir_return(gc, gpio, true); 456 } 457 458 static int gpio_mmio_setup_accessors(struct device *dev, 459 struct gpio_generic_chip *chip, 460 bool byte_be) 461 { 462 switch (chip->bits) { 463 case 8: 464 chip->read_reg = gpio_mmio_read8; 465 chip->write_reg = gpio_mmio_write8; 466 break; 467 case 16: 468 if (byte_be) { 469 chip->read_reg = gpio_mmio_read16be; 470 chip->write_reg = gpio_mmio_write16be; 471 } else { 472 chip->read_reg = gpio_mmio_read16; 473 chip->write_reg = gpio_mmio_write16; 474 } 475 break; 476 case 32: 477 if (byte_be) { 478 chip->read_reg = gpio_mmio_read32be; 479 chip->write_reg = gpio_mmio_write32be; 480 } else { 481 chip->read_reg = gpio_mmio_read32; 482 chip->write_reg = gpio_mmio_write32; 483 } 484 break; 485 #if BITS_PER_LONG >= 64 486 case 64: 487 if (byte_be) { 488 dev_err(dev, 489 "64 bit big endian byte order unsupported\n"); 490 return -EINVAL; 491 } else { 492 chip->read_reg = gpio_mmio_read64; 493 chip->write_reg = gpio_mmio_write64; 494 } 495 break; 496 #endif /* BITS_PER_LONG >= 64 */ 497 default: 498 dev_err(dev, "unsupported data width %u bits\n", chip->bits); 499 return -EINVAL; 500 } 501 502 return 0; 503 } 504 505 /* 506 * Create the device and allocate the resources. For setting GPIO's there are 507 * three supported configurations: 508 * 509 * - single input/output register resource (named "dat"). 510 * - set/clear pair (named "set" and "clr"). 511 * - single output register resource and single input resource ("set" and 512 * dat"). 513 * 514 * For the single output register, this drives a 1 by setting a bit and a zero 515 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 516 * in the set register and clears it by setting a bit in the clear register. 517 * The configuration is detected by which resources are present. 518 * 519 * For setting the GPIO direction, there are three supported configurations: 520 * 521 * - simple bidirection GPIO that requires no configuration. 522 * - an output direction register (named "dirout") where a 1 bit 523 * indicates the GPIO is an output. 524 * - an input direction register (named "dirin") where a 1 bit indicates 525 * the GPIO is an input. 526 */ 527 static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, 528 const struct gpio_generic_chip_config *cfg) 529 { 530 struct gpio_chip *gc = &chip->gc; 531 532 chip->reg_dat = cfg->dat; 533 if (!chip->reg_dat) 534 return -EINVAL; 535 536 if (cfg->set && cfg->clr) { 537 chip->reg_set = cfg->set; 538 chip->reg_clr = cfg->clr; 539 gc->set = gpio_mmio_set_with_clear; 540 gc->set_multiple = gpio_mmio_set_multiple_with_clear; 541 } else if (cfg->set && !cfg->clr) { 542 chip->reg_set = cfg->set; 543 gc->set = gpio_mmio_set_set; 544 gc->set_multiple = gpio_mmio_set_multiple_set; 545 } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { 546 gc->set = gpio_mmio_set_none; 547 gc->set_multiple = NULL; 548 } else { 549 gc->set = gpio_mmio_set; 550 gc->set_multiple = gpio_mmio_set_multiple; 551 } 552 553 if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && 554 (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { 555 gc->get = gpio_mmio_get_set; 556 if (!chip->be_bits) 557 gc->get_multiple = gpio_mmio_get_set_multiple; 558 /* 559 * We deliberately avoid assigning the ->get_multiple() call 560 * for big endian mirrored registers which are ALSO reflecting 561 * their value in the set register when used as output. It is 562 * simply too much complexity, let the GPIO core fall back to 563 * reading each line individually in that fringe case. 564 */ 565 } else { 566 gc->get = gpio_mmio_get; 567 if (chip->be_bits) 568 gc->get_multiple = gpio_mmio_get_multiple_be; 569 else 570 gc->get_multiple = gpio_mmio_get_multiple; 571 } 572 573 return 0; 574 } 575 576 static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, 577 const struct gpio_generic_chip_config *cfg) 578 { 579 struct gpio_chip *gc = &chip->gc; 580 581 if (cfg->dirout || cfg->dirin) { 582 chip->reg_dir_out = cfg->dirout; 583 chip->reg_dir_in = cfg->dirin; 584 if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) 585 gc->direction_output = gpio_mmio_dir_out_dir_first; 586 else 587 gc->direction_output = gpio_mmio_dir_out_val_first; 588 gc->direction_input = gpio_mmio_dir_in; 589 gc->get_direction = gpio_mmio_get_dir; 590 } else { 591 if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) 592 gc->direction_output = gpio_mmio_dir_out_err; 593 else 594 gc->direction_output = gpio_mmio_simple_dir_out; 595 596 if (cfg->flags & GPIO_GENERIC_NO_INPUT) 597 gc->direction_input = gpio_mmio_dir_in_err; 598 else 599 gc->direction_input = gpio_mmio_simple_dir_in; 600 } 601 602 return 0; 603 } 604 605 static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) 606 { 607 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 608 609 if (gpio_pin >= gc->ngpio) 610 return -EINVAL; 611 612 if (chip->pinctrl) 613 return gpiochip_generic_request(gc, gpio_pin); 614 615 return 0; 616 } 617 618 /** 619 * gpio_generic_chip_init() - Initialize a generic GPIO chip. 620 * @chip: Generic GPIO chip to set up. 621 * @cfg: Generic GPIO chip configuration. 622 * 623 * Returns 0 on success, negative error number on failure. 624 */ 625 int gpio_generic_chip_init(struct gpio_generic_chip *chip, 626 const struct gpio_generic_chip_config *cfg) 627 { 628 struct gpio_chip *gc = &chip->gc; 629 unsigned long flags = cfg->flags; 630 struct device *dev = cfg->dev; 631 int ret; 632 633 if (!is_power_of_2(cfg->sz)) 634 return -EINVAL; 635 636 chip->bits = cfg->sz * 8; 637 if (chip->bits > BITS_PER_LONG) 638 return -EINVAL; 639 640 raw_spin_lock_init(&chip->lock); 641 gc->parent = dev; 642 gc->label = dev_name(dev); 643 gc->base = -1; 644 gc->request = gpio_mmio_request; 645 chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN); 646 647 ret = gpiochip_get_ngpios(gc, dev); 648 if (ret) 649 gc->ngpio = chip->bits; 650 651 ret = gpio_mmio_setup_io(chip, cfg); 652 if (ret) 653 return ret; 654 655 ret = gpio_mmio_setup_accessors(dev, chip, 656 flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); 657 if (ret) 658 return ret; 659 660 ret = gpio_mmio_setup_direction(chip, cfg); 661 if (ret) 662 return ret; 663 664 if (flags & GPIO_GENERIC_PINCTRL_BACKEND) { 665 chip->pinctrl = true; 666 /* Currently this callback is only used for pincontrol */ 667 gc->free = gpiochip_generic_free; 668 } 669 670 chip->sdata = chip->read_reg(chip->reg_dat); 671 if (gc->set == gpio_mmio_set_set && 672 !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) 673 chip->sdata = chip->read_reg(chip->reg_set); 674 675 if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) 676 chip->dir_unreadable = true; 677 678 /* 679 * Inspect hardware to find initial direction setting. 680 */ 681 if ((chip->reg_dir_out || chip->reg_dir_in) && 682 !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { 683 if (chip->reg_dir_out) 684 chip->sdir = chip->read_reg(chip->reg_dir_out); 685 else if (chip->reg_dir_in) 686 chip->sdir = ~chip->read_reg(chip->reg_dir_in); 687 /* 688 * If we have two direction registers, synchronise 689 * input setting to output setting, the library 690 * can not handle a line being input and output at 691 * the same time. 692 */ 693 if (chip->reg_dir_out && chip->reg_dir_in) 694 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 695 } 696 697 return ret; 698 } 699 EXPORT_SYMBOL_GPL(gpio_generic_chip_init); 700 701 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 702 703 static void __iomem *gpio_mmio_map(struct platform_device *pdev, 704 const char *name, resource_size_t sane_sz) 705 { 706 struct resource *r; 707 resource_size_t sz; 708 709 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 710 if (!r) 711 return NULL; 712 713 sz = resource_size(r); 714 if (sz != sane_sz) 715 return IOMEM_ERR_PTR(-EINVAL); 716 717 return devm_ioremap_resource(&pdev->dev, r); 718 } 719 720 static const struct of_device_id gpio_mmio_of_match[] = { 721 { .compatible = "brcm,bcm6345-gpio" }, 722 { .compatible = "wd,mbl-gpio" }, 723 { .compatible = "ni,169445-nand-gpio" }, 724 { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 725 { .compatible = "opencores,gpio" }, 726 { } 727 }; 728 MODULE_DEVICE_TABLE(of, gpio_mmio_of_match); 729 730 static int gpio_mmio_pdev_probe(struct platform_device *pdev) 731 { 732 struct gpio_generic_chip_config config; 733 struct gpio_generic_chip *gen_gc; 734 struct device *dev = &pdev->dev; 735 struct resource *r; 736 void __iomem *dat; 737 void __iomem *set; 738 void __iomem *clr; 739 void __iomem *dirout; 740 void __iomem *dirin; 741 unsigned long sz; 742 unsigned long flags = 0; 743 unsigned int base; 744 int err; 745 const char *label; 746 747 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 748 if (!r) 749 return -EINVAL; 750 751 sz = resource_size(r); 752 753 dat = gpio_mmio_map(pdev, "dat", sz); 754 if (IS_ERR(dat)) 755 return PTR_ERR(dat); 756 757 set = gpio_mmio_map(pdev, "set", sz); 758 if (IS_ERR(set)) 759 return PTR_ERR(set); 760 761 clr = gpio_mmio_map(pdev, "clr", sz); 762 if (IS_ERR(clr)) 763 return PTR_ERR(clr); 764 765 dirout = gpio_mmio_map(pdev, "dirout", sz); 766 if (IS_ERR(dirout)) 767 return PTR_ERR(dirout); 768 769 dirin = gpio_mmio_map(pdev, "dirin", sz); 770 if (IS_ERR(dirin)) 771 return PTR_ERR(dirin); 772 773 gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); 774 if (!gen_gc) 775 return -ENOMEM; 776 777 if (device_is_big_endian(dev)) 778 flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 779 780 if (device_property_read_bool(dev, "no-output")) 781 flags |= GPIO_GENERIC_NO_OUTPUT; 782 783 config = (struct gpio_generic_chip_config) { 784 .dev = dev, 785 .sz = sz, 786 .dat = dat, 787 .set = set, 788 .clr = clr, 789 .dirout = dirout, 790 .dirin = dirin, 791 .flags = flags, 792 }; 793 794 err = gpio_generic_chip_init(gen_gc, &config); 795 if (err) 796 return err; 797 798 err = device_property_read_string(dev, "label", &label); 799 if (!err) 800 gen_gc->gc.label = label; 801 802 /* 803 * This property *must not* be used in device-tree sources, it's only 804 * meant to be passed to the driver from board files and MFD core. 805 */ 806 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 807 if (!err && base <= INT_MAX) 808 gen_gc->gc.base = base; 809 810 platform_set_drvdata(pdev, &gen_gc->gc); 811 812 return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL); 813 } 814 815 static const struct platform_device_id gpio_mmio_id_table[] = { 816 { 817 .name = "basic-mmio-gpio", 818 .driver_data = 0, 819 }, 820 { } 821 }; 822 MODULE_DEVICE_TABLE(platform, gpio_mmio_id_table); 823 824 static struct platform_driver gpio_mmio_driver = { 825 .driver = { 826 .name = "basic-mmio-gpio", 827 .of_match_table = gpio_mmio_of_match, 828 }, 829 .id_table = gpio_mmio_id_table, 830 .probe = gpio_mmio_pdev_probe, 831 }; 832 833 module_platform_driver(gpio_mmio_driver); 834 835 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 836 837 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 838 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 839 MODULE_LICENSE("GPL"); 840