1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/cleanup.h> 45 #include <linux/err.h> 46 #include <linux/io.h> 47 #include <linux/ioport.h> 48 #include <linux/limits.h> 49 #include <linux/log2.h> 50 #include <linux/module.h> 51 #include <linux/pinctrl/consumer.h> 52 #include <linux/platform_device.h> 53 #include <linux/property.h> 54 #include <linux/spinlock.h> 55 #include <linux/types.h> 56 57 #include <linux/gpio/driver.h> 58 #include <linux/gpio/generic.h> 59 60 #include "gpiolib.h" 61 62 static void gpio_mmio_write8(void __iomem *reg, unsigned long data) 63 { 64 writeb(data, reg); 65 } 66 67 static unsigned long gpio_mmio_read8(void __iomem *reg) 68 { 69 return readb(reg); 70 } 71 72 static void gpio_mmio_write16(void __iomem *reg, unsigned long data) 73 { 74 writew(data, reg); 75 } 76 77 static unsigned long gpio_mmio_read16(void __iomem *reg) 78 { 79 return readw(reg); 80 } 81 82 static void gpio_mmio_write32(void __iomem *reg, unsigned long data) 83 { 84 writel(data, reg); 85 } 86 87 static unsigned long gpio_mmio_read32(void __iomem *reg) 88 { 89 return readl(reg); 90 } 91 92 #if BITS_PER_LONG >= 64 93 static void gpio_mmio_write64(void __iomem *reg, unsigned long data) 94 { 95 writeq(data, reg); 96 } 97 98 static unsigned long gpio_mmio_read64(void __iomem *reg) 99 { 100 return readq(reg); 101 } 102 #endif /* BITS_PER_LONG >= 64 */ 103 104 static void gpio_mmio_write16be(void __iomem *reg, unsigned long data) 105 { 106 iowrite16be(data, reg); 107 } 108 109 static unsigned long gpio_mmio_read16be(void __iomem *reg) 110 { 111 return ioread16be(reg); 112 } 113 114 static void gpio_mmio_write32be(void __iomem *reg, unsigned long data) 115 { 116 iowrite32be(data, reg); 117 } 118 119 static unsigned long gpio_mmio_read32be(void __iomem *reg) 120 { 121 return ioread32be(reg); 122 } 123 124 static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line) 125 { 126 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 127 128 if (chip->be_bits) 129 return BIT(chip->bits - 1 - line); 130 return BIT(line); 131 } 132 133 static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio) 134 { 135 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 136 unsigned long pinmask = gpio_mmio_line2mask(gc, gpio); 137 bool dir = !!(chip->sdir & pinmask); 138 139 if (dir) 140 return !!(chip->read_reg(chip->reg_set) & pinmask); 141 142 return !!(chip->read_reg(chip->reg_dat) & pinmask); 143 } 144 145 /* 146 * This assumes that the bits in the GPIO register are in native endianness. 147 * We only assign the function pointer if we have that. 148 */ 149 static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 150 unsigned long *bits) 151 { 152 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 153 unsigned long get_mask = 0, set_mask = 0; 154 155 /* Make sure we first clear any bits that are zero when we read the register */ 156 *bits &= ~*mask; 157 158 set_mask = *mask & chip->sdir; 159 get_mask = *mask & ~chip->sdir; 160 161 if (set_mask) 162 *bits |= chip->read_reg(chip->reg_set) & set_mask; 163 if (get_mask) 164 *bits |= chip->read_reg(chip->reg_dat) & get_mask; 165 166 return 0; 167 } 168 169 static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio) 170 { 171 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 172 173 return !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio)); 174 } 175 176 /* 177 * This only works if the bits in the GPIO register are in native endianness. 178 */ 179 static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 180 unsigned long *bits) 181 { 182 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 183 184 /* Make sure we first clear any bits that are zero when we read the register */ 185 *bits &= ~*mask; 186 *bits |= chip->read_reg(chip->reg_dat) & *mask; 187 return 0; 188 } 189 190 /* 191 * With big endian mirrored bit order it becomes more tedious. 192 */ 193 static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 194 unsigned long *bits) 195 { 196 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 197 unsigned long readmask = 0; 198 unsigned long val; 199 int bit; 200 201 /* Make sure we first clear any bits that are zero when we read the register */ 202 *bits &= ~*mask; 203 204 /* Create a mirrored mask */ 205 for_each_set_bit(bit, mask, gc->ngpio) 206 readmask |= gpio_mmio_line2mask(gc, bit); 207 208 /* Read the register */ 209 val = chip->read_reg(chip->reg_dat) & readmask; 210 211 /* 212 * Mirror the result into the "bits" result, this will give line 0 213 * in bit 0 ... line 31 in bit 31 for a 32bit register. 214 */ 215 for_each_set_bit(bit, &val, gc->ngpio) 216 *bits |= gpio_mmio_line2mask(gc, bit); 217 218 return 0; 219 } 220 221 static int gpio_mmio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 222 { 223 return 0; 224 } 225 226 static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val) 227 { 228 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 229 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 230 231 guard(raw_spinlock_irqsave)(&chip->lock); 232 233 if (val) 234 chip->sdata |= mask; 235 else 236 chip->sdata &= ~mask; 237 238 chip->write_reg(chip->reg_dat, chip->sdata); 239 240 return 0; 241 } 242 243 static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 244 int val) 245 { 246 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 247 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 248 249 if (val) 250 chip->write_reg(chip->reg_set, mask); 251 else 252 chip->write_reg(chip->reg_clr, mask); 253 254 return 0; 255 } 256 257 static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 258 { 259 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 260 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 261 262 guard(raw_spinlock_irqsave)(&chip->lock); 263 264 if (val) 265 chip->sdata |= mask; 266 else 267 chip->sdata &= ~mask; 268 269 chip->write_reg(chip->reg_set, chip->sdata); 270 271 return 0; 272 } 273 274 static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc, 275 unsigned long *mask, 276 unsigned long *bits, 277 unsigned long *set_mask, 278 unsigned long *clear_mask) 279 { 280 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 281 int i; 282 283 *set_mask = 0; 284 *clear_mask = 0; 285 286 for_each_set_bit(i, mask, chip->bits) { 287 if (test_bit(i, bits)) 288 *set_mask |= gpio_mmio_line2mask(gc, i); 289 else 290 *clear_mask |= gpio_mmio_line2mask(gc, i); 291 } 292 } 293 294 static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc, 295 unsigned long *mask, 296 unsigned long *bits, 297 void __iomem *reg) 298 { 299 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 300 unsigned long set_mask, clear_mask; 301 302 guard(raw_spinlock_irqsave)(&chip->lock); 303 304 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 305 306 chip->sdata |= set_mask; 307 chip->sdata &= ~clear_mask; 308 309 chip->write_reg(reg, chip->sdata); 310 } 311 312 static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 313 unsigned long *bits) 314 { 315 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 316 317 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); 318 319 return 0; 320 } 321 322 static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 323 unsigned long *bits) 324 { 325 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 326 327 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); 328 329 return 0; 330 } 331 332 static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc, 333 unsigned long *mask, 334 unsigned long *bits) 335 { 336 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 337 unsigned long set_mask, clear_mask; 338 339 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 340 341 if (set_mask) 342 chip->write_reg(chip->reg_set, set_mask); 343 if (clear_mask) 344 chip->write_reg(chip->reg_clr, clear_mask); 345 346 return 0; 347 } 348 349 static int gpio_mmio_dir_return(struct gpio_chip *gc, unsigned int gpio, 350 bool dir_out) 351 { 352 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 353 354 if (!chip->pinctrl) 355 return 0; 356 357 if (dir_out) 358 return pinctrl_gpio_direction_output(gc, gpio); 359 else 360 return pinctrl_gpio_direction_input(gc, gpio); 361 } 362 363 static int gpio_mmio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) 364 { 365 return -EINVAL; 366 } 367 368 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 369 { 370 return gpio_mmio_dir_return(gc, gpio, false); 371 } 372 373 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 374 int val) 375 { 376 return -EINVAL; 377 } 378 379 static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 380 int val) 381 { 382 gc->set(gc, gpio, val); 383 384 return gpio_mmio_dir_return(gc, gpio, true); 385 } 386 387 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) 388 { 389 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 390 391 scoped_guard(raw_spinlock_irqsave, &chip->lock) { 392 chip->sdir &= ~gpio_mmio_line2mask(gc, gpio); 393 394 if (chip->reg_dir_in) 395 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 396 if (chip->reg_dir_out) 397 chip->write_reg(chip->reg_dir_out, chip->sdir); 398 } 399 400 return gpio_mmio_dir_return(gc, gpio, false); 401 } 402 403 static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio) 404 { 405 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 406 407 /* Return 0 if output, 1 if input */ 408 if (chip->dir_unreadable) { 409 if (chip->sdir & gpio_mmio_line2mask(gc, gpio)) 410 return GPIO_LINE_DIRECTION_OUT; 411 return GPIO_LINE_DIRECTION_IN; 412 } 413 414 if (chip->reg_dir_out) { 415 if (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio)) 416 return GPIO_LINE_DIRECTION_OUT; 417 return GPIO_LINE_DIRECTION_IN; 418 } 419 420 if (chip->reg_dir_in) 421 if (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio))) 422 return GPIO_LINE_DIRECTION_OUT; 423 424 return GPIO_LINE_DIRECTION_IN; 425 } 426 427 static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 428 { 429 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 430 431 guard(raw_spinlock_irqsave)(&chip->lock); 432 433 chip->sdir |= gpio_mmio_line2mask(gc, gpio); 434 435 if (chip->reg_dir_in) 436 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 437 if (chip->reg_dir_out) 438 chip->write_reg(chip->reg_dir_out, chip->sdir); 439 } 440 441 static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 442 int val) 443 { 444 gpio_mmio_dir_out(gc, gpio, val); 445 gc->set(gc, gpio, val); 446 return gpio_mmio_dir_return(gc, gpio, true); 447 } 448 449 static int gpio_mmio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 450 int val) 451 { 452 gc->set(gc, gpio, val); 453 gpio_mmio_dir_out(gc, gpio, val); 454 return gpio_mmio_dir_return(gc, gpio, true); 455 } 456 457 static int gpio_mmio_setup_accessors(struct device *dev, 458 struct gpio_generic_chip *chip, 459 bool byte_be) 460 { 461 switch (chip->bits) { 462 case 8: 463 chip->read_reg = gpio_mmio_read8; 464 chip->write_reg = gpio_mmio_write8; 465 break; 466 case 16: 467 if (byte_be) { 468 chip->read_reg = gpio_mmio_read16be; 469 chip->write_reg = gpio_mmio_write16be; 470 } else { 471 chip->read_reg = gpio_mmio_read16; 472 chip->write_reg = gpio_mmio_write16; 473 } 474 break; 475 case 32: 476 if (byte_be) { 477 chip->read_reg = gpio_mmio_read32be; 478 chip->write_reg = gpio_mmio_write32be; 479 } else { 480 chip->read_reg = gpio_mmio_read32; 481 chip->write_reg = gpio_mmio_write32; 482 } 483 break; 484 #if BITS_PER_LONG >= 64 485 case 64: 486 if (byte_be) { 487 dev_err(dev, 488 "64 bit big endian byte order unsupported\n"); 489 return -EINVAL; 490 } else { 491 chip->read_reg = gpio_mmio_read64; 492 chip->write_reg = gpio_mmio_write64; 493 } 494 break; 495 #endif /* BITS_PER_LONG >= 64 */ 496 default: 497 dev_err(dev, "unsupported data width %u bits\n", chip->bits); 498 return -EINVAL; 499 } 500 501 return 0; 502 } 503 504 /* 505 * Create the device and allocate the resources. For setting GPIO's there are 506 * three supported configurations: 507 * 508 * - single input/output register resource (named "dat"). 509 * - set/clear pair (named "set" and "clr"). 510 * - single output register resource and single input resource ("set" and 511 * dat"). 512 * 513 * For the single output register, this drives a 1 by setting a bit and a zero 514 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 515 * in the set register and clears it by setting a bit in the clear register. 516 * The configuration is detected by which resources are present. 517 * 518 * For setting the GPIO direction, there are three supported configurations: 519 * 520 * - simple bidirection GPIO that requires no configuration. 521 * - an output direction register (named "dirout") where a 1 bit 522 * indicates the GPIO is an output. 523 * - an input direction register (named "dirin") where a 1 bit indicates 524 * the GPIO is an input. 525 */ 526 static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, 527 const struct gpio_generic_chip_config *cfg) 528 { 529 struct gpio_chip *gc = &chip->gc; 530 531 chip->reg_dat = cfg->dat; 532 if (!chip->reg_dat) 533 return -EINVAL; 534 535 if (cfg->set && cfg->clr) { 536 chip->reg_set = cfg->set; 537 chip->reg_clr = cfg->clr; 538 gc->set = gpio_mmio_set_with_clear; 539 gc->set_multiple = gpio_mmio_set_multiple_with_clear; 540 } else if (cfg->set && !cfg->clr) { 541 chip->reg_set = cfg->set; 542 gc->set = gpio_mmio_set_set; 543 gc->set_multiple = gpio_mmio_set_multiple_set; 544 } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { 545 gc->set = gpio_mmio_set_none; 546 gc->set_multiple = NULL; 547 } else { 548 gc->set = gpio_mmio_set; 549 gc->set_multiple = gpio_mmio_set_multiple; 550 } 551 552 if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && 553 (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { 554 gc->get = gpio_mmio_get_set; 555 if (!chip->be_bits) 556 gc->get_multiple = gpio_mmio_get_set_multiple; 557 /* 558 * We deliberately avoid assigning the ->get_multiple() call 559 * for big endian mirrored registers which are ALSO reflecting 560 * their value in the set register when used as output. It is 561 * simply too much complexity, let the GPIO core fall back to 562 * reading each line individually in that fringe case. 563 */ 564 } else { 565 gc->get = gpio_mmio_get; 566 if (chip->be_bits) 567 gc->get_multiple = gpio_mmio_get_multiple_be; 568 else 569 gc->get_multiple = gpio_mmio_get_multiple; 570 } 571 572 return 0; 573 } 574 575 static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, 576 const struct gpio_generic_chip_config *cfg) 577 { 578 struct gpio_chip *gc = &chip->gc; 579 580 if (cfg->dirout || cfg->dirin) { 581 chip->reg_dir_out = cfg->dirout; 582 chip->reg_dir_in = cfg->dirin; 583 if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) 584 gc->direction_output = gpio_mmio_dir_out_dir_first; 585 else 586 gc->direction_output = gpio_mmio_dir_out_val_first; 587 gc->direction_input = gpio_mmio_dir_in; 588 gc->get_direction = gpio_mmio_get_dir; 589 } else { 590 if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) 591 gc->direction_output = gpio_mmio_dir_out_err; 592 else 593 gc->direction_output = gpio_mmio_simple_dir_out; 594 595 if (cfg->flags & GPIO_GENERIC_NO_INPUT) 596 gc->direction_input = gpio_mmio_dir_in_err; 597 else 598 gc->direction_input = gpio_mmio_simple_dir_in; 599 } 600 601 return 0; 602 } 603 604 static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) 605 { 606 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 607 608 if (gpio_pin >= gc->ngpio) 609 return -EINVAL; 610 611 if (chip->pinctrl) 612 return gpiochip_generic_request(gc, gpio_pin); 613 614 return 0; 615 } 616 617 /** 618 * gpio_generic_chip_init() - Initialize a generic GPIO chip. 619 * @chip: Generic GPIO chip to set up. 620 * @cfg: Generic GPIO chip configuration. 621 * 622 * Returns 0 on success, negative error number on failure. 623 */ 624 int gpio_generic_chip_init(struct gpio_generic_chip *chip, 625 const struct gpio_generic_chip_config *cfg) 626 { 627 struct gpio_chip *gc = &chip->gc; 628 unsigned long flags = cfg->flags; 629 struct device *dev = cfg->dev; 630 int ret; 631 632 if (!is_power_of_2(cfg->sz)) 633 return -EINVAL; 634 635 chip->bits = cfg->sz * 8; 636 if (chip->bits > BITS_PER_LONG) 637 return -EINVAL; 638 639 raw_spin_lock_init(&chip->lock); 640 gc->parent = dev; 641 gc->label = dev_name(dev); 642 gc->base = -1; 643 gc->request = gpio_mmio_request; 644 chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN); 645 646 ret = gpiochip_get_ngpios(gc, dev); 647 if (ret) 648 gc->ngpio = chip->bits; 649 650 ret = gpio_mmio_setup_io(chip, cfg); 651 if (ret) 652 return ret; 653 654 ret = gpio_mmio_setup_accessors(dev, chip, 655 flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); 656 if (ret) 657 return ret; 658 659 ret = gpio_mmio_setup_direction(chip, cfg); 660 if (ret) 661 return ret; 662 663 if (flags & GPIO_GENERIC_PINCTRL_BACKEND) { 664 chip->pinctrl = true; 665 /* Currently this callback is only used for pincontrol */ 666 gc->free = gpiochip_generic_free; 667 } 668 669 chip->sdata = chip->read_reg(chip->reg_dat); 670 if (gc->set == gpio_mmio_set_set && 671 !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) 672 chip->sdata = chip->read_reg(chip->reg_set); 673 674 if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) 675 chip->dir_unreadable = true; 676 677 /* 678 * Inspect hardware to find initial direction setting. 679 */ 680 if ((chip->reg_dir_out || chip->reg_dir_in) && 681 !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { 682 if (chip->reg_dir_out) 683 chip->sdir = chip->read_reg(chip->reg_dir_out); 684 else if (chip->reg_dir_in) 685 chip->sdir = ~chip->read_reg(chip->reg_dir_in); 686 /* 687 * If we have two direction registers, synchronise 688 * input setting to output setting, the library 689 * can not handle a line being input and output at 690 * the same time. 691 */ 692 if (chip->reg_dir_out && chip->reg_dir_in) 693 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 694 } 695 696 return ret; 697 } 698 EXPORT_SYMBOL_GPL(gpio_generic_chip_init); 699 700 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 701 702 static void __iomem *gpio_mmio_map(struct platform_device *pdev, 703 const char *name, resource_size_t sane_sz) 704 { 705 struct resource *r; 706 resource_size_t sz; 707 708 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 709 if (!r) 710 return NULL; 711 712 sz = resource_size(r); 713 if (sz != sane_sz) 714 return IOMEM_ERR_PTR(-EINVAL); 715 716 return devm_ioremap_resource(&pdev->dev, r); 717 } 718 719 static const struct of_device_id gpio_mmio_of_match[] = { 720 { .compatible = "brcm,bcm6345-gpio" }, 721 { .compatible = "wd,mbl-gpio" }, 722 { .compatible = "ni,169445-nand-gpio" }, 723 { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 724 { .compatible = "opencores,gpio" }, 725 { } 726 }; 727 MODULE_DEVICE_TABLE(of, gpio_mmio_of_match); 728 729 static int gpio_mmio_pdev_probe(struct platform_device *pdev) 730 { 731 struct gpio_generic_chip_config config; 732 struct gpio_generic_chip *gen_gc; 733 struct device *dev = &pdev->dev; 734 struct resource *r; 735 void __iomem *dat; 736 void __iomem *set; 737 void __iomem *clr; 738 void __iomem *dirout; 739 void __iomem *dirin; 740 unsigned long sz; 741 unsigned long flags = 0; 742 unsigned int base; 743 int err; 744 const char *label; 745 746 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 747 if (!r) 748 return -EINVAL; 749 750 sz = resource_size(r); 751 752 dat = gpio_mmio_map(pdev, "dat", sz); 753 if (IS_ERR(dat)) 754 return PTR_ERR(dat); 755 756 set = gpio_mmio_map(pdev, "set", sz); 757 if (IS_ERR(set)) 758 return PTR_ERR(set); 759 760 clr = gpio_mmio_map(pdev, "clr", sz); 761 if (IS_ERR(clr)) 762 return PTR_ERR(clr); 763 764 dirout = gpio_mmio_map(pdev, "dirout", sz); 765 if (IS_ERR(dirout)) 766 return PTR_ERR(dirout); 767 768 dirin = gpio_mmio_map(pdev, "dirin", sz); 769 if (IS_ERR(dirin)) 770 return PTR_ERR(dirin); 771 772 gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); 773 if (!gen_gc) 774 return -ENOMEM; 775 776 if (device_is_big_endian(dev)) 777 flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 778 779 if (device_property_read_bool(dev, "no-output")) 780 flags |= GPIO_GENERIC_NO_OUTPUT; 781 782 config = (struct gpio_generic_chip_config) { 783 .dev = dev, 784 .sz = sz, 785 .dat = dat, 786 .set = set, 787 .clr = clr, 788 .dirout = dirout, 789 .dirin = dirin, 790 .flags = flags, 791 }; 792 793 err = gpio_generic_chip_init(gen_gc, &config); 794 if (err) 795 return err; 796 797 err = device_property_read_string(dev, "label", &label); 798 if (!err) 799 gen_gc->gc.label = label; 800 801 /* 802 * This property *must not* be used in device-tree sources, it's only 803 * meant to be passed to the driver from board files and MFD core. 804 */ 805 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 806 if (!err && base <= INT_MAX) 807 gen_gc->gc.base = base; 808 809 platform_set_drvdata(pdev, &gen_gc->gc); 810 811 return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL); 812 } 813 814 static const struct platform_device_id gpio_mmio_id_table[] = { 815 { 816 .name = "basic-mmio-gpio", 817 .driver_data = 0, 818 }, 819 { } 820 }; 821 MODULE_DEVICE_TABLE(platform, gpio_mmio_id_table); 822 823 static struct platform_driver gpio_mmio_driver = { 824 .driver = { 825 .name = "basic-mmio-gpio", 826 .of_match_table = gpio_mmio_of_match, 827 }, 828 .id_table = gpio_mmio_id_table, 829 .probe = gpio_mmio_pdev_probe, 830 }; 831 832 module_platform_driver(gpio_mmio_driver); 833 834 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 835 836 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 837 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 838 MODULE_LICENSE("GPL"); 839