1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/cleanup.h> 45 #include <linux/compiler.h> 46 #include <linux/err.h> 47 #include <linux/init.h> 48 #include <linux/io.h> 49 #include <linux/ioport.h> 50 #include <linux/log2.h> 51 #include <linux/mod_devicetable.h> 52 #include <linux/module.h> 53 #include <linux/pinctrl/consumer.h> 54 #include <linux/platform_device.h> 55 #include <linux/property.h> 56 #include <linux/slab.h> 57 #include <linux/spinlock.h> 58 #include <linux/types.h> 59 60 #include <linux/gpio/driver.h> 61 #include <linux/gpio/generic.h> 62 63 #include "gpiolib.h" 64 65 static void gpio_mmio_write8(void __iomem *reg, unsigned long data) 66 { 67 writeb(data, reg); 68 } 69 70 static unsigned long gpio_mmio_read8(void __iomem *reg) 71 { 72 return readb(reg); 73 } 74 75 static void gpio_mmio_write16(void __iomem *reg, unsigned long data) 76 { 77 writew(data, reg); 78 } 79 80 static unsigned long gpio_mmio_read16(void __iomem *reg) 81 { 82 return readw(reg); 83 } 84 85 static void gpio_mmio_write32(void __iomem *reg, unsigned long data) 86 { 87 writel(data, reg); 88 } 89 90 static unsigned long gpio_mmio_read32(void __iomem *reg) 91 { 92 return readl(reg); 93 } 94 95 #if BITS_PER_LONG >= 64 96 static void gpio_mmio_write64(void __iomem *reg, unsigned long data) 97 { 98 writeq(data, reg); 99 } 100 101 static unsigned long gpio_mmio_read64(void __iomem *reg) 102 { 103 return readq(reg); 104 } 105 #endif /* BITS_PER_LONG >= 64 */ 106 107 static void gpio_mmio_write16be(void __iomem *reg, unsigned long data) 108 { 109 iowrite16be(data, reg); 110 } 111 112 static unsigned long gpio_mmio_read16be(void __iomem *reg) 113 { 114 return ioread16be(reg); 115 } 116 117 static void gpio_mmio_write32be(void __iomem *reg, unsigned long data) 118 { 119 iowrite32be(data, reg); 120 } 121 122 static unsigned long gpio_mmio_read32be(void __iomem *reg) 123 { 124 return ioread32be(reg); 125 } 126 127 static unsigned long gpio_mmio_line2mask(struct gpio_chip *gc, unsigned int line) 128 { 129 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 130 131 if (chip->be_bits) 132 return BIT(chip->bits - 1 - line); 133 return BIT(line); 134 } 135 136 static int gpio_mmio_get_set(struct gpio_chip *gc, unsigned int gpio) 137 { 138 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 139 unsigned long pinmask = gpio_mmio_line2mask(gc, gpio); 140 bool dir = !!(chip->sdir & pinmask); 141 142 if (dir) 143 return !!(chip->read_reg(chip->reg_set) & pinmask); 144 145 return !!(chip->read_reg(chip->reg_dat) & pinmask); 146 } 147 148 /* 149 * This assumes that the bits in the GPIO register are in native endianness. 150 * We only assign the function pointer if we have that. 151 */ 152 static int gpio_mmio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 153 unsigned long *bits) 154 { 155 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 156 unsigned long get_mask = 0, set_mask = 0; 157 158 /* Make sure we first clear any bits that are zero when we read the register */ 159 *bits &= ~*mask; 160 161 set_mask = *mask & chip->sdir; 162 get_mask = *mask & ~chip->sdir; 163 164 if (set_mask) 165 *bits |= chip->read_reg(chip->reg_set) & set_mask; 166 if (get_mask) 167 *bits |= chip->read_reg(chip->reg_dat) & get_mask; 168 169 return 0; 170 } 171 172 static int gpio_mmio_get(struct gpio_chip *gc, unsigned int gpio) 173 { 174 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 175 176 return !!(chip->read_reg(chip->reg_dat) & gpio_mmio_line2mask(gc, gpio)); 177 } 178 179 /* 180 * This only works if the bits in the GPIO register are in native endianness. 181 */ 182 static int gpio_mmio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 183 unsigned long *bits) 184 { 185 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 186 187 /* Make sure we first clear any bits that are zero when we read the register */ 188 *bits &= ~*mask; 189 *bits |= chip->read_reg(chip->reg_dat) & *mask; 190 return 0; 191 } 192 193 /* 194 * With big endian mirrored bit order it becomes more tedious. 195 */ 196 static int gpio_mmio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 197 unsigned long *bits) 198 { 199 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 200 unsigned long readmask = 0; 201 unsigned long val; 202 int bit; 203 204 /* Make sure we first clear any bits that are zero when we read the register */ 205 *bits &= ~*mask; 206 207 /* Create a mirrored mask */ 208 for_each_set_bit(bit, mask, gc->ngpio) 209 readmask |= gpio_mmio_line2mask(gc, bit); 210 211 /* Read the register */ 212 val = chip->read_reg(chip->reg_dat) & readmask; 213 214 /* 215 * Mirror the result into the "bits" result, this will give line 0 216 * in bit 0 ... line 31 in bit 31 for a 32bit register. 217 */ 218 for_each_set_bit(bit, &val, gc->ngpio) 219 *bits |= gpio_mmio_line2mask(gc, bit); 220 221 return 0; 222 } 223 224 static int gpio_mmio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 225 { 226 return 0; 227 } 228 229 static int gpio_mmio_set(struct gpio_chip *gc, unsigned int gpio, int val) 230 { 231 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 232 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 233 234 guard(raw_spinlock_irqsave)(&chip->lock); 235 236 if (val) 237 chip->sdata |= mask; 238 else 239 chip->sdata &= ~mask; 240 241 chip->write_reg(chip->reg_dat, chip->sdata); 242 243 return 0; 244 } 245 246 static int gpio_mmio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 247 int val) 248 { 249 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 250 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 251 252 if (val) 253 chip->write_reg(chip->reg_set, mask); 254 else 255 chip->write_reg(chip->reg_clr, mask); 256 257 return 0; 258 } 259 260 static int gpio_mmio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 261 { 262 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 263 unsigned long mask = gpio_mmio_line2mask(gc, gpio); 264 265 guard(raw_spinlock_irqsave)(&chip->lock); 266 267 if (val) 268 chip->sdata |= mask; 269 else 270 chip->sdata &= ~mask; 271 272 chip->write_reg(chip->reg_set, chip->sdata); 273 274 return 0; 275 } 276 277 static void gpio_mmio_multiple_get_masks(struct gpio_chip *gc, 278 unsigned long *mask, 279 unsigned long *bits, 280 unsigned long *set_mask, 281 unsigned long *clear_mask) 282 { 283 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 284 int i; 285 286 *set_mask = 0; 287 *clear_mask = 0; 288 289 for_each_set_bit(i, mask, chip->bits) { 290 if (test_bit(i, bits)) 291 *set_mask |= gpio_mmio_line2mask(gc, i); 292 else 293 *clear_mask |= gpio_mmio_line2mask(gc, i); 294 } 295 } 296 297 static void gpio_mmio_set_multiple_single_reg(struct gpio_chip *gc, 298 unsigned long *mask, 299 unsigned long *bits, 300 void __iomem *reg) 301 { 302 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 303 unsigned long set_mask, clear_mask; 304 305 guard(raw_spinlock_irqsave)(&chip->lock); 306 307 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 308 309 chip->sdata |= set_mask; 310 chip->sdata &= ~clear_mask; 311 312 chip->write_reg(reg, chip->sdata); 313 } 314 315 static int gpio_mmio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 316 unsigned long *bits) 317 { 318 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 319 320 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); 321 322 return 0; 323 } 324 325 static int gpio_mmio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 326 unsigned long *bits) 327 { 328 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 329 330 gpio_mmio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); 331 332 return 0; 333 } 334 335 static int gpio_mmio_set_multiple_with_clear(struct gpio_chip *gc, 336 unsigned long *mask, 337 unsigned long *bits) 338 { 339 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 340 unsigned long set_mask, clear_mask; 341 342 gpio_mmio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 343 344 if (set_mask) 345 chip->write_reg(chip->reg_set, set_mask); 346 if (clear_mask) 347 chip->write_reg(chip->reg_clr, clear_mask); 348 349 return 0; 350 } 351 352 static int gpio_mmio_dir_return(struct gpio_chip *gc, unsigned int gpio, 353 bool dir_out) 354 { 355 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 356 357 if (!chip->pinctrl) 358 return 0; 359 360 if (dir_out) 361 return pinctrl_gpio_direction_output(gc, gpio); 362 else 363 return pinctrl_gpio_direction_input(gc, gpio); 364 } 365 366 static int gpio_mmio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) 367 { 368 return -EINVAL; 369 } 370 371 static int gpio_mmio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 372 { 373 return gpio_mmio_dir_return(gc, gpio, false); 374 } 375 376 static int gpio_mmio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 377 int val) 378 { 379 return -EINVAL; 380 } 381 382 static int gpio_mmio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 383 int val) 384 { 385 gc->set(gc, gpio, val); 386 387 return gpio_mmio_dir_return(gc, gpio, true); 388 } 389 390 static int gpio_mmio_dir_in(struct gpio_chip *gc, unsigned int gpio) 391 { 392 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 393 394 scoped_guard(raw_spinlock_irqsave, &chip->lock) { 395 chip->sdir &= ~gpio_mmio_line2mask(gc, gpio); 396 397 if (chip->reg_dir_in) 398 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 399 if (chip->reg_dir_out) 400 chip->write_reg(chip->reg_dir_out, chip->sdir); 401 } 402 403 return gpio_mmio_dir_return(gc, gpio, false); 404 } 405 406 static int gpio_mmio_get_dir(struct gpio_chip *gc, unsigned int gpio) 407 { 408 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 409 410 /* Return 0 if output, 1 if input */ 411 if (chip->dir_unreadable) { 412 if (chip->sdir & gpio_mmio_line2mask(gc, gpio)) 413 return GPIO_LINE_DIRECTION_OUT; 414 return GPIO_LINE_DIRECTION_IN; 415 } 416 417 if (chip->reg_dir_out) { 418 if (chip->read_reg(chip->reg_dir_out) & gpio_mmio_line2mask(gc, gpio)) 419 return GPIO_LINE_DIRECTION_OUT; 420 return GPIO_LINE_DIRECTION_IN; 421 } 422 423 if (chip->reg_dir_in) 424 if (!(chip->read_reg(chip->reg_dir_in) & gpio_mmio_line2mask(gc, gpio))) 425 return GPIO_LINE_DIRECTION_OUT; 426 427 return GPIO_LINE_DIRECTION_IN; 428 } 429 430 static void gpio_mmio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 431 { 432 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 433 434 guard(raw_spinlock_irqsave)(&chip->lock); 435 436 chip->sdir |= gpio_mmio_line2mask(gc, gpio); 437 438 if (chip->reg_dir_in) 439 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 440 if (chip->reg_dir_out) 441 chip->write_reg(chip->reg_dir_out, chip->sdir); 442 } 443 444 static int gpio_mmio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 445 int val) 446 { 447 gpio_mmio_dir_out(gc, gpio, val); 448 gc->set(gc, gpio, val); 449 return gpio_mmio_dir_return(gc, gpio, true); 450 } 451 452 static int gpio_mmio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 453 int val) 454 { 455 gc->set(gc, gpio, val); 456 gpio_mmio_dir_out(gc, gpio, val); 457 return gpio_mmio_dir_return(gc, gpio, true); 458 } 459 460 static int gpio_mmio_setup_accessors(struct device *dev, 461 struct gpio_generic_chip *chip, 462 bool byte_be) 463 { 464 switch (chip->bits) { 465 case 8: 466 chip->read_reg = gpio_mmio_read8; 467 chip->write_reg = gpio_mmio_write8; 468 break; 469 case 16: 470 if (byte_be) { 471 chip->read_reg = gpio_mmio_read16be; 472 chip->write_reg = gpio_mmio_write16be; 473 } else { 474 chip->read_reg = gpio_mmio_read16; 475 chip->write_reg = gpio_mmio_write16; 476 } 477 break; 478 case 32: 479 if (byte_be) { 480 chip->read_reg = gpio_mmio_read32be; 481 chip->write_reg = gpio_mmio_write32be; 482 } else { 483 chip->read_reg = gpio_mmio_read32; 484 chip->write_reg = gpio_mmio_write32; 485 } 486 break; 487 #if BITS_PER_LONG >= 64 488 case 64: 489 if (byte_be) { 490 dev_err(dev, 491 "64 bit big endian byte order unsupported\n"); 492 return -EINVAL; 493 } else { 494 chip->read_reg = gpio_mmio_read64; 495 chip->write_reg = gpio_mmio_write64; 496 } 497 break; 498 #endif /* BITS_PER_LONG >= 64 */ 499 default: 500 dev_err(dev, "unsupported data width %u bits\n", chip->bits); 501 return -EINVAL; 502 } 503 504 return 0; 505 } 506 507 /* 508 * Create the device and allocate the resources. For setting GPIO's there are 509 * three supported configurations: 510 * 511 * - single input/output register resource (named "dat"). 512 * - set/clear pair (named "set" and "clr"). 513 * - single output register resource and single input resource ("set" and 514 * dat"). 515 * 516 * For the single output register, this drives a 1 by setting a bit and a zero 517 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 518 * in the set register and clears it by setting a bit in the clear register. 519 * The configuration is detected by which resources are present. 520 * 521 * For setting the GPIO direction, there are three supported configurations: 522 * 523 * - simple bidirection GPIO that requires no configuration. 524 * - an output direction register (named "dirout") where a 1 bit 525 * indicates the GPIO is an output. 526 * - an input direction register (named "dirin") where a 1 bit indicates 527 * the GPIO is an input. 528 */ 529 static int gpio_mmio_setup_io(struct gpio_generic_chip *chip, 530 const struct gpio_generic_chip_config *cfg) 531 { 532 struct gpio_chip *gc = &chip->gc; 533 534 chip->reg_dat = cfg->dat; 535 if (!chip->reg_dat) 536 return -EINVAL; 537 538 if (cfg->set && cfg->clr) { 539 chip->reg_set = cfg->set; 540 chip->reg_clr = cfg->clr; 541 gc->set = gpio_mmio_set_with_clear; 542 gc->set_multiple = gpio_mmio_set_multiple_with_clear; 543 } else if (cfg->set && !cfg->clr) { 544 chip->reg_set = cfg->set; 545 gc->set = gpio_mmio_set_set; 546 gc->set_multiple = gpio_mmio_set_multiple_set; 547 } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { 548 gc->set = gpio_mmio_set_none; 549 gc->set_multiple = NULL; 550 } else { 551 gc->set = gpio_mmio_set; 552 gc->set_multiple = gpio_mmio_set_multiple; 553 } 554 555 if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && 556 (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { 557 gc->get = gpio_mmio_get_set; 558 if (!chip->be_bits) 559 gc->get_multiple = gpio_mmio_get_set_multiple; 560 /* 561 * We deliberately avoid assigning the ->get_multiple() call 562 * for big endian mirrored registers which are ALSO reflecting 563 * their value in the set register when used as output. It is 564 * simply too much complexity, let the GPIO core fall back to 565 * reading each line individually in that fringe case. 566 */ 567 } else { 568 gc->get = gpio_mmio_get; 569 if (chip->be_bits) 570 gc->get_multiple = gpio_mmio_get_multiple_be; 571 else 572 gc->get_multiple = gpio_mmio_get_multiple; 573 } 574 575 return 0; 576 } 577 578 static int gpio_mmio_setup_direction(struct gpio_generic_chip *chip, 579 const struct gpio_generic_chip_config *cfg) 580 { 581 struct gpio_chip *gc = &chip->gc; 582 583 if (cfg->dirout || cfg->dirin) { 584 chip->reg_dir_out = cfg->dirout; 585 chip->reg_dir_in = cfg->dirin; 586 if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) 587 gc->direction_output = gpio_mmio_dir_out_dir_first; 588 else 589 gc->direction_output = gpio_mmio_dir_out_val_first; 590 gc->direction_input = gpio_mmio_dir_in; 591 gc->get_direction = gpio_mmio_get_dir; 592 } else { 593 if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) 594 gc->direction_output = gpio_mmio_dir_out_err; 595 else 596 gc->direction_output = gpio_mmio_simple_dir_out; 597 598 if (cfg->flags & GPIO_GENERIC_NO_INPUT) 599 gc->direction_input = gpio_mmio_dir_in_err; 600 else 601 gc->direction_input = gpio_mmio_simple_dir_in; 602 } 603 604 return 0; 605 } 606 607 static int gpio_mmio_request(struct gpio_chip *gc, unsigned int gpio_pin) 608 { 609 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 610 611 if (gpio_pin >= gc->ngpio) 612 return -EINVAL; 613 614 if (chip->pinctrl) 615 return gpiochip_generic_request(gc, gpio_pin); 616 617 return 0; 618 } 619 620 /** 621 * gpio_generic_chip_init() - Initialize a generic GPIO chip. 622 * @chip: Generic GPIO chip to set up. 623 * @cfg: Generic GPIO chip configuration. 624 * 625 * Returns 0 on success, negative error number on failure. 626 */ 627 int gpio_generic_chip_init(struct gpio_generic_chip *chip, 628 const struct gpio_generic_chip_config *cfg) 629 { 630 struct gpio_chip *gc = &chip->gc; 631 unsigned long flags = cfg->flags; 632 struct device *dev = cfg->dev; 633 int ret; 634 635 if (!is_power_of_2(cfg->sz)) 636 return -EINVAL; 637 638 chip->bits = cfg->sz * 8; 639 if (chip->bits > BITS_PER_LONG) 640 return -EINVAL; 641 642 raw_spin_lock_init(&chip->lock); 643 gc->parent = dev; 644 gc->label = dev_name(dev); 645 gc->base = -1; 646 gc->request = gpio_mmio_request; 647 chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN); 648 649 ret = gpiochip_get_ngpios(gc, dev); 650 if (ret) 651 gc->ngpio = chip->bits; 652 653 ret = gpio_mmio_setup_io(chip, cfg); 654 if (ret) 655 return ret; 656 657 ret = gpio_mmio_setup_accessors(dev, chip, 658 flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); 659 if (ret) 660 return ret; 661 662 ret = gpio_mmio_setup_direction(chip, cfg); 663 if (ret) 664 return ret; 665 666 if (flags & GPIO_GENERIC_PINCTRL_BACKEND) { 667 chip->pinctrl = true; 668 /* Currently this callback is only used for pincontrol */ 669 gc->free = gpiochip_generic_free; 670 } 671 672 chip->sdata = chip->read_reg(chip->reg_dat); 673 if (gc->set == gpio_mmio_set_set && 674 !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) 675 chip->sdata = chip->read_reg(chip->reg_set); 676 677 if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) 678 chip->dir_unreadable = true; 679 680 /* 681 * Inspect hardware to find initial direction setting. 682 */ 683 if ((chip->reg_dir_out || chip->reg_dir_in) && 684 !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { 685 if (chip->reg_dir_out) 686 chip->sdir = chip->read_reg(chip->reg_dir_out); 687 else if (chip->reg_dir_in) 688 chip->sdir = ~chip->read_reg(chip->reg_dir_in); 689 /* 690 * If we have two direction registers, synchronise 691 * input setting to output setting, the library 692 * can not handle a line being input and output at 693 * the same time. 694 */ 695 if (chip->reg_dir_out && chip->reg_dir_in) 696 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 697 } 698 699 return ret; 700 } 701 EXPORT_SYMBOL_GPL(gpio_generic_chip_init); 702 703 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 704 705 static void __iomem *gpio_mmio_map(struct platform_device *pdev, 706 const char *name, resource_size_t sane_sz) 707 { 708 struct resource *r; 709 resource_size_t sz; 710 711 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 712 if (!r) 713 return NULL; 714 715 sz = resource_size(r); 716 if (sz != sane_sz) 717 return IOMEM_ERR_PTR(-EINVAL); 718 719 return devm_ioremap_resource(&pdev->dev, r); 720 } 721 722 static const struct of_device_id gpio_mmio_of_match[] = { 723 { .compatible = "brcm,bcm6345-gpio" }, 724 { .compatible = "wd,mbl-gpio" }, 725 { .compatible = "ni,169445-nand-gpio" }, 726 { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 727 { } 728 }; 729 MODULE_DEVICE_TABLE(of, gpio_mmio_of_match); 730 731 static int gpio_mmio_pdev_probe(struct platform_device *pdev) 732 { 733 struct gpio_generic_chip_config config; 734 struct gpio_generic_chip *gen_gc; 735 struct device *dev = &pdev->dev; 736 struct resource *r; 737 void __iomem *dat; 738 void __iomem *set; 739 void __iomem *clr; 740 void __iomem *dirout; 741 void __iomem *dirin; 742 unsigned long sz; 743 unsigned long flags = 0; 744 unsigned int base; 745 int err; 746 const char *label; 747 748 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 749 if (!r) 750 return -EINVAL; 751 752 sz = resource_size(r); 753 754 dat = gpio_mmio_map(pdev, "dat", sz); 755 if (IS_ERR(dat)) 756 return PTR_ERR(dat); 757 758 set = gpio_mmio_map(pdev, "set", sz); 759 if (IS_ERR(set)) 760 return PTR_ERR(set); 761 762 clr = gpio_mmio_map(pdev, "clr", sz); 763 if (IS_ERR(clr)) 764 return PTR_ERR(clr); 765 766 dirout = gpio_mmio_map(pdev, "dirout", sz); 767 if (IS_ERR(dirout)) 768 return PTR_ERR(dirout); 769 770 dirin = gpio_mmio_map(pdev, "dirin", sz); 771 if (IS_ERR(dirin)) 772 return PTR_ERR(dirin); 773 774 gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); 775 if (!gen_gc) 776 return -ENOMEM; 777 778 if (device_is_big_endian(dev)) 779 flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 780 781 if (device_property_read_bool(dev, "no-output")) 782 flags |= GPIO_GENERIC_NO_OUTPUT; 783 784 config = (struct gpio_generic_chip_config) { 785 .dev = dev, 786 .sz = sz, 787 .dat = dat, 788 .set = set, 789 .clr = clr, 790 .dirout = dirout, 791 .dirin = dirin, 792 .flags = flags, 793 }; 794 795 err = gpio_generic_chip_init(gen_gc, &config); 796 if (err) 797 return err; 798 799 err = device_property_read_string(dev, "label", &label); 800 if (!err) 801 gen_gc->gc.label = label; 802 803 /* 804 * This property *must not* be used in device-tree sources, it's only 805 * meant to be passed to the driver from board files and MFD core. 806 */ 807 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 808 if (!err && base <= INT_MAX) 809 gen_gc->gc.base = base; 810 811 platform_set_drvdata(pdev, &gen_gc->gc); 812 813 return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL); 814 } 815 816 static const struct platform_device_id gpio_mmio_id_table[] = { 817 { 818 .name = "basic-mmio-gpio", 819 .driver_data = 0, 820 }, 821 { } 822 }; 823 MODULE_DEVICE_TABLE(platform, gpio_mmio_id_table); 824 825 static struct platform_driver gpio_mmio_driver = { 826 .driver = { 827 .name = "basic-mmio-gpio", 828 .of_match_table = gpio_mmio_of_match, 829 }, 830 .id_table = gpio_mmio_id_table, 831 .probe = gpio_mmio_pdev_probe, 832 }; 833 834 module_platform_driver(gpio_mmio_driver); 835 836 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 837 838 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 839 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 840 MODULE_LICENSE("GPL"); 841