1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Generic driver for memory-mapped GPIO controllers. 4 * 5 * Copyright 2008 MontaVista Software, Inc. 6 * Copyright 2008,2010 Anton Vorontsov <cbouatmailru@gmail.com> 7 * 8 * ....``.```~~~~````.`.`.`.`.```````'',,,.........`````......`....... 9 * ...`` ```````.. 10 * ..The simplest form of a GPIO controller that the driver supports is`` 11 * `.just a single "data" register, where GPIO state can be read and/or ` 12 * `,..written. ,,..``~~~~ .....``.`.`.~~.```.`.........``````.``````` 13 * ````````` 14 ___ 15 _/~~|___/~| . ```~~~~~~ ___/___\___ ,~.`.`.`.`````.~~...,,,,... 16 __________|~$@~~~ %~ /o*o*o*o*o*o\ .. Implementing such a GPIO . 17 o ` ~~~~\___/~~~~ ` controller in FPGA is ,.` 18 `....trivial..'~`.```.``` 19 * ``````` 20 * .```````~~~~`..`.``.``. 21 * . The driver supports `... ,..```.`~~~```````````````....````.``,, 22 * . big-endian notation, just`. .. A bit more sophisticated controllers , 23 * . register the device with -be`. .with a pair of set/clear-bit registers , 24 * `.. suffix. ```~~`````....`.` . affecting the data register and the .` 25 * ``.`.``...``` ```.. output pins are also supported.` 26 * ^^ `````.`````````.,``~``~``~~`````` 27 * . ^^ 28 * ,..`.`.`...````````````......`.`.`.`.`.`..`.`.`.. 29 * .. The expectation is that in at least some cases . ,-~~~-, 30 * .this will be used with roll-your-own ASIC/FPGA .` \ / 31 * .logic in Verilog or VHDL. ~~~`````````..`````~~` \ / 32 * ..````````......``````````` \o_ 33 * | 34 * ^^ / \ 35 * 36 * ...`````~~`.....``.`..........``````.`.``.```........``. 37 * ` 8, 16, 32 and 64 bits registers are supported, and``. 38 * . the number of GPIOs is determined by the width of ~ 39 * .. the registers. ,............```.`.`..`.`.~~~.`.`.`~ 40 * `.......````.``` 41 */ 42 43 #include <linux/bitops.h> 44 #include <linux/compiler.h> 45 #include <linux/err.h> 46 #include <linux/init.h> 47 #include <linux/io.h> 48 #include <linux/ioport.h> 49 #include <linux/log2.h> 50 #include <linux/mod_devicetable.h> 51 #include <linux/module.h> 52 #include <linux/pinctrl/consumer.h> 53 #include <linux/platform_device.h> 54 #include <linux/property.h> 55 #include <linux/slab.h> 56 #include <linux/spinlock.h> 57 #include <linux/types.h> 58 59 #include <linux/gpio/driver.h> 60 #include <linux/gpio/generic.h> 61 62 #include "gpiolib.h" 63 64 static void bgpio_write8(void __iomem *reg, unsigned long data) 65 { 66 writeb(data, reg); 67 } 68 69 static unsigned long bgpio_read8(void __iomem *reg) 70 { 71 return readb(reg); 72 } 73 74 static void bgpio_write16(void __iomem *reg, unsigned long data) 75 { 76 writew(data, reg); 77 } 78 79 static unsigned long bgpio_read16(void __iomem *reg) 80 { 81 return readw(reg); 82 } 83 84 static void bgpio_write32(void __iomem *reg, unsigned long data) 85 { 86 writel(data, reg); 87 } 88 89 static unsigned long bgpio_read32(void __iomem *reg) 90 { 91 return readl(reg); 92 } 93 94 #if BITS_PER_LONG >= 64 95 static void bgpio_write64(void __iomem *reg, unsigned long data) 96 { 97 writeq(data, reg); 98 } 99 100 static unsigned long bgpio_read64(void __iomem *reg) 101 { 102 return readq(reg); 103 } 104 #endif /* BITS_PER_LONG >= 64 */ 105 106 static void bgpio_write16be(void __iomem *reg, unsigned long data) 107 { 108 iowrite16be(data, reg); 109 } 110 111 static unsigned long bgpio_read16be(void __iomem *reg) 112 { 113 return ioread16be(reg); 114 } 115 116 static void bgpio_write32be(void __iomem *reg, unsigned long data) 117 { 118 iowrite32be(data, reg); 119 } 120 121 static unsigned long bgpio_read32be(void __iomem *reg) 122 { 123 return ioread32be(reg); 124 } 125 126 static unsigned long bgpio_line2mask(struct gpio_chip *gc, unsigned int line) 127 { 128 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 129 130 if (chip->be_bits) 131 return BIT(chip->bits - 1 - line); 132 return BIT(line); 133 } 134 135 static int bgpio_get_set(struct gpio_chip *gc, unsigned int gpio) 136 { 137 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 138 unsigned long pinmask = bgpio_line2mask(gc, gpio); 139 bool dir = !!(chip->sdir & pinmask); 140 141 if (dir) 142 return !!(chip->read_reg(chip->reg_set) & pinmask); 143 144 return !!(chip->read_reg(chip->reg_dat) & pinmask); 145 } 146 147 /* 148 * This assumes that the bits in the GPIO register are in native endianness. 149 * We only assign the function pointer if we have that. 150 */ 151 static int bgpio_get_set_multiple(struct gpio_chip *gc, unsigned long *mask, 152 unsigned long *bits) 153 { 154 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 155 unsigned long get_mask = 0, set_mask = 0; 156 157 /* Make sure we first clear any bits that are zero when we read the register */ 158 *bits &= ~*mask; 159 160 set_mask = *mask & chip->sdir; 161 get_mask = *mask & ~chip->sdir; 162 163 if (set_mask) 164 *bits |= chip->read_reg(chip->reg_set) & set_mask; 165 if (get_mask) 166 *bits |= chip->read_reg(chip->reg_dat) & get_mask; 167 168 return 0; 169 } 170 171 static int bgpio_get(struct gpio_chip *gc, unsigned int gpio) 172 { 173 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 174 175 return !!(chip->read_reg(chip->reg_dat) & bgpio_line2mask(gc, gpio)); 176 } 177 178 /* 179 * This only works if the bits in the GPIO register are in native endianness. 180 */ 181 static int bgpio_get_multiple(struct gpio_chip *gc, unsigned long *mask, 182 unsigned long *bits) 183 { 184 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 185 186 /* Make sure we first clear any bits that are zero when we read the register */ 187 *bits &= ~*mask; 188 *bits |= chip->read_reg(chip->reg_dat) & *mask; 189 return 0; 190 } 191 192 /* 193 * With big endian mirrored bit order it becomes more tedious. 194 */ 195 static int bgpio_get_multiple_be(struct gpio_chip *gc, unsigned long *mask, 196 unsigned long *bits) 197 { 198 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 199 unsigned long readmask = 0; 200 unsigned long val; 201 int bit; 202 203 /* Make sure we first clear any bits that are zero when we read the register */ 204 *bits &= ~*mask; 205 206 /* Create a mirrored mask */ 207 for_each_set_bit(bit, mask, gc->ngpio) 208 readmask |= bgpio_line2mask(gc, bit); 209 210 /* Read the register */ 211 val = chip->read_reg(chip->reg_dat) & readmask; 212 213 /* 214 * Mirror the result into the "bits" result, this will give line 0 215 * in bit 0 ... line 31 in bit 31 for a 32bit register. 216 */ 217 for_each_set_bit(bit, &val, gc->ngpio) 218 *bits |= bgpio_line2mask(gc, bit); 219 220 return 0; 221 } 222 223 static int bgpio_set_none(struct gpio_chip *gc, unsigned int gpio, int val) 224 { 225 return 0; 226 } 227 228 static int bgpio_set(struct gpio_chip *gc, unsigned int gpio, int val) 229 { 230 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 231 unsigned long mask = bgpio_line2mask(gc, gpio); 232 unsigned long flags; 233 234 raw_spin_lock_irqsave(&chip->lock, flags); 235 236 if (val) 237 chip->sdata |= mask; 238 else 239 chip->sdata &= ~mask; 240 241 chip->write_reg(chip->reg_dat, chip->sdata); 242 243 raw_spin_unlock_irqrestore(&chip->lock, flags); 244 245 return 0; 246 } 247 248 static int bgpio_set_with_clear(struct gpio_chip *gc, unsigned int gpio, 249 int val) 250 { 251 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 252 unsigned long mask = bgpio_line2mask(gc, gpio); 253 254 if (val) 255 chip->write_reg(chip->reg_set, mask); 256 else 257 chip->write_reg(chip->reg_clr, mask); 258 259 return 0; 260 } 261 262 static int bgpio_set_set(struct gpio_chip *gc, unsigned int gpio, int val) 263 { 264 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 265 unsigned long mask = bgpio_line2mask(gc, gpio), flags; 266 267 raw_spin_lock_irqsave(&chip->lock, flags); 268 269 if (val) 270 chip->sdata |= mask; 271 else 272 chip->sdata &= ~mask; 273 274 chip->write_reg(chip->reg_set, chip->sdata); 275 276 raw_spin_unlock_irqrestore(&chip->lock, flags); 277 278 return 0; 279 } 280 281 static void bgpio_multiple_get_masks(struct gpio_chip *gc, 282 unsigned long *mask, unsigned long *bits, 283 unsigned long *set_mask, 284 unsigned long *clear_mask) 285 { 286 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 287 int i; 288 289 *set_mask = 0; 290 *clear_mask = 0; 291 292 for_each_set_bit(i, mask, chip->bits) { 293 if (test_bit(i, bits)) 294 *set_mask |= bgpio_line2mask(gc, i); 295 else 296 *clear_mask |= bgpio_line2mask(gc, i); 297 } 298 } 299 300 static void bgpio_set_multiple_single_reg(struct gpio_chip *gc, 301 unsigned long *mask, 302 unsigned long *bits, 303 void __iomem *reg) 304 { 305 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 306 unsigned long flags, set_mask, clear_mask; 307 308 raw_spin_lock_irqsave(&chip->lock, flags); 309 310 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 311 312 chip->sdata |= set_mask; 313 chip->sdata &= ~clear_mask; 314 315 chip->write_reg(reg, chip->sdata); 316 317 raw_spin_unlock_irqrestore(&chip->lock, flags); 318 } 319 320 static int bgpio_set_multiple(struct gpio_chip *gc, unsigned long *mask, 321 unsigned long *bits) 322 { 323 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 324 325 bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_dat); 326 327 return 0; 328 } 329 330 static int bgpio_set_multiple_set(struct gpio_chip *gc, unsigned long *mask, 331 unsigned long *bits) 332 { 333 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 334 335 bgpio_set_multiple_single_reg(gc, mask, bits, chip->reg_set); 336 337 return 0; 338 } 339 340 static int bgpio_set_multiple_with_clear(struct gpio_chip *gc, 341 unsigned long *mask, 342 unsigned long *bits) 343 { 344 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 345 unsigned long set_mask, clear_mask; 346 347 bgpio_multiple_get_masks(gc, mask, bits, &set_mask, &clear_mask); 348 349 if (set_mask) 350 chip->write_reg(chip->reg_set, set_mask); 351 if (clear_mask) 352 chip->write_reg(chip->reg_clr, clear_mask); 353 354 return 0; 355 } 356 357 static int bgpio_dir_return(struct gpio_chip *gc, unsigned int gpio, bool dir_out) 358 { 359 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 360 361 if (!chip->pinctrl) 362 return 0; 363 364 if (dir_out) 365 return pinctrl_gpio_direction_output(gc, gpio); 366 else 367 return pinctrl_gpio_direction_input(gc, gpio); 368 } 369 370 static int bgpio_dir_in_err(struct gpio_chip *gc, unsigned int gpio) 371 { 372 return -EINVAL; 373 } 374 375 static int bgpio_simple_dir_in(struct gpio_chip *gc, unsigned int gpio) 376 { 377 return bgpio_dir_return(gc, gpio, false); 378 } 379 380 static int bgpio_dir_out_err(struct gpio_chip *gc, unsigned int gpio, 381 int val) 382 { 383 return -EINVAL; 384 } 385 386 static int bgpio_simple_dir_out(struct gpio_chip *gc, unsigned int gpio, 387 int val) 388 { 389 gc->set(gc, gpio, val); 390 391 return bgpio_dir_return(gc, gpio, true); 392 } 393 394 static int bgpio_dir_in(struct gpio_chip *gc, unsigned int gpio) 395 { 396 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 397 unsigned long flags; 398 399 raw_spin_lock_irqsave(&chip->lock, flags); 400 401 chip->sdir &= ~bgpio_line2mask(gc, gpio); 402 403 if (chip->reg_dir_in) 404 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 405 if (chip->reg_dir_out) 406 chip->write_reg(chip->reg_dir_out, chip->sdir); 407 408 raw_spin_unlock_irqrestore(&chip->lock, flags); 409 410 return bgpio_dir_return(gc, gpio, false); 411 } 412 413 static int bgpio_get_dir(struct gpio_chip *gc, unsigned int gpio) 414 { 415 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 416 417 /* Return 0 if output, 1 if input */ 418 if (chip->dir_unreadable) { 419 if (chip->sdir & bgpio_line2mask(gc, gpio)) 420 return GPIO_LINE_DIRECTION_OUT; 421 return GPIO_LINE_DIRECTION_IN; 422 } 423 424 if (chip->reg_dir_out) { 425 if (chip->read_reg(chip->reg_dir_out) & bgpio_line2mask(gc, gpio)) 426 return GPIO_LINE_DIRECTION_OUT; 427 return GPIO_LINE_DIRECTION_IN; 428 } 429 430 if (chip->reg_dir_in) 431 if (!(chip->read_reg(chip->reg_dir_in) & bgpio_line2mask(gc, gpio))) 432 return GPIO_LINE_DIRECTION_OUT; 433 434 return GPIO_LINE_DIRECTION_IN; 435 } 436 437 static void bgpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val) 438 { 439 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 440 unsigned long flags; 441 442 raw_spin_lock_irqsave(&chip->lock, flags); 443 444 chip->sdir |= bgpio_line2mask(gc, gpio); 445 446 if (chip->reg_dir_in) 447 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 448 if (chip->reg_dir_out) 449 chip->write_reg(chip->reg_dir_out, chip->sdir); 450 451 raw_spin_unlock_irqrestore(&chip->lock, flags); 452 } 453 454 static int bgpio_dir_out_dir_first(struct gpio_chip *gc, unsigned int gpio, 455 int val) 456 { 457 bgpio_dir_out(gc, gpio, val); 458 gc->set(gc, gpio, val); 459 return bgpio_dir_return(gc, gpio, true); 460 } 461 462 static int bgpio_dir_out_val_first(struct gpio_chip *gc, unsigned int gpio, 463 int val) 464 { 465 gc->set(gc, gpio, val); 466 bgpio_dir_out(gc, gpio, val); 467 return bgpio_dir_return(gc, gpio, true); 468 } 469 470 static int bgpio_setup_accessors(struct device *dev, 471 struct gpio_generic_chip *chip, 472 bool byte_be) 473 { 474 switch (chip->bits) { 475 case 8: 476 chip->read_reg = bgpio_read8; 477 chip->write_reg = bgpio_write8; 478 break; 479 case 16: 480 if (byte_be) { 481 chip->read_reg = bgpio_read16be; 482 chip->write_reg = bgpio_write16be; 483 } else { 484 chip->read_reg = bgpio_read16; 485 chip->write_reg = bgpio_write16; 486 } 487 break; 488 case 32: 489 if (byte_be) { 490 chip->read_reg = bgpio_read32be; 491 chip->write_reg = bgpio_write32be; 492 } else { 493 chip->read_reg = bgpio_read32; 494 chip->write_reg = bgpio_write32; 495 } 496 break; 497 #if BITS_PER_LONG >= 64 498 case 64: 499 if (byte_be) { 500 dev_err(dev, 501 "64 bit big endian byte order unsupported\n"); 502 return -EINVAL; 503 } else { 504 chip->read_reg = bgpio_read64; 505 chip->write_reg = bgpio_write64; 506 } 507 break; 508 #endif /* BITS_PER_LONG >= 64 */ 509 default: 510 dev_err(dev, "unsupported data width %u bits\n", chip->bits); 511 return -EINVAL; 512 } 513 514 return 0; 515 } 516 517 /* 518 * Create the device and allocate the resources. For setting GPIO's there are 519 * three supported configurations: 520 * 521 * - single input/output register resource (named "dat"). 522 * - set/clear pair (named "set" and "clr"). 523 * - single output register resource and single input resource ("set" and 524 * dat"). 525 * 526 * For the single output register, this drives a 1 by setting a bit and a zero 527 * by clearing a bit. For the set clr pair, this drives a 1 by setting a bit 528 * in the set register and clears it by setting a bit in the clear register. 529 * The configuration is detected by which resources are present. 530 * 531 * For setting the GPIO direction, there are three supported configurations: 532 * 533 * - simple bidirection GPIO that requires no configuration. 534 * - an output direction register (named "dirout") where a 1 bit 535 * indicates the GPIO is an output. 536 * - an input direction register (named "dirin") where a 1 bit indicates 537 * the GPIO is an input. 538 */ 539 static int bgpio_setup_io(struct gpio_generic_chip *chip, 540 const struct gpio_generic_chip_config *cfg) 541 { 542 struct gpio_chip *gc = &chip->gc; 543 544 chip->reg_dat = cfg->dat; 545 if (!chip->reg_dat) 546 return -EINVAL; 547 548 if (cfg->set && cfg->clr) { 549 chip->reg_set = cfg->set; 550 chip->reg_clr = cfg->clr; 551 gc->set = bgpio_set_with_clear; 552 gc->set_multiple = bgpio_set_multiple_with_clear; 553 } else if (cfg->set && !cfg->clr) { 554 chip->reg_set = cfg->set; 555 gc->set = bgpio_set_set; 556 gc->set_multiple = bgpio_set_multiple_set; 557 } else if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) { 558 gc->set = bgpio_set_none; 559 gc->set_multiple = NULL; 560 } else { 561 gc->set = bgpio_set; 562 gc->set_multiple = bgpio_set_multiple; 563 } 564 565 if (!(cfg->flags & GPIO_GENERIC_UNREADABLE_REG_SET) && 566 (cfg->flags & GPIO_GENERIC_READ_OUTPUT_REG_SET)) { 567 gc->get = bgpio_get_set; 568 if (!chip->be_bits) 569 gc->get_multiple = bgpio_get_set_multiple; 570 /* 571 * We deliberately avoid assigning the ->get_multiple() call 572 * for big endian mirrored registers which are ALSO reflecting 573 * their value in the set register when used as output. It is 574 * simply too much complexity, let the GPIO core fall back to 575 * reading each line individually in that fringe case. 576 */ 577 } else { 578 gc->get = bgpio_get; 579 if (chip->be_bits) 580 gc->get_multiple = bgpio_get_multiple_be; 581 else 582 gc->get_multiple = bgpio_get_multiple; 583 } 584 585 return 0; 586 } 587 588 static int bgpio_setup_direction(struct gpio_generic_chip *chip, 589 const struct gpio_generic_chip_config *cfg) 590 { 591 struct gpio_chip *gc = &chip->gc; 592 593 if (cfg->dirout || cfg->dirin) { 594 chip->reg_dir_out = cfg->dirout; 595 chip->reg_dir_in = cfg->dirin; 596 if (cfg->flags & GPIO_GENERIC_NO_SET_ON_INPUT) 597 gc->direction_output = bgpio_dir_out_dir_first; 598 else 599 gc->direction_output = bgpio_dir_out_val_first; 600 gc->direction_input = bgpio_dir_in; 601 gc->get_direction = bgpio_get_dir; 602 } else { 603 if (cfg->flags & GPIO_GENERIC_NO_OUTPUT) 604 gc->direction_output = bgpio_dir_out_err; 605 else 606 gc->direction_output = bgpio_simple_dir_out; 607 608 if (cfg->flags & GPIO_GENERIC_NO_INPUT) 609 gc->direction_input = bgpio_dir_in_err; 610 else 611 gc->direction_input = bgpio_simple_dir_in; 612 } 613 614 return 0; 615 } 616 617 static int bgpio_request(struct gpio_chip *gc, unsigned int gpio_pin) 618 { 619 struct gpio_generic_chip *chip = to_gpio_generic_chip(gc); 620 621 if (gpio_pin >= gc->ngpio) 622 return -EINVAL; 623 624 if (chip->pinctrl) 625 return gpiochip_generic_request(gc, gpio_pin); 626 627 return 0; 628 } 629 630 /** 631 * gpio_generic_chip_init() - Initialize a generic GPIO chip. 632 * @chip: Generic GPIO chip to set up. 633 * @cfg: Generic GPIO chip configuration. 634 * 635 * Returns 0 on success, negative error number on failure. 636 */ 637 int gpio_generic_chip_init(struct gpio_generic_chip *chip, 638 const struct gpio_generic_chip_config *cfg) 639 { 640 struct gpio_chip *gc = &chip->gc; 641 unsigned long flags = cfg->flags; 642 struct device *dev = cfg->dev; 643 int ret; 644 645 if (!is_power_of_2(cfg->sz)) 646 return -EINVAL; 647 648 chip->bits = cfg->sz * 8; 649 if (chip->bits > BITS_PER_LONG) 650 return -EINVAL; 651 652 raw_spin_lock_init(&chip->lock); 653 gc->parent = dev; 654 gc->label = dev_name(dev); 655 gc->base = -1; 656 gc->request = bgpio_request; 657 chip->be_bits = !!(flags & GPIO_GENERIC_BIG_ENDIAN); 658 659 ret = gpiochip_get_ngpios(gc, dev); 660 if (ret) 661 gc->ngpio = chip->bits; 662 663 ret = bgpio_setup_io(chip, cfg); 664 if (ret) 665 return ret; 666 667 ret = bgpio_setup_accessors(dev, chip, 668 flags & GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER); 669 if (ret) 670 return ret; 671 672 ret = bgpio_setup_direction(chip, cfg); 673 if (ret) 674 return ret; 675 676 if (flags & GPIO_GENERIC_PINCTRL_BACKEND) { 677 chip->pinctrl = true; 678 /* Currently this callback is only used for pincontrol */ 679 gc->free = gpiochip_generic_free; 680 } 681 682 chip->sdata = chip->read_reg(chip->reg_dat); 683 if (gc->set == bgpio_set_set && 684 !(flags & GPIO_GENERIC_UNREADABLE_REG_SET)) 685 chip->sdata = chip->read_reg(chip->reg_set); 686 687 if (flags & GPIO_GENERIC_UNREADABLE_REG_DIR) 688 chip->dir_unreadable = true; 689 690 /* 691 * Inspect hardware to find initial direction setting. 692 */ 693 if ((chip->reg_dir_out || chip->reg_dir_in) && 694 !(flags & GPIO_GENERIC_UNREADABLE_REG_DIR)) { 695 if (chip->reg_dir_out) 696 chip->sdir = chip->read_reg(chip->reg_dir_out); 697 else if (chip->reg_dir_in) 698 chip->sdir = ~chip->read_reg(chip->reg_dir_in); 699 /* 700 * If we have two direction registers, synchronise 701 * input setting to output setting, the library 702 * can not handle a line being input and output at 703 * the same time. 704 */ 705 if (chip->reg_dir_out && chip->reg_dir_in) 706 chip->write_reg(chip->reg_dir_in, ~chip->sdir); 707 } 708 709 return ret; 710 } 711 EXPORT_SYMBOL_GPL(gpio_generic_chip_init); 712 713 #if IS_ENABLED(CONFIG_GPIO_GENERIC_PLATFORM) 714 715 static void __iomem *bgpio_map(struct platform_device *pdev, 716 const char *name, 717 resource_size_t sane_sz) 718 { 719 struct resource *r; 720 resource_size_t sz; 721 722 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, name); 723 if (!r) 724 return NULL; 725 726 sz = resource_size(r); 727 if (sz != sane_sz) 728 return IOMEM_ERR_PTR(-EINVAL); 729 730 return devm_ioremap_resource(&pdev->dev, r); 731 } 732 733 static const struct of_device_id bgpio_of_match[] = { 734 { .compatible = "brcm,bcm6345-gpio" }, 735 { .compatible = "wd,mbl-gpio" }, 736 { .compatible = "ni,169445-nand-gpio" }, 737 { .compatible = "intel,ixp4xx-expansion-bus-mmio-gpio" }, 738 { } 739 }; 740 MODULE_DEVICE_TABLE(of, bgpio_of_match); 741 742 static int bgpio_pdev_probe(struct platform_device *pdev) 743 { 744 struct gpio_generic_chip_config config; 745 struct gpio_generic_chip *gen_gc; 746 struct device *dev = &pdev->dev; 747 struct resource *r; 748 void __iomem *dat; 749 void __iomem *set; 750 void __iomem *clr; 751 void __iomem *dirout; 752 void __iomem *dirin; 753 unsigned long sz; 754 unsigned long flags = 0; 755 unsigned int base; 756 int err; 757 const char *label; 758 759 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat"); 760 if (!r) 761 return -EINVAL; 762 763 sz = resource_size(r); 764 765 dat = bgpio_map(pdev, "dat", sz); 766 if (IS_ERR(dat)) 767 return PTR_ERR(dat); 768 769 set = bgpio_map(pdev, "set", sz); 770 if (IS_ERR(set)) 771 return PTR_ERR(set); 772 773 clr = bgpio_map(pdev, "clr", sz); 774 if (IS_ERR(clr)) 775 return PTR_ERR(clr); 776 777 dirout = bgpio_map(pdev, "dirout", sz); 778 if (IS_ERR(dirout)) 779 return PTR_ERR(dirout); 780 781 dirin = bgpio_map(pdev, "dirin", sz); 782 if (IS_ERR(dirin)) 783 return PTR_ERR(dirin); 784 785 gen_gc = devm_kzalloc(&pdev->dev, sizeof(*gen_gc), GFP_KERNEL); 786 if (!gen_gc) 787 return -ENOMEM; 788 789 if (device_is_big_endian(dev)) 790 flags |= GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 791 792 if (device_property_read_bool(dev, "no-output")) 793 flags |= GPIO_GENERIC_NO_OUTPUT; 794 795 config = (struct gpio_generic_chip_config) { 796 .dev = dev, 797 .sz = sz, 798 .dat = dat, 799 .set = set, 800 .clr = clr, 801 .dirout = dirout, 802 .dirin = dirin, 803 .flags = flags, 804 }; 805 806 err = gpio_generic_chip_init(gen_gc, &config); 807 if (err) 808 return err; 809 810 err = device_property_read_string(dev, "label", &label); 811 if (!err) 812 gen_gc->gc.label = label; 813 814 /* 815 * This property *must not* be used in device-tree sources, it's only 816 * meant to be passed to the driver from board files and MFD core. 817 */ 818 err = device_property_read_u32(dev, "gpio-mmio,base", &base); 819 if (!err && base <= INT_MAX) 820 gen_gc->gc.base = base; 821 822 platform_set_drvdata(pdev, &gen_gc->gc); 823 824 return devm_gpiochip_add_data(&pdev->dev, &gen_gc->gc, NULL); 825 } 826 827 static const struct platform_device_id bgpio_id_table[] = { 828 { 829 .name = "basic-mmio-gpio", 830 .driver_data = 0, 831 }, 832 { } 833 }; 834 MODULE_DEVICE_TABLE(platform, bgpio_id_table); 835 836 static struct platform_driver bgpio_driver = { 837 .driver = { 838 .name = "basic-mmio-gpio", 839 .of_match_table = bgpio_of_match, 840 }, 841 .id_table = bgpio_id_table, 842 .probe = bgpio_pdev_probe, 843 }; 844 845 module_platform_driver(bgpio_driver); 846 847 #endif /* CONFIG_GPIO_GENERIC_PLATFORM */ 848 849 MODULE_DESCRIPTION("Driver for basic memory-mapped GPIO controllers"); 850 MODULE_AUTHOR("Anton Vorontsov <cbouatmailru@gmail.com>"); 851 MODULE_LICENSE("GPL"); 852