xref: /linux/drivers/gpio/gpio-mm-lantiq.c (revision a36e9a1c5fa67cdc965fe011f1d04317adb35953)
15238f7bcSJohn Crispin /*
25238f7bcSJohn Crispin  *  This program is free software; you can redistribute it and/or modify it
35238f7bcSJohn Crispin  *  under the terms of the GNU General Public License version 2 as published
45238f7bcSJohn Crispin  *  by the Free Software Foundation.
55238f7bcSJohn Crispin  *
6*a36e9a1cSJohn Crispin  *  Copyright (C) 2012 John Crispin <blogic@openwrt.org>
75238f7bcSJohn Crispin  */
85238f7bcSJohn Crispin 
95238f7bcSJohn Crispin #include <linux/init.h>
10*a36e9a1cSJohn Crispin #include <linux/module.h>
115238f7bcSJohn Crispin #include <linux/types.h>
125238f7bcSJohn Crispin #include <linux/platform_device.h>
135238f7bcSJohn Crispin #include <linux/mutex.h>
145238f7bcSJohn Crispin #include <linux/gpio.h>
15*a36e9a1cSJohn Crispin #include <linux/of.h>
16*a36e9a1cSJohn Crispin #include <linux/of_gpio.h>
175238f7bcSJohn Crispin #include <linux/io.h>
18*a36e9a1cSJohn Crispin #include <linux/slab.h>
195238f7bcSJohn Crispin 
205238f7bcSJohn Crispin #include <lantiq_soc.h>
215238f7bcSJohn Crispin 
225238f7bcSJohn Crispin /*
235238f7bcSJohn Crispin  * By attaching hardware latches to the EBU it is possible to create output
245238f7bcSJohn Crispin  * only gpios. This driver configures a special memory address, which when
255238f7bcSJohn Crispin  * written to outputs 16 bit to the latches.
265238f7bcSJohn Crispin  */
275238f7bcSJohn Crispin 
285238f7bcSJohn Crispin #define LTQ_EBU_BUSCON	0x1e7ff		/* 16 bit access, slowest timing */
295238f7bcSJohn Crispin #define LTQ_EBU_WP	0x80000000	/* write protect bit */
305238f7bcSJohn Crispin 
31*a36e9a1cSJohn Crispin struct ltq_mm {
32*a36e9a1cSJohn Crispin 	struct of_mm_gpio_chip mmchip;
33*a36e9a1cSJohn Crispin 	u16 shadow;	/* shadow the latches state */
34*a36e9a1cSJohn Crispin };
355238f7bcSJohn Crispin 
36*a36e9a1cSJohn Crispin /**
37*a36e9a1cSJohn Crispin  * ltq_mm_apply() - write the shadow value to the ebu address.
38*a36e9a1cSJohn Crispin  * @chip:     Pointer to our private data structure.
39*a36e9a1cSJohn Crispin  *
40*a36e9a1cSJohn Crispin  * Write the shadow value to the EBU to set the gpios. We need to set the
41*a36e9a1cSJohn Crispin  * global EBU lock to make sure that PCI/MTD dont break.
42*a36e9a1cSJohn Crispin  */
43*a36e9a1cSJohn Crispin static void ltq_mm_apply(struct ltq_mm *chip)
445238f7bcSJohn Crispin {
455238f7bcSJohn Crispin 	unsigned long flags;
465238f7bcSJohn Crispin 
475238f7bcSJohn Crispin 	spin_lock_irqsave(&ebu_lock, flags);
485238f7bcSJohn Crispin 	ltq_ebu_w32(LTQ_EBU_BUSCON, LTQ_EBU_BUSCON1);
49*a36e9a1cSJohn Crispin 	__raw_writew(chip->shadow, chip->mmchip.regs);
505238f7bcSJohn Crispin 	ltq_ebu_w32(LTQ_EBU_BUSCON | LTQ_EBU_WP, LTQ_EBU_BUSCON1);
515238f7bcSJohn Crispin 	spin_unlock_irqrestore(&ebu_lock, flags);
525238f7bcSJohn Crispin }
535238f7bcSJohn Crispin 
54*a36e9a1cSJohn Crispin /**
55*a36e9a1cSJohn Crispin  * ltq_mm_set() - gpio_chip->set - set gpios.
56*a36e9a1cSJohn Crispin  * @gc:     Pointer to gpio_chip device structure.
57*a36e9a1cSJohn Crispin  * @gpio:   GPIO signal number.
58*a36e9a1cSJohn Crispin  * @val:    Value to be written to specified signal.
59*a36e9a1cSJohn Crispin  *
60*a36e9a1cSJohn Crispin  * Set the shadow value and call ltq_mm_apply.
61*a36e9a1cSJohn Crispin  */
62*a36e9a1cSJohn Crispin static void ltq_mm_set(struct gpio_chip *gc, unsigned offset, int value)
635238f7bcSJohn Crispin {
64*a36e9a1cSJohn Crispin 	struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
65*a36e9a1cSJohn Crispin 	struct ltq_mm *chip =
66*a36e9a1cSJohn Crispin 		container_of(mm_gc, struct ltq_mm, mmchip);
67*a36e9a1cSJohn Crispin 
685238f7bcSJohn Crispin 	if (value)
69*a36e9a1cSJohn Crispin 		chip->shadow |= (1 << offset);
705238f7bcSJohn Crispin 	else
71*a36e9a1cSJohn Crispin 		chip->shadow &= ~(1 << offset);
72*a36e9a1cSJohn Crispin 	ltq_mm_apply(chip);
735238f7bcSJohn Crispin }
745238f7bcSJohn Crispin 
75*a36e9a1cSJohn Crispin /**
76*a36e9a1cSJohn Crispin  * ltq_mm_dir_out() - gpio_chip->dir_out - set gpio direction.
77*a36e9a1cSJohn Crispin  * @gc:     Pointer to gpio_chip device structure.
78*a36e9a1cSJohn Crispin  * @gpio:   GPIO signal number.
79*a36e9a1cSJohn Crispin  * @val:    Value to be written to specified signal.
80*a36e9a1cSJohn Crispin  *
81*a36e9a1cSJohn Crispin  * Same as ltq_mm_set, always returns 0.
82*a36e9a1cSJohn Crispin  */
83*a36e9a1cSJohn Crispin static int ltq_mm_dir_out(struct gpio_chip *gc, unsigned offset, int value)
845238f7bcSJohn Crispin {
85*a36e9a1cSJohn Crispin 	ltq_mm_set(gc, offset, value);
865238f7bcSJohn Crispin 
875238f7bcSJohn Crispin 	return 0;
885238f7bcSJohn Crispin }
895238f7bcSJohn Crispin 
90*a36e9a1cSJohn Crispin /**
91*a36e9a1cSJohn Crispin  * ltq_mm_save_regs() - Set initial values of GPIO pins
92*a36e9a1cSJohn Crispin  * @mm_gc: pointer to memory mapped GPIO chip structure
93*a36e9a1cSJohn Crispin  */
94*a36e9a1cSJohn Crispin static void ltq_mm_save_regs(struct of_mm_gpio_chip *mm_gc)
955238f7bcSJohn Crispin {
96*a36e9a1cSJohn Crispin 	struct ltq_mm *chip =
97*a36e9a1cSJohn Crispin 		container_of(mm_gc, struct ltq_mm, mmchip);
98*a36e9a1cSJohn Crispin 
99*a36e9a1cSJohn Crispin 	/* tell the ebu controller which memory address we will be using */
100*a36e9a1cSJohn Crispin 	ltq_ebu_w32(CPHYSADDR(chip->mmchip.regs) | 0x1, LTQ_EBU_ADDRSEL1);
101*a36e9a1cSJohn Crispin 
102*a36e9a1cSJohn Crispin 	ltq_mm_apply(chip);
103*a36e9a1cSJohn Crispin }
104*a36e9a1cSJohn Crispin 
105*a36e9a1cSJohn Crispin static int ltq_mm_probe(struct platform_device *pdev)
106*a36e9a1cSJohn Crispin {
1075238f7bcSJohn Crispin 	struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
108*a36e9a1cSJohn Crispin 	struct ltq_mm *chip;
109*a36e9a1cSJohn Crispin 	const __be32 *shadow;
110*a36e9a1cSJohn Crispin 	int ret = 0;
1115238f7bcSJohn Crispin 
1125238f7bcSJohn Crispin 	if (!res) {
1135238f7bcSJohn Crispin 		dev_err(&pdev->dev, "failed to get memory resource\n");
1145238f7bcSJohn Crispin 		return -ENOENT;
1155238f7bcSJohn Crispin 	}
1165238f7bcSJohn Crispin 
117*a36e9a1cSJohn Crispin 	chip = kzalloc(sizeof(*chip), GFP_KERNEL);
118*a36e9a1cSJohn Crispin 	if (!chip)
1195238f7bcSJohn Crispin 		return -ENOMEM;
1205238f7bcSJohn Crispin 
121*a36e9a1cSJohn Crispin 	chip->mmchip.gc.ngpio = 16;
122*a36e9a1cSJohn Crispin 	chip->mmchip.gc.label = "gpio-mm-ltq";
123*a36e9a1cSJohn Crispin 	chip->mmchip.gc.direction_output = ltq_mm_dir_out;
124*a36e9a1cSJohn Crispin 	chip->mmchip.gc.set = ltq_mm_set;
125*a36e9a1cSJohn Crispin 	chip->mmchip.save_regs = ltq_mm_save_regs;
1265238f7bcSJohn Crispin 
127*a36e9a1cSJohn Crispin 	/* store the shadow value if one was passed by the devicetree */
128*a36e9a1cSJohn Crispin 	shadow = of_get_property(pdev->dev.of_node, "lantiq,shadow", NULL);
129*a36e9a1cSJohn Crispin 	if (shadow)
130*a36e9a1cSJohn Crispin 		chip->shadow = be32_to_cpu(*shadow);
1315238f7bcSJohn Crispin 
132*a36e9a1cSJohn Crispin 	ret = of_mm_gpiochip_add(pdev->dev.of_node, &chip->mmchip);
133*a36e9a1cSJohn Crispin 	if (ret)
134*a36e9a1cSJohn Crispin 		kfree(chip);
1355238f7bcSJohn Crispin 	return ret;
1365238f7bcSJohn Crispin }
1375238f7bcSJohn Crispin 
138*a36e9a1cSJohn Crispin static const struct of_device_id ltq_mm_match[] = {
139*a36e9a1cSJohn Crispin 	{ .compatible = "lantiq,gpio-mm" },
140*a36e9a1cSJohn Crispin 	{},
141*a36e9a1cSJohn Crispin };
142*a36e9a1cSJohn Crispin MODULE_DEVICE_TABLE(of, ltq_mm_match);
143*a36e9a1cSJohn Crispin 
144*a36e9a1cSJohn Crispin static struct platform_driver ltq_mm_driver = {
145*a36e9a1cSJohn Crispin 	.probe = ltq_mm_probe,
1465238f7bcSJohn Crispin 	.driver = {
147*a36e9a1cSJohn Crispin 		.name = "gpio-mm-ltq",
1485238f7bcSJohn Crispin 		.owner = THIS_MODULE,
149*a36e9a1cSJohn Crispin 		.of_match_table = ltq_mm_match,
1505238f7bcSJohn Crispin 	},
1515238f7bcSJohn Crispin };
1525238f7bcSJohn Crispin 
153*a36e9a1cSJohn Crispin static int __init ltq_mm_init(void)
1545238f7bcSJohn Crispin {
155*a36e9a1cSJohn Crispin 	return platform_driver_register(&ltq_mm_driver);
1565238f7bcSJohn Crispin }
1575238f7bcSJohn Crispin 
158*a36e9a1cSJohn Crispin subsys_initcall(ltq_mm_init);
159