1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/acpi.h> 4 #include <linux/bitfield.h> 5 #include <linux/bitops.h> 6 #include <linux/device.h> 7 #include <linux/gpio/driver.h> 8 #include <linux/io.h> 9 #include <linux/ioport.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm.h> 14 #include <linux/resource.h> 15 #include <linux/spinlock.h> 16 #include <linux/types.h> 17 18 /* 19 * There are 3 YU GPIO blocks: 20 * gpio[0]: HOST_GPIO0->HOST_GPIO31 21 * gpio[1]: HOST_GPIO32->HOST_GPIO63 22 * gpio[2]: HOST_GPIO64->HOST_GPIO69 23 */ 24 #define MLXBF2_GPIO_MAX_PINS_PER_BLOCK 32 25 26 /* 27 * arm_gpio_lock register: 28 * bit[31] lock status: active if set 29 * bit[15:0] set lock 30 * The lock is enabled only if 0xd42f is written to this field 31 */ 32 #define YU_ARM_GPIO_LOCK_ADDR 0x2801088 33 #define YU_ARM_GPIO_LOCK_SIZE 0x8 34 #define YU_LOCK_ACTIVE_BIT(val) (val >> 31) 35 #define YU_ARM_GPIO_LOCK_ACQUIRE 0xd42f 36 #define YU_ARM_GPIO_LOCK_RELEASE 0x0 37 38 /* 39 * gpio[x] block registers and their offset 40 */ 41 #define YU_GPIO_DATAIN 0x04 42 #define YU_GPIO_MODE1 0x08 43 #define YU_GPIO_MODE0 0x0c 44 #define YU_GPIO_DATASET 0x14 45 #define YU_GPIO_DATACLEAR 0x18 46 #define YU_GPIO_MODE1_CLEAR 0x50 47 #define YU_GPIO_MODE0_SET 0x54 48 #define YU_GPIO_MODE0_CLEAR 0x58 49 50 #ifdef CONFIG_PM 51 struct mlxbf2_gpio_context_save_regs { 52 u32 gpio_mode0; 53 u32 gpio_mode1; 54 }; 55 #endif 56 57 /* BlueField-2 gpio block context structure. */ 58 struct mlxbf2_gpio_context { 59 struct gpio_chip gc; 60 61 /* YU GPIO blocks address */ 62 void __iomem *gpio_io; 63 64 #ifdef CONFIG_PM 65 struct mlxbf2_gpio_context_save_regs *csave_regs; 66 #endif 67 }; 68 69 /* BlueField-2 gpio shared structure. */ 70 struct mlxbf2_gpio_param { 71 void __iomem *io; 72 struct resource *res; 73 struct mutex *lock; 74 }; 75 76 static struct resource yu_arm_gpio_lock_res = { 77 .start = YU_ARM_GPIO_LOCK_ADDR, 78 .end = YU_ARM_GPIO_LOCK_ADDR + YU_ARM_GPIO_LOCK_SIZE - 1, 79 .name = "YU_ARM_GPIO_LOCK", 80 }; 81 82 static DEFINE_MUTEX(yu_arm_gpio_lock_mutex); 83 84 static struct mlxbf2_gpio_param yu_arm_gpio_lock_param = { 85 .res = &yu_arm_gpio_lock_res, 86 .lock = &yu_arm_gpio_lock_mutex, 87 }; 88 89 /* Request memory region and map yu_arm_gpio_lock resource */ 90 static int mlxbf2_gpio_get_lock_res(struct platform_device *pdev) 91 { 92 struct device *dev = &pdev->dev; 93 struct resource *res; 94 resource_size_t size; 95 int ret = 0; 96 97 mutex_lock(yu_arm_gpio_lock_param.lock); 98 99 /* Check if the memory map already exists */ 100 if (yu_arm_gpio_lock_param.io) 101 goto exit; 102 103 res = yu_arm_gpio_lock_param.res; 104 size = resource_size(res); 105 106 if (!devm_request_mem_region(dev, res->start, size, res->name)) { 107 ret = -EFAULT; 108 goto exit; 109 } 110 111 yu_arm_gpio_lock_param.io = devm_ioremap(dev, res->start, size); 112 if (!yu_arm_gpio_lock_param.io) 113 ret = -ENOMEM; 114 115 exit: 116 mutex_unlock(yu_arm_gpio_lock_param.lock); 117 118 return ret; 119 } 120 121 /* 122 * Acquire the YU arm_gpio_lock to be able to change the direction 123 * mode. If the lock_active bit is already set, return an error. 124 */ 125 static int mlxbf2_gpio_lock_acquire(struct mlxbf2_gpio_context *gs) 126 { 127 u32 arm_gpio_lock_val; 128 129 mutex_lock(yu_arm_gpio_lock_param.lock); 130 spin_lock(&gs->gc.bgpio_lock); 131 132 arm_gpio_lock_val = readl(yu_arm_gpio_lock_param.io); 133 134 /* 135 * When lock active bit[31] is set, ModeX is write enabled 136 */ 137 if (YU_LOCK_ACTIVE_BIT(arm_gpio_lock_val)) { 138 spin_unlock(&gs->gc.bgpio_lock); 139 mutex_unlock(yu_arm_gpio_lock_param.lock); 140 return -EINVAL; 141 } 142 143 writel(YU_ARM_GPIO_LOCK_ACQUIRE, yu_arm_gpio_lock_param.io); 144 145 return 0; 146 } 147 148 /* 149 * Release the YU arm_gpio_lock after changing the direction mode. 150 */ 151 static void mlxbf2_gpio_lock_release(struct mlxbf2_gpio_context *gs) 152 { 153 writel(YU_ARM_GPIO_LOCK_RELEASE, yu_arm_gpio_lock_param.io); 154 spin_unlock(&gs->gc.bgpio_lock); 155 mutex_unlock(yu_arm_gpio_lock_param.lock); 156 } 157 158 /* 159 * mode0 and mode1 are both locked by the gpio_lock field. 160 * 161 * Together, mode0 and mode1 define the gpio Mode dependeing also 162 * on Reg_DataOut. 163 * 164 * {mode1,mode0}:{Reg_DataOut=0,Reg_DataOut=1}->{DataOut=0,DataOut=1} 165 * 166 * {0,0}:Reg_DataOut{0,1}->{Z,Z} Input PAD 167 * {0,1}:Reg_DataOut{0,1}->{0,1} Full drive Output PAD 168 * {1,0}:Reg_DataOut{0,1}->{0,Z} 0-set PAD to low, 1-float 169 * {1,1}:Reg_DataOut{0,1}->{Z,1} 0-float, 1-set PAD to high 170 */ 171 172 /* 173 * Set input direction: 174 * {mode1,mode0} = {0,0} 175 */ 176 static int mlxbf2_gpio_direction_input(struct gpio_chip *chip, 177 unsigned int offset) 178 { 179 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); 180 int ret; 181 182 /* 183 * Although the arm_gpio_lock was set in the probe function, check again 184 * if it is still enabled to be able to write to the ModeX registers. 185 */ 186 ret = mlxbf2_gpio_lock_acquire(gs); 187 if (ret < 0) 188 return ret; 189 190 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_CLEAR); 191 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR); 192 193 mlxbf2_gpio_lock_release(gs); 194 195 return ret; 196 } 197 198 /* 199 * Set output direction: 200 * {mode1,mode0} = {0,1} 201 */ 202 static int mlxbf2_gpio_direction_output(struct gpio_chip *chip, 203 unsigned int offset, 204 int value) 205 { 206 struct mlxbf2_gpio_context *gs = gpiochip_get_data(chip); 207 int ret = 0; 208 209 /* 210 * Although the arm_gpio_lock was set in the probe function, 211 * check again it is still enabled to be able to write to the 212 * ModeX registers. 213 */ 214 ret = mlxbf2_gpio_lock_acquire(gs); 215 if (ret < 0) 216 return ret; 217 218 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE1_CLEAR); 219 writel(BIT(offset), gs->gpio_io + YU_GPIO_MODE0_SET); 220 221 mlxbf2_gpio_lock_release(gs); 222 223 return ret; 224 } 225 226 /* BlueField-2 GPIO driver initialization routine. */ 227 static int 228 mlxbf2_gpio_probe(struct platform_device *pdev) 229 { 230 struct mlxbf2_gpio_context *gs; 231 struct device *dev = &pdev->dev; 232 struct gpio_chip *gc; 233 struct resource *res; 234 unsigned int npins; 235 int ret; 236 237 gs = devm_kzalloc(dev, sizeof(*gs), GFP_KERNEL); 238 if (!gs) 239 return -ENOMEM; 240 241 /* YU GPIO block address */ 242 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 243 if (!res) 244 return -ENODEV; 245 246 gs->gpio_io = devm_ioremap(dev, res->start, resource_size(res)); 247 if (!gs->gpio_io) 248 return -ENOMEM; 249 250 ret = mlxbf2_gpio_get_lock_res(pdev); 251 if (ret) { 252 dev_err(dev, "Failed to get yu_arm_gpio_lock resource\n"); 253 return ret; 254 } 255 256 if (device_property_read_u32(dev, "npins", &npins)) 257 npins = MLXBF2_GPIO_MAX_PINS_PER_BLOCK; 258 259 gc = &gs->gc; 260 261 ret = bgpio_init(gc, dev, 4, 262 gs->gpio_io + YU_GPIO_DATAIN, 263 gs->gpio_io + YU_GPIO_DATASET, 264 gs->gpio_io + YU_GPIO_DATACLEAR, 265 NULL, 266 NULL, 267 0); 268 269 gc->direction_input = mlxbf2_gpio_direction_input; 270 gc->direction_output = mlxbf2_gpio_direction_output; 271 gc->ngpio = npins; 272 gc->owner = THIS_MODULE; 273 274 platform_set_drvdata(pdev, gs); 275 276 ret = devm_gpiochip_add_data(dev, &gs->gc, gs); 277 if (ret) { 278 dev_err(dev, "Failed adding memory mapped gpiochip\n"); 279 return ret; 280 } 281 282 return 0; 283 } 284 285 #ifdef CONFIG_PM 286 static int mlxbf2_gpio_suspend(struct platform_device *pdev, 287 pm_message_t state) 288 { 289 struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); 290 291 gs->csave_regs->gpio_mode0 = readl(gs->gpio_io + 292 YU_GPIO_MODE0); 293 gs->csave_regs->gpio_mode1 = readl(gs->gpio_io + 294 YU_GPIO_MODE1); 295 296 return 0; 297 } 298 299 static int mlxbf2_gpio_resume(struct platform_device *pdev) 300 { 301 struct mlxbf2_gpio_context *gs = platform_get_drvdata(pdev); 302 303 writel(gs->csave_regs->gpio_mode0, gs->gpio_io + 304 YU_GPIO_MODE0); 305 writel(gs->csave_regs->gpio_mode1, gs->gpio_io + 306 YU_GPIO_MODE1); 307 308 return 0; 309 } 310 #endif 311 312 static const struct acpi_device_id mlxbf2_gpio_acpi_match[] = { 313 { "MLNXBF22", 0 }, 314 {}, 315 }; 316 MODULE_DEVICE_TABLE(acpi, mlxbf2_gpio_acpi_match); 317 318 static struct platform_driver mlxbf2_gpio_driver = { 319 .driver = { 320 .name = "mlxbf2_gpio", 321 .acpi_match_table = ACPI_PTR(mlxbf2_gpio_acpi_match), 322 }, 323 .probe = mlxbf2_gpio_probe, 324 #ifdef CONFIG_PM 325 .suspend = mlxbf2_gpio_suspend, 326 .resume = mlxbf2_gpio_resume, 327 #endif 328 }; 329 330 module_platform_driver(mlxbf2_gpio_driver); 331 332 MODULE_DESCRIPTION("Mellanox BlueField-2 GPIO Driver"); 333 MODULE_AUTHOR("Mellanox Technologies"); 334 MODULE_LICENSE("GPL v2"); 335