1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2010 OKI SEMICONDUCTOR Co., LTD. 4 */ 5 #include <linux/module.h> 6 #include <linux/kernel.h> 7 #include <linux/slab.h> 8 #include <linux/pci.h> 9 #include <linux/gpio/driver.h> 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 13 #define IOH_EDGE_FALLING 0 14 #define IOH_EDGE_RISING BIT(0) 15 #define IOH_LEVEL_L BIT(1) 16 #define IOH_LEVEL_H (BIT(0) | BIT(1)) 17 #define IOH_EDGE_BOTH BIT(2) 18 #define IOH_IM_MASK (BIT(0) | BIT(1) | BIT(2)) 19 20 #define IOH_IRQ_BASE 0 21 22 struct ioh_reg_comn { 23 u32 ien; 24 u32 istatus; 25 u32 idisp; 26 u32 iclr; 27 u32 imask; 28 u32 imaskclr; 29 u32 po; 30 u32 pi; 31 u32 pm; 32 u32 im_0; 33 u32 im_1; 34 u32 reserved; 35 }; 36 37 struct ioh_regs { 38 struct ioh_reg_comn regs[8]; 39 u32 reserve1[16]; 40 u32 ioh_sel_reg[4]; 41 u32 reserve2[11]; 42 u32 srst; 43 }; 44 45 /** 46 * struct ioh_gpio_reg_data - The register store data. 47 * @ien_reg: To store contents of interrupt enable register. 48 * @imask_reg: To store contents of interrupt mask regist 49 * @po_reg: To store contents of PO register. 50 * @pm_reg: To store contents of PM register. 51 * @im0_reg: To store contents of interrupt mode regist0 52 * @im1_reg: To store contents of interrupt mode regist1 53 * @use_sel_reg: To store contents of GPIO_USE_SEL0~3 54 */ 55 struct ioh_gpio_reg_data { 56 u32 ien_reg; 57 u32 imask_reg; 58 u32 po_reg; 59 u32 pm_reg; 60 u32 im0_reg; 61 u32 im1_reg; 62 u32 use_sel_reg; 63 }; 64 65 /** 66 * struct ioh_gpio - GPIO private data structure. 67 * @base: PCI base address of Memory mapped I/O register. 68 * @reg: Memory mapped IOH GPIO register list. 69 * @dev: Pointer to device structure. 70 * @gpio: Data for GPIO infrastructure. 71 * @ioh_gpio_reg: Memory mapped Register data is saved here 72 * when suspend. 73 * @gpio_use_sel: Save GPIO_USE_SEL1~4 register for PM 74 * @ch: Indicate GPIO channel 75 * @irq_base: Save base of IRQ number for interrupt 76 * @spinlock: Used for register access protection 77 */ 78 struct ioh_gpio { 79 void __iomem *base; 80 struct ioh_regs __iomem *reg; 81 struct device *dev; 82 struct gpio_chip gpio; 83 struct ioh_gpio_reg_data ioh_gpio_reg; 84 u32 gpio_use_sel; 85 int ch; 86 int irq_base; 87 spinlock_t spinlock; 88 }; 89 90 static const int num_ports[] = {6, 12, 16, 16, 15, 16, 16, 12}; 91 92 static int ioh_gpio_set(struct gpio_chip *gpio, unsigned int nr, int val) 93 { 94 u32 reg_val; 95 struct ioh_gpio *chip = gpiochip_get_data(gpio); 96 unsigned long flags; 97 98 spin_lock_irqsave(&chip->spinlock, flags); 99 reg_val = ioread32(&chip->reg->regs[chip->ch].po); 100 if (val) 101 reg_val |= BIT(nr); 102 else 103 reg_val &= ~BIT(nr); 104 105 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); 106 spin_unlock_irqrestore(&chip->spinlock, flags); 107 108 return 0; 109 } 110 111 static int ioh_gpio_get(struct gpio_chip *gpio, unsigned nr) 112 { 113 struct ioh_gpio *chip = gpiochip_get_data(gpio); 114 115 return !!(ioread32(&chip->reg->regs[chip->ch].pi) & BIT(nr)); 116 } 117 118 static int ioh_gpio_direction_output(struct gpio_chip *gpio, unsigned nr, 119 int val) 120 { 121 struct ioh_gpio *chip = gpiochip_get_data(gpio); 122 u32 pm; 123 u32 reg_val; 124 unsigned long flags; 125 126 spin_lock_irqsave(&chip->spinlock, flags); 127 pm = ioread32(&chip->reg->regs[chip->ch].pm); 128 pm &= BIT(num_ports[chip->ch]) - 1; 129 pm |= BIT(nr); 130 iowrite32(pm, &chip->reg->regs[chip->ch].pm); 131 132 reg_val = ioread32(&chip->reg->regs[chip->ch].po); 133 if (val) 134 reg_val |= BIT(nr); 135 else 136 reg_val &= ~BIT(nr); 137 iowrite32(reg_val, &chip->reg->regs[chip->ch].po); 138 139 spin_unlock_irqrestore(&chip->spinlock, flags); 140 141 return 0; 142 } 143 144 static int ioh_gpio_direction_input(struct gpio_chip *gpio, unsigned nr) 145 { 146 struct ioh_gpio *chip = gpiochip_get_data(gpio); 147 u32 pm; 148 unsigned long flags; 149 150 spin_lock_irqsave(&chip->spinlock, flags); 151 pm = ioread32(&chip->reg->regs[chip->ch].pm); 152 pm &= BIT(num_ports[chip->ch]) - 1; 153 pm &= ~BIT(nr); 154 iowrite32(pm, &chip->reg->regs[chip->ch].pm); 155 spin_unlock_irqrestore(&chip->spinlock, flags); 156 157 return 0; 158 } 159 160 /* 161 * Save register configuration and disable interrupts. 162 */ 163 static void __maybe_unused ioh_gpio_save_reg_conf(struct ioh_gpio *chip) 164 { 165 int i; 166 167 for (i = 0; i < 8; i ++, chip++) { 168 chip->ioh_gpio_reg.po_reg = 169 ioread32(&chip->reg->regs[chip->ch].po); 170 chip->ioh_gpio_reg.pm_reg = 171 ioread32(&chip->reg->regs[chip->ch].pm); 172 chip->ioh_gpio_reg.ien_reg = 173 ioread32(&chip->reg->regs[chip->ch].ien); 174 chip->ioh_gpio_reg.imask_reg = 175 ioread32(&chip->reg->regs[chip->ch].imask); 176 chip->ioh_gpio_reg.im0_reg = 177 ioread32(&chip->reg->regs[chip->ch].im_0); 178 chip->ioh_gpio_reg.im1_reg = 179 ioread32(&chip->reg->regs[chip->ch].im_1); 180 if (i < 4) 181 chip->ioh_gpio_reg.use_sel_reg = 182 ioread32(&chip->reg->ioh_sel_reg[i]); 183 } 184 } 185 186 /* 187 * This function restores the register configuration of the GPIO device. 188 */ 189 static void __maybe_unused ioh_gpio_restore_reg_conf(struct ioh_gpio *chip) 190 { 191 int i; 192 193 for (i = 0; i < 8; i ++, chip++) { 194 iowrite32(chip->ioh_gpio_reg.po_reg, 195 &chip->reg->regs[chip->ch].po); 196 iowrite32(chip->ioh_gpio_reg.pm_reg, 197 &chip->reg->regs[chip->ch].pm); 198 iowrite32(chip->ioh_gpio_reg.ien_reg, 199 &chip->reg->regs[chip->ch].ien); 200 iowrite32(chip->ioh_gpio_reg.imask_reg, 201 &chip->reg->regs[chip->ch].imask); 202 iowrite32(chip->ioh_gpio_reg.im0_reg, 203 &chip->reg->regs[chip->ch].im_0); 204 iowrite32(chip->ioh_gpio_reg.im1_reg, 205 &chip->reg->regs[chip->ch].im_1); 206 if (i < 4) 207 iowrite32(chip->ioh_gpio_reg.use_sel_reg, 208 &chip->reg->ioh_sel_reg[i]); 209 } 210 } 211 212 static int ioh_gpio_to_irq(struct gpio_chip *gpio, unsigned offset) 213 { 214 struct ioh_gpio *chip = gpiochip_get_data(gpio); 215 return chip->irq_base + offset; 216 } 217 218 static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port) 219 { 220 struct gpio_chip *gpio = &chip->gpio; 221 222 gpio->label = dev_name(chip->dev); 223 gpio->owner = THIS_MODULE; 224 gpio->direction_input = ioh_gpio_direction_input; 225 gpio->get = ioh_gpio_get; 226 gpio->direction_output = ioh_gpio_direction_output; 227 gpio->set = ioh_gpio_set; 228 gpio->dbg_show = NULL; 229 gpio->base = -1; 230 gpio->ngpio = num_port; 231 gpio->can_sleep = false; 232 gpio->to_irq = ioh_gpio_to_irq; 233 } 234 235 static int ioh_irq_type(struct irq_data *d, unsigned int type) 236 { 237 u32 im; 238 void __iomem *im_reg; 239 u32 ien; 240 u32 im_pos; 241 int ch; 242 unsigned long flags; 243 u32 val; 244 int irq = d->irq; 245 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 246 struct ioh_gpio *chip = gc->private; 247 248 ch = irq - chip->irq_base; 249 if (irq <= chip->irq_base + 7) { 250 im_reg = &chip->reg->regs[chip->ch].im_0; 251 im_pos = ch; 252 } else { 253 im_reg = &chip->reg->regs[chip->ch].im_1; 254 im_pos = ch - 8; 255 } 256 dev_dbg(chip->dev, "%s:irq=%d type=%d ch=%d pos=%d type=%d\n", 257 __func__, irq, type, ch, im_pos, type); 258 259 spin_lock_irqsave(&chip->spinlock, flags); 260 261 switch (type) { 262 case IRQ_TYPE_EDGE_RISING: 263 val = IOH_EDGE_RISING; 264 break; 265 case IRQ_TYPE_EDGE_FALLING: 266 val = IOH_EDGE_FALLING; 267 break; 268 case IRQ_TYPE_EDGE_BOTH: 269 val = IOH_EDGE_BOTH; 270 break; 271 case IRQ_TYPE_LEVEL_HIGH: 272 val = IOH_LEVEL_H; 273 break; 274 case IRQ_TYPE_LEVEL_LOW: 275 val = IOH_LEVEL_L; 276 break; 277 case IRQ_TYPE_PROBE: 278 goto end; 279 default: 280 dev_warn(chip->dev, "%s: unknown type(%dd)", 281 __func__, type); 282 goto end; 283 } 284 285 /* Set interrupt mode */ 286 im = ioread32(im_reg) & ~(IOH_IM_MASK << (im_pos * 4)); 287 iowrite32(im | (val << (im_pos * 4)), im_reg); 288 289 /* iclr */ 290 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr); 291 292 /* IMASKCLR */ 293 iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr); 294 295 /* Enable interrupt */ 296 ien = ioread32(&chip->reg->regs[chip->ch].ien); 297 iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien); 298 end: 299 spin_unlock_irqrestore(&chip->spinlock, flags); 300 301 return 0; 302 } 303 304 static void ioh_irq_unmask(struct irq_data *d) 305 { 306 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 307 struct ioh_gpio *chip = gc->private; 308 309 iowrite32(BIT(d->irq - chip->irq_base), 310 &chip->reg->regs[chip->ch].imaskclr); 311 } 312 313 static void ioh_irq_mask(struct irq_data *d) 314 { 315 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 316 struct ioh_gpio *chip = gc->private; 317 318 iowrite32(BIT(d->irq - chip->irq_base), 319 &chip->reg->regs[chip->ch].imask); 320 } 321 322 static void ioh_irq_disable(struct irq_data *d) 323 { 324 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 325 struct ioh_gpio *chip = gc->private; 326 unsigned long flags; 327 u32 ien; 328 329 spin_lock_irqsave(&chip->spinlock, flags); 330 ien = ioread32(&chip->reg->regs[chip->ch].ien); 331 ien &= ~BIT(d->irq - chip->irq_base); 332 iowrite32(ien, &chip->reg->regs[chip->ch].ien); 333 spin_unlock_irqrestore(&chip->spinlock, flags); 334 } 335 336 static void ioh_irq_enable(struct irq_data *d) 337 { 338 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 339 struct ioh_gpio *chip = gc->private; 340 unsigned long flags; 341 u32 ien; 342 343 spin_lock_irqsave(&chip->spinlock, flags); 344 ien = ioread32(&chip->reg->regs[chip->ch].ien); 345 ien |= BIT(d->irq - chip->irq_base); 346 iowrite32(ien, &chip->reg->regs[chip->ch].ien); 347 spin_unlock_irqrestore(&chip->spinlock, flags); 348 } 349 350 static irqreturn_t ioh_gpio_handler(int irq, void *dev_id) 351 { 352 struct ioh_gpio *chip = dev_id; 353 u32 reg_val; 354 int i, j; 355 int ret = IRQ_NONE; 356 357 for (i = 0; i < 8; i++, chip++) { 358 reg_val = ioread32(&chip->reg->regs[i].istatus); 359 for (j = 0; j < num_ports[i]; j++) { 360 if (reg_val & BIT(j)) { 361 dev_dbg(chip->dev, 362 "%s:[%d]:irq=%d status=0x%x\n", 363 __func__, j, irq, reg_val); 364 iowrite32(BIT(j), 365 &chip->reg->regs[chip->ch].iclr); 366 generic_handle_irq(chip->irq_base + j); 367 ret = IRQ_HANDLED; 368 } 369 } 370 } 371 return ret; 372 } 373 374 static int ioh_gpio_alloc_generic_chip(struct ioh_gpio *chip, 375 unsigned int irq_start, 376 unsigned int num) 377 { 378 struct irq_chip_generic *gc; 379 struct irq_chip_type *ct; 380 int rv; 381 382 gc = devm_irq_alloc_generic_chip(chip->dev, "ioh_gpio", 1, irq_start, 383 chip->base, handle_simple_irq); 384 if (!gc) 385 return -ENOMEM; 386 387 gc->private = chip; 388 ct = gc->chip_types; 389 390 ct->chip.irq_mask = ioh_irq_mask; 391 ct->chip.irq_unmask = ioh_irq_unmask; 392 ct->chip.irq_set_type = ioh_irq_type; 393 ct->chip.irq_disable = ioh_irq_disable; 394 ct->chip.irq_enable = ioh_irq_enable; 395 396 rv = devm_irq_setup_generic_chip(chip->dev, gc, IRQ_MSK(num), 397 IRQ_GC_INIT_MASK_CACHE, 398 IRQ_NOREQUEST | IRQ_NOPROBE, 0); 399 400 return rv; 401 } 402 403 static int ioh_gpio_probe(struct pci_dev *pdev, 404 const struct pci_device_id *id) 405 { 406 struct device *dev = &pdev->dev; 407 int ret; 408 int i, j; 409 struct ioh_gpio *chip; 410 void __iomem *base; 411 void *chip_save; 412 int irq_base; 413 414 ret = pcim_enable_device(pdev); 415 if (ret) { 416 dev_err(dev, "%s : pcim_enable_device failed", __func__); 417 return ret; 418 } 419 420 ret = pcim_iomap_regions(pdev, BIT(1), KBUILD_MODNAME); 421 if (ret) { 422 dev_err(dev, "pcim_iomap_regions failed-%d", ret); 423 return ret; 424 } 425 426 base = pcim_iomap_table(pdev)[1]; 427 if (!base) { 428 dev_err(dev, "%s : pcim_iomap_table failed", __func__); 429 return -ENOMEM; 430 } 431 432 chip_save = devm_kcalloc(dev, 8, sizeof(*chip), GFP_KERNEL); 433 if (chip_save == NULL) { 434 return -ENOMEM; 435 } 436 437 chip = chip_save; 438 for (i = 0; i < 8; i++, chip++) { 439 chip->dev = dev; 440 chip->base = base; 441 chip->reg = chip->base; 442 chip->ch = i; 443 spin_lock_init(&chip->spinlock); 444 ioh_gpio_setup(chip, num_ports[i]); 445 ret = devm_gpiochip_add_data(dev, &chip->gpio, chip); 446 if (ret) { 447 dev_err(dev, "IOH gpio: Failed to register GPIO\n"); 448 return ret; 449 } 450 } 451 452 chip = chip_save; 453 for (j = 0; j < 8; j++, chip++) { 454 irq_base = devm_irq_alloc_descs(dev, -1, IOH_IRQ_BASE, 455 num_ports[j], NUMA_NO_NODE); 456 if (irq_base < 0) { 457 dev_warn(dev, 458 "ml_ioh_gpio: Failed to get IRQ base num\n"); 459 return irq_base; 460 } 461 chip->irq_base = irq_base; 462 463 ret = ioh_gpio_alloc_generic_chip(chip, 464 irq_base, num_ports[j]); 465 if (ret) 466 return ret; 467 } 468 469 chip = chip_save; 470 ret = devm_request_irq(dev, pdev->irq, ioh_gpio_handler, 471 IRQF_SHARED, KBUILD_MODNAME, chip); 472 if (ret != 0) { 473 dev_err(dev, "%s request_irq failed\n", __func__); 474 return ret; 475 } 476 477 pci_set_drvdata(pdev, chip); 478 479 return 0; 480 } 481 482 static int __maybe_unused ioh_gpio_suspend(struct device *dev) 483 { 484 struct ioh_gpio *chip = dev_get_drvdata(dev); 485 unsigned long flags; 486 487 spin_lock_irqsave(&chip->spinlock, flags); 488 ioh_gpio_save_reg_conf(chip); 489 spin_unlock_irqrestore(&chip->spinlock, flags); 490 491 return 0; 492 } 493 494 static int __maybe_unused ioh_gpio_resume(struct device *dev) 495 { 496 struct ioh_gpio *chip = dev_get_drvdata(dev); 497 unsigned long flags; 498 499 spin_lock_irqsave(&chip->spinlock, flags); 500 iowrite32(0x01, &chip->reg->srst); 501 iowrite32(0x00, &chip->reg->srst); 502 ioh_gpio_restore_reg_conf(chip); 503 spin_unlock_irqrestore(&chip->spinlock, flags); 504 505 return 0; 506 } 507 508 static SIMPLE_DEV_PM_OPS(ioh_gpio_pm_ops, ioh_gpio_suspend, ioh_gpio_resume); 509 510 static const struct pci_device_id ioh_gpio_pcidev_id[] = { 511 { PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x802E) }, 512 { 0, } 513 }; 514 MODULE_DEVICE_TABLE(pci, ioh_gpio_pcidev_id); 515 516 static struct pci_driver ioh_gpio_driver = { 517 .name = "ml_ioh_gpio", 518 .id_table = ioh_gpio_pcidev_id, 519 .probe = ioh_gpio_probe, 520 .driver = { 521 .pm = &ioh_gpio_pm_ops, 522 }, 523 }; 524 525 module_pci_driver(ioh_gpio_driver); 526 527 MODULE_DESCRIPTION("OKI SEMICONDUCTOR ML-IOH series GPIO Driver"); 528 MODULE_LICENSE("GPL"); 529