1ccf6fd6dSAndy Shevchenko /* 2ccf6fd6dSAndy Shevchenko * Intel Merrifield SoC GPIO driver 3ccf6fd6dSAndy Shevchenko * 4ccf6fd6dSAndy Shevchenko * Copyright (c) 2016 Intel Corporation. 5ccf6fd6dSAndy Shevchenko * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 6ccf6fd6dSAndy Shevchenko * 7ccf6fd6dSAndy Shevchenko * This program is free software; you can redistribute it and/or modify 8ccf6fd6dSAndy Shevchenko * it under the terms of the GNU General Public License version 2 as 9ccf6fd6dSAndy Shevchenko * published by the Free Software Foundation. 10ccf6fd6dSAndy Shevchenko */ 11ccf6fd6dSAndy Shevchenko 12ccf6fd6dSAndy Shevchenko #include <linux/bitops.h> 13ccf6fd6dSAndy Shevchenko #include <linux/gpio/driver.h> 1446a5c112SAndy Shevchenko #include <linux/gpio.h> 15ccf6fd6dSAndy Shevchenko #include <linux/init.h> 16ccf6fd6dSAndy Shevchenko #include <linux/interrupt.h> 17ccf6fd6dSAndy Shevchenko #include <linux/io.h> 18ccf6fd6dSAndy Shevchenko #include <linux/module.h> 19ccf6fd6dSAndy Shevchenko #include <linux/pci.h> 20ccf6fd6dSAndy Shevchenko #include <linux/pinctrl/consumer.h> 21ccf6fd6dSAndy Shevchenko 22ccf6fd6dSAndy Shevchenko #define GCCR 0x000 /* controller configuration */ 23ccf6fd6dSAndy Shevchenko #define GPLR 0x004 /* pin level r/o */ 24ccf6fd6dSAndy Shevchenko #define GPDR 0x01c /* pin direction */ 25ccf6fd6dSAndy Shevchenko #define GPSR 0x034 /* pin set w/o */ 26ccf6fd6dSAndy Shevchenko #define GPCR 0x04c /* pin clear w/o */ 27ccf6fd6dSAndy Shevchenko #define GRER 0x064 /* rising edge detect */ 28ccf6fd6dSAndy Shevchenko #define GFER 0x07c /* falling edge detect */ 29ccf6fd6dSAndy Shevchenko #define GFBR 0x094 /* glitch filter bypass */ 30ccf6fd6dSAndy Shevchenko #define GIMR 0x0ac /* interrupt mask */ 31ccf6fd6dSAndy Shevchenko #define GISR 0x0c4 /* interrupt source */ 32ccf6fd6dSAndy Shevchenko #define GITR 0x300 /* input type */ 33ccf6fd6dSAndy Shevchenko #define GLPR 0x318 /* level input polarity */ 34ccf6fd6dSAndy Shevchenko #define GWMR 0x400 /* wake mask */ 35ccf6fd6dSAndy Shevchenko #define GWSR 0x418 /* wake source */ 36ccf6fd6dSAndy Shevchenko #define GSIR 0xc00 /* secure input */ 37ccf6fd6dSAndy Shevchenko 38ccf6fd6dSAndy Shevchenko /* Intel Merrifield has 192 GPIO pins */ 39ccf6fd6dSAndy Shevchenko #define MRFLD_NGPIO 192 40ccf6fd6dSAndy Shevchenko 41ccf6fd6dSAndy Shevchenko struct mrfld_gpio_pinrange { 42ccf6fd6dSAndy Shevchenko unsigned int gpio_base; 43ccf6fd6dSAndy Shevchenko unsigned int pin_base; 44ccf6fd6dSAndy Shevchenko unsigned int npins; 45ccf6fd6dSAndy Shevchenko }; 46ccf6fd6dSAndy Shevchenko 47ccf6fd6dSAndy Shevchenko #define GPIO_PINRANGE(gstart, gend, pstart) \ 48ccf6fd6dSAndy Shevchenko { \ 49ccf6fd6dSAndy Shevchenko .gpio_base = (gstart), \ 50ccf6fd6dSAndy Shevchenko .pin_base = (pstart), \ 51ccf6fd6dSAndy Shevchenko .npins = (gend) - (gstart) + 1, \ 52ccf6fd6dSAndy Shevchenko } 53ccf6fd6dSAndy Shevchenko 54ccf6fd6dSAndy Shevchenko struct mrfld_gpio { 55ccf6fd6dSAndy Shevchenko struct gpio_chip chip; 56ccf6fd6dSAndy Shevchenko void __iomem *reg_base; 57ccf6fd6dSAndy Shevchenko raw_spinlock_t lock; 58ccf6fd6dSAndy Shevchenko struct device *dev; 59ccf6fd6dSAndy Shevchenko }; 60ccf6fd6dSAndy Shevchenko 61ccf6fd6dSAndy Shevchenko static const struct mrfld_gpio_pinrange mrfld_gpio_ranges[] = { 62ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(0, 11, 146), 63ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(12, 13, 144), 64ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(14, 15, 35), 65ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(16, 16, 164), 66ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(17, 18, 105), 67ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(19, 22, 101), 68ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(23, 30, 107), 69ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(32, 43, 67), 70ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(44, 63, 195), 71ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(64, 67, 140), 72ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(68, 69, 165), 73ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(70, 71, 65), 74ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(72, 76, 228), 75ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(77, 86, 37), 76ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(87, 87, 48), 77ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(88, 88, 47), 78ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(89, 96, 49), 79ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(97, 97, 34), 80ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(102, 119, 83), 81ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(120, 123, 79), 82ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(124, 135, 115), 83ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(137, 142, 158), 84ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(154, 163, 24), 85ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(164, 176, 215), 86ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(177, 189, 127), 87ccf6fd6dSAndy Shevchenko GPIO_PINRANGE(190, 191, 178), 88ccf6fd6dSAndy Shevchenko }; 89ccf6fd6dSAndy Shevchenko 90ccf6fd6dSAndy Shevchenko static void __iomem *gpio_reg(struct gpio_chip *chip, unsigned int offset, 91ccf6fd6dSAndy Shevchenko unsigned int reg_type_offset) 92ccf6fd6dSAndy Shevchenko { 93ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(chip); 94ccf6fd6dSAndy Shevchenko u8 reg = offset / 32; 95ccf6fd6dSAndy Shevchenko 96ccf6fd6dSAndy Shevchenko return priv->reg_base + reg_type_offset + reg * 4; 97ccf6fd6dSAndy Shevchenko } 98ccf6fd6dSAndy Shevchenko 99ccf6fd6dSAndy Shevchenko static int mrfld_gpio_get(struct gpio_chip *chip, unsigned int offset) 100ccf6fd6dSAndy Shevchenko { 101ccf6fd6dSAndy Shevchenko void __iomem *gplr = gpio_reg(chip, offset, GPLR); 102ccf6fd6dSAndy Shevchenko 103ccf6fd6dSAndy Shevchenko return !!(readl(gplr) & BIT(offset % 32)); 104ccf6fd6dSAndy Shevchenko } 105ccf6fd6dSAndy Shevchenko 106ccf6fd6dSAndy Shevchenko static void mrfld_gpio_set(struct gpio_chip *chip, unsigned int offset, 107ccf6fd6dSAndy Shevchenko int value) 108ccf6fd6dSAndy Shevchenko { 109fcce9f14SAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(chip); 110ccf6fd6dSAndy Shevchenko void __iomem *gpsr, *gpcr; 111fcce9f14SAndy Shevchenko unsigned long flags; 112fcce9f14SAndy Shevchenko 113fcce9f14SAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 114ccf6fd6dSAndy Shevchenko 115ccf6fd6dSAndy Shevchenko if (value) { 116ccf6fd6dSAndy Shevchenko gpsr = gpio_reg(chip, offset, GPSR); 117ccf6fd6dSAndy Shevchenko writel(BIT(offset % 32), gpsr); 118ccf6fd6dSAndy Shevchenko } else { 119ccf6fd6dSAndy Shevchenko gpcr = gpio_reg(chip, offset, GPCR); 120ccf6fd6dSAndy Shevchenko writel(BIT(offset % 32), gpcr); 121ccf6fd6dSAndy Shevchenko } 122fcce9f14SAndy Shevchenko 123fcce9f14SAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 124ccf6fd6dSAndy Shevchenko } 125ccf6fd6dSAndy Shevchenko 126ccf6fd6dSAndy Shevchenko static int mrfld_gpio_direction_input(struct gpio_chip *chip, 127ccf6fd6dSAndy Shevchenko unsigned int offset) 128ccf6fd6dSAndy Shevchenko { 129ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(chip); 130ccf6fd6dSAndy Shevchenko void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 131ccf6fd6dSAndy Shevchenko unsigned long flags; 132ccf6fd6dSAndy Shevchenko u32 value; 133ccf6fd6dSAndy Shevchenko 134ccf6fd6dSAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 135ccf6fd6dSAndy Shevchenko 136ccf6fd6dSAndy Shevchenko value = readl(gpdr); 137ccf6fd6dSAndy Shevchenko value &= ~BIT(offset % 32); 138ccf6fd6dSAndy Shevchenko writel(value, gpdr); 139ccf6fd6dSAndy Shevchenko 140ccf6fd6dSAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 141ccf6fd6dSAndy Shevchenko 142ccf6fd6dSAndy Shevchenko return 0; 143ccf6fd6dSAndy Shevchenko } 144ccf6fd6dSAndy Shevchenko 145ccf6fd6dSAndy Shevchenko static int mrfld_gpio_direction_output(struct gpio_chip *chip, 146ccf6fd6dSAndy Shevchenko unsigned int offset, int value) 147ccf6fd6dSAndy Shevchenko { 148ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(chip); 149ccf6fd6dSAndy Shevchenko void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 150ccf6fd6dSAndy Shevchenko unsigned long flags; 151ccf6fd6dSAndy Shevchenko 152ccf6fd6dSAndy Shevchenko mrfld_gpio_set(chip, offset, value); 153ccf6fd6dSAndy Shevchenko 154ccf6fd6dSAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 155ccf6fd6dSAndy Shevchenko 156ccf6fd6dSAndy Shevchenko value = readl(gpdr); 157ccf6fd6dSAndy Shevchenko value |= BIT(offset % 32); 158ccf6fd6dSAndy Shevchenko writel(value, gpdr); 159ccf6fd6dSAndy Shevchenko 160ccf6fd6dSAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 161ccf6fd6dSAndy Shevchenko 162ccf6fd6dSAndy Shevchenko return 0; 163ccf6fd6dSAndy Shevchenko } 164ccf6fd6dSAndy Shevchenko 16546a5c112SAndy Shevchenko static int mrfld_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) 16646a5c112SAndy Shevchenko { 16746a5c112SAndy Shevchenko void __iomem *gpdr = gpio_reg(chip, offset, GPDR); 16846a5c112SAndy Shevchenko 16946a5c112SAndy Shevchenko return (readl(gpdr) & BIT(offset % 32)) ? GPIOF_DIR_OUT : GPIOF_DIR_IN; 17046a5c112SAndy Shevchenko } 17146a5c112SAndy Shevchenko 172e7a718f9SAndy Shevchenko static int mrfld_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset, 173e7a718f9SAndy Shevchenko unsigned int debounce) 174e7a718f9SAndy Shevchenko { 175e7a718f9SAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(chip); 176e7a718f9SAndy Shevchenko void __iomem *gfbr = gpio_reg(chip, offset, GFBR); 177e7a718f9SAndy Shevchenko unsigned long flags; 178e7a718f9SAndy Shevchenko u32 value; 179e7a718f9SAndy Shevchenko 180e7a718f9SAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 181e7a718f9SAndy Shevchenko 182e7a718f9SAndy Shevchenko if (debounce) 183e7a718f9SAndy Shevchenko value = readl(gfbr) & ~BIT(offset % 32); 184e7a718f9SAndy Shevchenko else 185e7a718f9SAndy Shevchenko value = readl(gfbr) | BIT(offset % 32); 186e7a718f9SAndy Shevchenko writel(value, gfbr); 187e7a718f9SAndy Shevchenko 188e7a718f9SAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 189e7a718f9SAndy Shevchenko 190e7a718f9SAndy Shevchenko return 0; 191e7a718f9SAndy Shevchenko } 192e7a718f9SAndy Shevchenko 193*2956b5d9SMika Westerberg static int mrfld_gpio_set_config(struct gpio_chip *chip, unsigned int offset, 194*2956b5d9SMika Westerberg unsigned long config) 195*2956b5d9SMika Westerberg { 196*2956b5d9SMika Westerberg u32 debounce; 197*2956b5d9SMika Westerberg 198*2956b5d9SMika Westerberg if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE) 199*2956b5d9SMika Westerberg return -ENOTSUPP; 200*2956b5d9SMika Westerberg 201*2956b5d9SMika Westerberg debounce = pinconf_to_config_argument(config); 202*2956b5d9SMika Westerberg return mrfld_gpio_set_debounce(chip, offset, debounce); 203*2956b5d9SMika Westerberg } 204*2956b5d9SMika Westerberg 205ccf6fd6dSAndy Shevchenko static void mrfld_irq_ack(struct irq_data *d) 206ccf6fd6dSAndy Shevchenko { 207ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); 208ccf6fd6dSAndy Shevchenko u32 gpio = irqd_to_hwirq(d); 209ccf6fd6dSAndy Shevchenko void __iomem *gisr = gpio_reg(&priv->chip, gpio, GISR); 210fcce9f14SAndy Shevchenko unsigned long flags; 211fcce9f14SAndy Shevchenko 212fcce9f14SAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 213ccf6fd6dSAndy Shevchenko 214ccf6fd6dSAndy Shevchenko writel(BIT(gpio % 32), gisr); 215fcce9f14SAndy Shevchenko 216fcce9f14SAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 217ccf6fd6dSAndy Shevchenko } 218ccf6fd6dSAndy Shevchenko 219ccf6fd6dSAndy Shevchenko static void mrfld_irq_unmask_mask(struct irq_data *d, bool unmask) 220ccf6fd6dSAndy Shevchenko { 221ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = irq_data_get_irq_chip_data(d); 222ccf6fd6dSAndy Shevchenko u32 gpio = irqd_to_hwirq(d); 223ccf6fd6dSAndy Shevchenko void __iomem *gimr = gpio_reg(&priv->chip, gpio, GIMR); 224ccf6fd6dSAndy Shevchenko unsigned long flags; 225ccf6fd6dSAndy Shevchenko u32 value; 226ccf6fd6dSAndy Shevchenko 227ccf6fd6dSAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 228ccf6fd6dSAndy Shevchenko 229ccf6fd6dSAndy Shevchenko if (unmask) 230ccf6fd6dSAndy Shevchenko value = readl(gimr) | BIT(gpio % 32); 231ccf6fd6dSAndy Shevchenko else 232ccf6fd6dSAndy Shevchenko value = readl(gimr) & ~BIT(gpio % 32); 233ccf6fd6dSAndy Shevchenko writel(value, gimr); 234ccf6fd6dSAndy Shevchenko 235ccf6fd6dSAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 236ccf6fd6dSAndy Shevchenko } 237ccf6fd6dSAndy Shevchenko 238ccf6fd6dSAndy Shevchenko static void mrfld_irq_mask(struct irq_data *d) 239ccf6fd6dSAndy Shevchenko { 240ccf6fd6dSAndy Shevchenko mrfld_irq_unmask_mask(d, false); 241ccf6fd6dSAndy Shevchenko } 242ccf6fd6dSAndy Shevchenko 243ccf6fd6dSAndy Shevchenko static void mrfld_irq_unmask(struct irq_data *d) 244ccf6fd6dSAndy Shevchenko { 245ccf6fd6dSAndy Shevchenko mrfld_irq_unmask_mask(d, true); 246ccf6fd6dSAndy Shevchenko } 247ccf6fd6dSAndy Shevchenko 248ccf6fd6dSAndy Shevchenko static int mrfld_irq_set_type(struct irq_data *d, unsigned int type) 249ccf6fd6dSAndy Shevchenko { 250ccf6fd6dSAndy Shevchenko struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 251ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(gc); 252ccf6fd6dSAndy Shevchenko u32 gpio = irqd_to_hwirq(d); 253ccf6fd6dSAndy Shevchenko void __iomem *grer = gpio_reg(&priv->chip, gpio, GRER); 254ccf6fd6dSAndy Shevchenko void __iomem *gfer = gpio_reg(&priv->chip, gpio, GFER); 255ccf6fd6dSAndy Shevchenko void __iomem *gitr = gpio_reg(&priv->chip, gpio, GITR); 256ccf6fd6dSAndy Shevchenko void __iomem *glpr = gpio_reg(&priv->chip, gpio, GLPR); 257ccf6fd6dSAndy Shevchenko unsigned long flags; 258ccf6fd6dSAndy Shevchenko u32 value; 259ccf6fd6dSAndy Shevchenko 260ccf6fd6dSAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 261ccf6fd6dSAndy Shevchenko 262ccf6fd6dSAndy Shevchenko if (type & IRQ_TYPE_EDGE_RISING) 263ccf6fd6dSAndy Shevchenko value = readl(grer) | BIT(gpio % 32); 264ccf6fd6dSAndy Shevchenko else 265ccf6fd6dSAndy Shevchenko value = readl(grer) & ~BIT(gpio % 32); 266ccf6fd6dSAndy Shevchenko writel(value, grer); 267ccf6fd6dSAndy Shevchenko 268ccf6fd6dSAndy Shevchenko if (type & IRQ_TYPE_EDGE_FALLING) 269ccf6fd6dSAndy Shevchenko value = readl(gfer) | BIT(gpio % 32); 270ccf6fd6dSAndy Shevchenko else 271ccf6fd6dSAndy Shevchenko value = readl(gfer) & ~BIT(gpio % 32); 272ccf6fd6dSAndy Shevchenko writel(value, gfer); 273ccf6fd6dSAndy Shevchenko 274ccf6fd6dSAndy Shevchenko /* 275ccf6fd6dSAndy Shevchenko * To prevent glitches from triggering an unintended level interrupt, 276ccf6fd6dSAndy Shevchenko * configure GLPR register first and then configure GITR. 277ccf6fd6dSAndy Shevchenko */ 278ccf6fd6dSAndy Shevchenko if (type & IRQ_TYPE_LEVEL_LOW) 279ccf6fd6dSAndy Shevchenko value = readl(glpr) | BIT(gpio % 32); 280ccf6fd6dSAndy Shevchenko else 281ccf6fd6dSAndy Shevchenko value = readl(glpr) & ~BIT(gpio % 32); 282ccf6fd6dSAndy Shevchenko writel(value, glpr); 283ccf6fd6dSAndy Shevchenko 284ccf6fd6dSAndy Shevchenko if (type & IRQ_TYPE_LEVEL_MASK) { 285ccf6fd6dSAndy Shevchenko value = readl(gitr) | BIT(gpio % 32); 286ccf6fd6dSAndy Shevchenko writel(value, gitr); 287ccf6fd6dSAndy Shevchenko 288ccf6fd6dSAndy Shevchenko irq_set_handler_locked(d, handle_level_irq); 289ccf6fd6dSAndy Shevchenko } else if (type & IRQ_TYPE_EDGE_BOTH) { 290ccf6fd6dSAndy Shevchenko value = readl(gitr) & ~BIT(gpio % 32); 291ccf6fd6dSAndy Shevchenko writel(value, gitr); 292ccf6fd6dSAndy Shevchenko 293ccf6fd6dSAndy Shevchenko irq_set_handler_locked(d, handle_edge_irq); 294ccf6fd6dSAndy Shevchenko } 295ccf6fd6dSAndy Shevchenko 296ccf6fd6dSAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 297ccf6fd6dSAndy Shevchenko 298ccf6fd6dSAndy Shevchenko return 0; 299ccf6fd6dSAndy Shevchenko } 300ccf6fd6dSAndy Shevchenko 301ccf6fd6dSAndy Shevchenko static int mrfld_irq_set_wake(struct irq_data *d, unsigned int on) 302ccf6fd6dSAndy Shevchenko { 303ccf6fd6dSAndy Shevchenko struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 304ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(gc); 305ccf6fd6dSAndy Shevchenko u32 gpio = irqd_to_hwirq(d); 306ccf6fd6dSAndy Shevchenko void __iomem *gwmr = gpio_reg(&priv->chip, gpio, GWMR); 307ccf6fd6dSAndy Shevchenko void __iomem *gwsr = gpio_reg(&priv->chip, gpio, GWSR); 308ccf6fd6dSAndy Shevchenko unsigned long flags; 309ccf6fd6dSAndy Shevchenko u32 value; 310ccf6fd6dSAndy Shevchenko 311ccf6fd6dSAndy Shevchenko raw_spin_lock_irqsave(&priv->lock, flags); 312ccf6fd6dSAndy Shevchenko 313ccf6fd6dSAndy Shevchenko /* Clear the existing wake status */ 314ccf6fd6dSAndy Shevchenko writel(BIT(gpio % 32), gwsr); 315ccf6fd6dSAndy Shevchenko 316ccf6fd6dSAndy Shevchenko if (on) 317ccf6fd6dSAndy Shevchenko value = readl(gwmr) | BIT(gpio % 32); 318ccf6fd6dSAndy Shevchenko else 319ccf6fd6dSAndy Shevchenko value = readl(gwmr) & ~BIT(gpio % 32); 320ccf6fd6dSAndy Shevchenko writel(value, gwmr); 321ccf6fd6dSAndy Shevchenko 322ccf6fd6dSAndy Shevchenko raw_spin_unlock_irqrestore(&priv->lock, flags); 323ccf6fd6dSAndy Shevchenko 324ccf6fd6dSAndy Shevchenko dev_dbg(priv->dev, "%sable wake for gpio %u\n", on ? "en" : "dis", gpio); 325ccf6fd6dSAndy Shevchenko return 0; 326ccf6fd6dSAndy Shevchenko } 327ccf6fd6dSAndy Shevchenko 328ccf6fd6dSAndy Shevchenko static struct irq_chip mrfld_irqchip = { 329ccf6fd6dSAndy Shevchenko .name = "gpio-merrifield", 330ccf6fd6dSAndy Shevchenko .irq_ack = mrfld_irq_ack, 331ccf6fd6dSAndy Shevchenko .irq_mask = mrfld_irq_mask, 332ccf6fd6dSAndy Shevchenko .irq_unmask = mrfld_irq_unmask, 333ccf6fd6dSAndy Shevchenko .irq_set_type = mrfld_irq_set_type, 334ccf6fd6dSAndy Shevchenko .irq_set_wake = mrfld_irq_set_wake, 335ccf6fd6dSAndy Shevchenko }; 336ccf6fd6dSAndy Shevchenko 337ccf6fd6dSAndy Shevchenko static void mrfld_irq_handler(struct irq_desc *desc) 338ccf6fd6dSAndy Shevchenko { 339ccf6fd6dSAndy Shevchenko struct gpio_chip *gc = irq_desc_get_handler_data(desc); 340ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv = gpiochip_get_data(gc); 341ccf6fd6dSAndy Shevchenko struct irq_chip *irqchip = irq_desc_get_chip(desc); 342ccf6fd6dSAndy Shevchenko unsigned long base, gpio; 343ccf6fd6dSAndy Shevchenko 344ccf6fd6dSAndy Shevchenko chained_irq_enter(irqchip, desc); 345ccf6fd6dSAndy Shevchenko 346ccf6fd6dSAndy Shevchenko /* Check GPIO controller to check which pin triggered the interrupt */ 347ccf6fd6dSAndy Shevchenko for (base = 0; base < priv->chip.ngpio; base += 32) { 348ccf6fd6dSAndy Shevchenko void __iomem *gisr = gpio_reg(&priv->chip, base, GISR); 349ccf6fd6dSAndy Shevchenko void __iomem *gimr = gpio_reg(&priv->chip, base, GIMR); 350ccf6fd6dSAndy Shevchenko unsigned long pending, enabled; 351ccf6fd6dSAndy Shevchenko 352ccf6fd6dSAndy Shevchenko pending = readl(gisr); 353ccf6fd6dSAndy Shevchenko enabled = readl(gimr); 354ccf6fd6dSAndy Shevchenko 355ccf6fd6dSAndy Shevchenko /* Only interrupts that are enabled */ 356ccf6fd6dSAndy Shevchenko pending &= enabled; 357ccf6fd6dSAndy Shevchenko 358ccf6fd6dSAndy Shevchenko for_each_set_bit(gpio, &pending, 32) { 359ccf6fd6dSAndy Shevchenko unsigned int irq; 360ccf6fd6dSAndy Shevchenko 361ccf6fd6dSAndy Shevchenko irq = irq_find_mapping(gc->irqdomain, base + gpio); 362ccf6fd6dSAndy Shevchenko generic_handle_irq(irq); 363ccf6fd6dSAndy Shevchenko } 364ccf6fd6dSAndy Shevchenko } 365ccf6fd6dSAndy Shevchenko 366ccf6fd6dSAndy Shevchenko chained_irq_exit(irqchip, desc); 367ccf6fd6dSAndy Shevchenko } 368ccf6fd6dSAndy Shevchenko 369ccf6fd6dSAndy Shevchenko static void mrfld_irq_init_hw(struct mrfld_gpio *priv) 370ccf6fd6dSAndy Shevchenko { 371ccf6fd6dSAndy Shevchenko void __iomem *reg; 372ccf6fd6dSAndy Shevchenko unsigned int base; 373ccf6fd6dSAndy Shevchenko 374ccf6fd6dSAndy Shevchenko for (base = 0; base < priv->chip.ngpio; base += 32) { 375ccf6fd6dSAndy Shevchenko /* Clear the rising-edge detect register */ 376ccf6fd6dSAndy Shevchenko reg = gpio_reg(&priv->chip, base, GRER); 377ccf6fd6dSAndy Shevchenko writel(0, reg); 378ccf6fd6dSAndy Shevchenko /* Clear the falling-edge detect register */ 379ccf6fd6dSAndy Shevchenko reg = gpio_reg(&priv->chip, base, GFER); 380ccf6fd6dSAndy Shevchenko writel(0, reg); 381ccf6fd6dSAndy Shevchenko } 382ccf6fd6dSAndy Shevchenko } 383ccf6fd6dSAndy Shevchenko 384ccf6fd6dSAndy Shevchenko static int mrfld_gpio_probe(struct pci_dev *pdev, const struct pci_device_id *id) 385ccf6fd6dSAndy Shevchenko { 386ccf6fd6dSAndy Shevchenko const struct mrfld_gpio_pinrange *range; 387ccf6fd6dSAndy Shevchenko struct mrfld_gpio *priv; 388ccf6fd6dSAndy Shevchenko u32 gpio_base, irq_base; 389ccf6fd6dSAndy Shevchenko void __iomem *base; 390ccf6fd6dSAndy Shevchenko unsigned int i; 391ccf6fd6dSAndy Shevchenko int retval; 392ccf6fd6dSAndy Shevchenko 393ccf6fd6dSAndy Shevchenko retval = pcim_enable_device(pdev); 394ccf6fd6dSAndy Shevchenko if (retval) 395ccf6fd6dSAndy Shevchenko return retval; 396ccf6fd6dSAndy Shevchenko 397ccf6fd6dSAndy Shevchenko retval = pcim_iomap_regions(pdev, BIT(1) | BIT(0), pci_name(pdev)); 398ccf6fd6dSAndy Shevchenko if (retval) { 399ccf6fd6dSAndy Shevchenko dev_err(&pdev->dev, "I/O memory mapping error\n"); 400ccf6fd6dSAndy Shevchenko return retval; 401ccf6fd6dSAndy Shevchenko } 402ccf6fd6dSAndy Shevchenko 403ccf6fd6dSAndy Shevchenko base = pcim_iomap_table(pdev)[1]; 404ccf6fd6dSAndy Shevchenko 405ccf6fd6dSAndy Shevchenko irq_base = readl(base); 406ccf6fd6dSAndy Shevchenko gpio_base = readl(sizeof(u32) + base); 407ccf6fd6dSAndy Shevchenko 408ccf6fd6dSAndy Shevchenko /* Release the IO mapping, since we already get the info from BAR1 */ 409ccf6fd6dSAndy Shevchenko pcim_iounmap_regions(pdev, BIT(1)); 410ccf6fd6dSAndy Shevchenko 411ccf6fd6dSAndy Shevchenko priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 412ccf6fd6dSAndy Shevchenko if (!priv) { 413ccf6fd6dSAndy Shevchenko dev_err(&pdev->dev, "can't allocate chip data\n"); 414ccf6fd6dSAndy Shevchenko return -ENOMEM; 415ccf6fd6dSAndy Shevchenko } 416ccf6fd6dSAndy Shevchenko 417ccf6fd6dSAndy Shevchenko priv->dev = &pdev->dev; 418ccf6fd6dSAndy Shevchenko priv->reg_base = pcim_iomap_table(pdev)[0]; 419ccf6fd6dSAndy Shevchenko 420ccf6fd6dSAndy Shevchenko priv->chip.label = dev_name(&pdev->dev); 421ccf6fd6dSAndy Shevchenko priv->chip.parent = &pdev->dev; 422ccf6fd6dSAndy Shevchenko priv->chip.request = gpiochip_generic_request; 423ccf6fd6dSAndy Shevchenko priv->chip.free = gpiochip_generic_free; 424ccf6fd6dSAndy Shevchenko priv->chip.direction_input = mrfld_gpio_direction_input; 425ccf6fd6dSAndy Shevchenko priv->chip.direction_output = mrfld_gpio_direction_output; 426ccf6fd6dSAndy Shevchenko priv->chip.get = mrfld_gpio_get; 427ccf6fd6dSAndy Shevchenko priv->chip.set = mrfld_gpio_set; 42846a5c112SAndy Shevchenko priv->chip.get_direction = mrfld_gpio_get_direction; 429*2956b5d9SMika Westerberg priv->chip.set_config = mrfld_gpio_set_config; 430ccf6fd6dSAndy Shevchenko priv->chip.base = gpio_base; 431ccf6fd6dSAndy Shevchenko priv->chip.ngpio = MRFLD_NGPIO; 432ccf6fd6dSAndy Shevchenko priv->chip.can_sleep = false; 433ccf6fd6dSAndy Shevchenko 434ccf6fd6dSAndy Shevchenko raw_spin_lock_init(&priv->lock); 435ccf6fd6dSAndy Shevchenko 436ccf6fd6dSAndy Shevchenko pci_set_drvdata(pdev, priv); 437ccf6fd6dSAndy Shevchenko retval = devm_gpiochip_add_data(&pdev->dev, &priv->chip, priv); 438ccf6fd6dSAndy Shevchenko if (retval) { 439ccf6fd6dSAndy Shevchenko dev_err(&pdev->dev, "gpiochip_add error %d\n", retval); 440ccf6fd6dSAndy Shevchenko return retval; 441ccf6fd6dSAndy Shevchenko } 442ccf6fd6dSAndy Shevchenko 443ccf6fd6dSAndy Shevchenko for (i = 0; i < ARRAY_SIZE(mrfld_gpio_ranges); i++) { 444ccf6fd6dSAndy Shevchenko range = &mrfld_gpio_ranges[i]; 445ccf6fd6dSAndy Shevchenko retval = gpiochip_add_pin_range(&priv->chip, 446ccf6fd6dSAndy Shevchenko "pinctrl-merrifield", 447ccf6fd6dSAndy Shevchenko range->gpio_base, 448ccf6fd6dSAndy Shevchenko range->pin_base, 449ccf6fd6dSAndy Shevchenko range->npins); 450ccf6fd6dSAndy Shevchenko if (retval) { 451ccf6fd6dSAndy Shevchenko dev_err(&pdev->dev, "failed to add GPIO pin range\n"); 452ccf6fd6dSAndy Shevchenko return retval; 453ccf6fd6dSAndy Shevchenko } 454ccf6fd6dSAndy Shevchenko } 455ccf6fd6dSAndy Shevchenko 456ccf6fd6dSAndy Shevchenko retval = gpiochip_irqchip_add(&priv->chip, &mrfld_irqchip, irq_base, 457e78ade0aSAndy Shevchenko handle_bad_irq, IRQ_TYPE_NONE); 458ccf6fd6dSAndy Shevchenko if (retval) { 459ccf6fd6dSAndy Shevchenko dev_err(&pdev->dev, "could not connect irqchip to gpiochip\n"); 460ccf6fd6dSAndy Shevchenko return retval; 461ccf6fd6dSAndy Shevchenko } 462ccf6fd6dSAndy Shevchenko 463ccf6fd6dSAndy Shevchenko mrfld_irq_init_hw(priv); 464ccf6fd6dSAndy Shevchenko 465ccf6fd6dSAndy Shevchenko gpiochip_set_chained_irqchip(&priv->chip, &mrfld_irqchip, pdev->irq, 466ccf6fd6dSAndy Shevchenko mrfld_irq_handler); 467ccf6fd6dSAndy Shevchenko 468ccf6fd6dSAndy Shevchenko return 0; 469ccf6fd6dSAndy Shevchenko } 470ccf6fd6dSAndy Shevchenko 471ccf6fd6dSAndy Shevchenko static const struct pci_device_id mrfld_gpio_ids[] = { 472ccf6fd6dSAndy Shevchenko { PCI_VDEVICE(INTEL, 0x1199) }, 473ccf6fd6dSAndy Shevchenko { } 474ccf6fd6dSAndy Shevchenko }; 475ccf6fd6dSAndy Shevchenko MODULE_DEVICE_TABLE(pci, mrfld_gpio_ids); 476ccf6fd6dSAndy Shevchenko 477ccf6fd6dSAndy Shevchenko static struct pci_driver mrfld_gpio_driver = { 478ccf6fd6dSAndy Shevchenko .name = "gpio-merrifield", 479ccf6fd6dSAndy Shevchenko .id_table = mrfld_gpio_ids, 480ccf6fd6dSAndy Shevchenko .probe = mrfld_gpio_probe, 481ccf6fd6dSAndy Shevchenko }; 482ccf6fd6dSAndy Shevchenko 483ccf6fd6dSAndy Shevchenko module_pci_driver(mrfld_gpio_driver); 484ccf6fd6dSAndy Shevchenko 485ccf6fd6dSAndy Shevchenko MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>"); 486ccf6fd6dSAndy Shevchenko MODULE_DESCRIPTION("Intel Merrifield SoC GPIO driver"); 487ccf6fd6dSAndy Shevchenko MODULE_LICENSE("GPL v2"); 488