1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/drivers/gpio/gpio-mb86s7x.c 4 * 5 * Copyright (C) 2015 Fujitsu Semiconductor Limited 6 * Copyright (C) 2015 Linaro Ltd. 7 */ 8 9 #include <linux/io.h> 10 #include <linux/init.h> 11 #include <linux/clk.h> 12 #include <linux/module.h> 13 #include <linux/err.h> 14 #include <linux/errno.h> 15 #include <linux/ioport.h> 16 #include <linux/of_device.h> 17 #include <linux/gpio/driver.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <linux/slab.h> 21 22 /* 23 * Only first 8bits of a register correspond to each pin, 24 * so there are 4 registers for 32 pins. 25 */ 26 #define PDR(x) (0x0 + x / 8 * 4) 27 #define DDR(x) (0x10 + x / 8 * 4) 28 #define PFR(x) (0x20 + x / 8 * 4) 29 30 #define OFFSET(x) BIT((x) % 8) 31 32 struct mb86s70_gpio_chip { 33 struct gpio_chip gc; 34 void __iomem *base; 35 struct clk *clk; 36 spinlock_t lock; 37 }; 38 39 static int mb86s70_gpio_request(struct gpio_chip *gc, unsigned gpio) 40 { 41 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 42 unsigned long flags; 43 u32 val; 44 45 spin_lock_irqsave(&gchip->lock, flags); 46 47 val = readl(gchip->base + PFR(gpio)); 48 val &= ~OFFSET(gpio); 49 writel(val, gchip->base + PFR(gpio)); 50 51 spin_unlock_irqrestore(&gchip->lock, flags); 52 53 return 0; 54 } 55 56 static void mb86s70_gpio_free(struct gpio_chip *gc, unsigned gpio) 57 { 58 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 59 unsigned long flags; 60 u32 val; 61 62 spin_lock_irqsave(&gchip->lock, flags); 63 64 val = readl(gchip->base + PFR(gpio)); 65 val |= OFFSET(gpio); 66 writel(val, gchip->base + PFR(gpio)); 67 68 spin_unlock_irqrestore(&gchip->lock, flags); 69 } 70 71 static int mb86s70_gpio_direction_input(struct gpio_chip *gc, unsigned gpio) 72 { 73 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 74 unsigned long flags; 75 unsigned char val; 76 77 spin_lock_irqsave(&gchip->lock, flags); 78 79 val = readl(gchip->base + DDR(gpio)); 80 val &= ~OFFSET(gpio); 81 writel(val, gchip->base + DDR(gpio)); 82 83 spin_unlock_irqrestore(&gchip->lock, flags); 84 85 return 0; 86 } 87 88 static int mb86s70_gpio_direction_output(struct gpio_chip *gc, 89 unsigned gpio, int value) 90 { 91 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 92 unsigned long flags; 93 unsigned char val; 94 95 spin_lock_irqsave(&gchip->lock, flags); 96 97 val = readl(gchip->base + PDR(gpio)); 98 if (value) 99 val |= OFFSET(gpio); 100 else 101 val &= ~OFFSET(gpio); 102 writel(val, gchip->base + PDR(gpio)); 103 104 val = readl(gchip->base + DDR(gpio)); 105 val |= OFFSET(gpio); 106 writel(val, gchip->base + DDR(gpio)); 107 108 spin_unlock_irqrestore(&gchip->lock, flags); 109 110 return 0; 111 } 112 113 static int mb86s70_gpio_get(struct gpio_chip *gc, unsigned gpio) 114 { 115 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 116 117 return !!(readl(gchip->base + PDR(gpio)) & OFFSET(gpio)); 118 } 119 120 static void mb86s70_gpio_set(struct gpio_chip *gc, unsigned gpio, int value) 121 { 122 struct mb86s70_gpio_chip *gchip = gpiochip_get_data(gc); 123 unsigned long flags; 124 unsigned char val; 125 126 spin_lock_irqsave(&gchip->lock, flags); 127 128 val = readl(gchip->base + PDR(gpio)); 129 if (value) 130 val |= OFFSET(gpio); 131 else 132 val &= ~OFFSET(gpio); 133 writel(val, gchip->base + PDR(gpio)); 134 135 spin_unlock_irqrestore(&gchip->lock, flags); 136 } 137 138 static int mb86s70_gpio_probe(struct platform_device *pdev) 139 { 140 struct mb86s70_gpio_chip *gchip; 141 int ret; 142 143 gchip = devm_kzalloc(&pdev->dev, sizeof(*gchip), GFP_KERNEL); 144 if (gchip == NULL) 145 return -ENOMEM; 146 147 platform_set_drvdata(pdev, gchip); 148 149 gchip->base = devm_platform_ioremap_resource(pdev, 0); 150 if (IS_ERR(gchip->base)) 151 return PTR_ERR(gchip->base); 152 153 gchip->clk = devm_clk_get(&pdev->dev, NULL); 154 if (IS_ERR(gchip->clk)) 155 return PTR_ERR(gchip->clk); 156 157 ret = clk_prepare_enable(gchip->clk); 158 if (ret) 159 return ret; 160 161 spin_lock_init(&gchip->lock); 162 163 gchip->gc.direction_output = mb86s70_gpio_direction_output; 164 gchip->gc.direction_input = mb86s70_gpio_direction_input; 165 gchip->gc.request = mb86s70_gpio_request; 166 gchip->gc.free = mb86s70_gpio_free; 167 gchip->gc.get = mb86s70_gpio_get; 168 gchip->gc.set = mb86s70_gpio_set; 169 gchip->gc.label = dev_name(&pdev->dev); 170 gchip->gc.ngpio = 32; 171 gchip->gc.owner = THIS_MODULE; 172 gchip->gc.parent = &pdev->dev; 173 gchip->gc.base = -1; 174 175 ret = gpiochip_add_data(&gchip->gc, gchip); 176 if (ret) { 177 dev_err(&pdev->dev, "couldn't register gpio driver\n"); 178 clk_disable_unprepare(gchip->clk); 179 } 180 181 return ret; 182 } 183 184 static int mb86s70_gpio_remove(struct platform_device *pdev) 185 { 186 struct mb86s70_gpio_chip *gchip = platform_get_drvdata(pdev); 187 188 gpiochip_remove(&gchip->gc); 189 clk_disable_unprepare(gchip->clk); 190 191 return 0; 192 } 193 194 static const struct of_device_id mb86s70_gpio_dt_ids[] = { 195 { .compatible = "fujitsu,mb86s70-gpio" }, 196 { /* sentinel */ } 197 }; 198 MODULE_DEVICE_TABLE(of, mb86s70_gpio_dt_ids); 199 200 static struct platform_driver mb86s70_gpio_driver = { 201 .driver = { 202 .name = "mb86s70-gpio", 203 .of_match_table = mb86s70_gpio_dt_ids, 204 }, 205 .probe = mb86s70_gpio_probe, 206 .remove = mb86s70_gpio_remove, 207 }; 208 module_platform_driver(mb86s70_gpio_driver); 209 210 MODULE_DESCRIPTION("MB86S7x GPIO Driver"); 211 MODULE_ALIAS("platform:mb86s70-gpio"); 212 MODULE_LICENSE("GPL"); 213