1 // SPDX-License-Identifier: GPL-2.0-only 2 // 3 // Copyright 2020 Google Inc 4 // Copyright 2025 Linaro Ltd. 5 // 6 // GPIO driver for Maxim MAX77759 7 8 #include <linux/dev_printk.h> 9 #include <linux/device.h> 10 #include <linux/device/driver.h> 11 #include <linux/gpio/driver.h> 12 #include <linux/interrupt.h> 13 #include <linux/irq.h> 14 #include <linux/irqreturn.h> 15 #include <linux/lockdep.h> 16 #include <linux/mfd/max77759.h> 17 #include <linux/module.h> 18 #include <linux/overflow.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 #include <linux/seq_file.h> 22 23 #define MAX77759_N_GPIOS ARRAY_SIZE(max77759_gpio_line_names) 24 static const char * const max77759_gpio_line_names[] = { "GPIO5", "GPIO6" }; 25 26 struct max77759_gpio_chip { 27 struct regmap *map; 28 struct max77759 *max77759; 29 struct gpio_chip gc; 30 struct mutex maxq_lock; /* protect MaxQ r/m/w operations */ 31 32 struct mutex irq_lock; /* protect irq bus */ 33 int irq_mask; 34 int irq_mask_changed; 35 int irq_trig; 36 int irq_trig_changed; 37 }; 38 39 #define MAX77759_GPIOx_TRIGGER(offs, val) (((val) & 1) << (offs)) 40 #define MAX77759_GPIOx_TRIGGER_MASK(offs) MAX77759_GPIOx_TRIGGER(offs, ~0) 41 enum max77759_trigger_gpio_type { 42 MAX77759_GPIO_TRIGGER_RISING = 0, 43 MAX77759_GPIO_TRIGGER_FALLING = 1 44 }; 45 46 #define MAX77759_GPIOx_DIR(offs, dir) (((dir) & 1) << (2 + (3 * (offs)))) 47 #define MAX77759_GPIOx_DIR_MASK(offs) MAX77759_GPIOx_DIR(offs, ~0) 48 enum max77759_control_gpio_dir { 49 MAX77759_GPIO_DIR_IN = 0, 50 MAX77759_GPIO_DIR_OUT = 1 51 }; 52 53 #define MAX77759_GPIOx_OUTVAL(offs, val) (((val) & 1) << (3 + (3 * (offs)))) 54 #define MAX77759_GPIOx_OUTVAL_MASK(offs) MAX77759_GPIOx_OUTVAL(offs, ~0) 55 56 #define MAX77759_GPIOx_INVAL_MASK(offs) (BIT(4) << (3 * (offs))) 57 58 static int max77759_gpio_maxq_gpio_trigger_read(struct max77759_gpio_chip *chip) 59 { 60 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1); 61 DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2); 62 int ret; 63 64 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_READ; 65 66 ret = max77759_maxq_command(chip->max77759, cmd, rsp); 67 if (ret < 0) 68 return ret; 69 70 return rsp->rsp[1]; 71 } 72 73 static int max77759_gpio_maxq_gpio_trigger_write(struct max77759_gpio_chip *chip, 74 u8 trigger) 75 { 76 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2); 77 78 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_TRIGGER_WRITE; 79 cmd->cmd[1] = trigger; 80 81 return max77759_maxq_command(chip->max77759, cmd, NULL); 82 } 83 84 static int max77759_gpio_maxq_gpio_control_read(struct max77759_gpio_chip *chip) 85 { 86 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 1); 87 DEFINE_FLEX(struct max77759_maxq_response, rsp, rsp, length, 2); 88 int ret; 89 90 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_CONTROL_READ; 91 92 ret = max77759_maxq_command(chip->max77759, cmd, rsp); 93 if (ret < 0) 94 return ret; 95 96 return rsp->rsp[1]; 97 } 98 99 static int max77759_gpio_maxq_gpio_control_write(struct max77759_gpio_chip *chip, 100 u8 ctrl) 101 { 102 DEFINE_FLEX(struct max77759_maxq_command, cmd, cmd, length, 2); 103 104 cmd->cmd[0] = MAX77759_MAXQ_OPCODE_GPIO_CONTROL_WRITE; 105 cmd->cmd[1] = ctrl; 106 107 return max77759_maxq_command(chip->max77759, cmd, NULL); 108 } 109 110 static int 111 max77759_gpio_direction_from_control(int ctrl, unsigned int offset) 112 { 113 enum max77759_control_gpio_dir dir; 114 115 dir = !!(ctrl & MAX77759_GPIOx_DIR_MASK(offset)); 116 return ((dir == MAX77759_GPIO_DIR_OUT) 117 ? GPIO_LINE_DIRECTION_OUT 118 : GPIO_LINE_DIRECTION_IN); 119 } 120 121 static int max77759_gpio_get_direction(struct gpio_chip *gc, 122 unsigned int offset) 123 { 124 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 125 int ctrl; 126 127 ctrl = max77759_gpio_maxq_gpio_control_read(chip); 128 if (ctrl < 0) 129 return ctrl; 130 131 return max77759_gpio_direction_from_control(ctrl, offset); 132 } 133 134 static int max77759_gpio_direction_helper(struct gpio_chip *gc, 135 unsigned int offset, 136 enum max77759_control_gpio_dir dir, 137 int value) 138 { 139 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 140 int ctrl, new_ctrl; 141 142 guard(mutex)(&chip->maxq_lock); 143 144 ctrl = max77759_gpio_maxq_gpio_control_read(chip); 145 if (ctrl < 0) 146 return ctrl; 147 148 new_ctrl = ctrl & ~MAX77759_GPIOx_DIR_MASK(offset); 149 new_ctrl |= MAX77759_GPIOx_DIR(offset, dir); 150 151 if (dir == MAX77759_GPIO_DIR_OUT) { 152 new_ctrl &= ~MAX77759_GPIOx_OUTVAL_MASK(offset); 153 new_ctrl |= MAX77759_GPIOx_OUTVAL(offset, value); 154 } 155 156 if (new_ctrl == ctrl) 157 return 0; 158 159 return max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); 160 } 161 162 static int max77759_gpio_direction_input(struct gpio_chip *gc, 163 unsigned int offset) 164 { 165 return max77759_gpio_direction_helper(gc, offset, 166 MAX77759_GPIO_DIR_IN, -1); 167 } 168 169 static int max77759_gpio_direction_output(struct gpio_chip *gc, 170 unsigned int offset, int value) 171 { 172 return max77759_gpio_direction_helper(gc, offset, 173 MAX77759_GPIO_DIR_OUT, value); 174 } 175 176 static int max77759_gpio_get_value(struct gpio_chip *gc, unsigned int offset) 177 { 178 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 179 int ctrl, mask; 180 181 ctrl = max77759_gpio_maxq_gpio_control_read(chip); 182 if (ctrl < 0) 183 return ctrl; 184 185 /* 186 * The input status bit doesn't reflect the pin state when the GPIO is 187 * configured as an output. Check the direction, and inspect the input 188 * or output bit accordingly. 189 */ 190 mask = ((max77759_gpio_direction_from_control(ctrl, offset) 191 == GPIO_LINE_DIRECTION_IN) 192 ? MAX77759_GPIOx_INVAL_MASK(offset) 193 : MAX77759_GPIOx_OUTVAL_MASK(offset)); 194 195 return !!(ctrl & mask); 196 } 197 198 static int max77759_gpio_set_value(struct gpio_chip *gc, 199 unsigned int offset, int value) 200 { 201 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 202 int ctrl, new_ctrl; 203 204 guard(mutex)(&chip->maxq_lock); 205 206 ctrl = max77759_gpio_maxq_gpio_control_read(chip); 207 if (ctrl < 0) 208 return ctrl; 209 210 new_ctrl = ctrl & ~MAX77759_GPIOx_OUTVAL_MASK(offset); 211 new_ctrl |= MAX77759_GPIOx_OUTVAL(offset, value); 212 213 if (new_ctrl == ctrl) 214 return 0; 215 216 return max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); 217 } 218 219 static void max77759_gpio_irq_mask(struct irq_data *d) 220 { 221 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 222 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 223 irq_hw_number_t hwirq = irqd_to_hwirq(d); 224 225 chip->irq_mask &= ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq); 226 chip->irq_mask |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); 227 chip->irq_mask_changed |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); 228 229 gpiochip_disable_irq(gc, hwirq); 230 } 231 232 static void max77759_gpio_irq_unmask(struct irq_data *d) 233 { 234 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 235 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 236 irq_hw_number_t hwirq = irqd_to_hwirq(d); 237 238 gpiochip_enable_irq(gc, hwirq); 239 240 chip->irq_mask &= ~MAX77759_MAXQ_REG_UIC_INT1_GPIOxI_MASK(hwirq); 241 chip->irq_mask |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 0); 242 chip->irq_mask_changed |= MAX77759_MAXQ_REG_UIC_INT1_GPIOxI(hwirq, 1); 243 } 244 245 static int max77759_gpio_set_irq_type(struct irq_data *d, unsigned int type) 246 { 247 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 248 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 249 irq_hw_number_t hwirq = irqd_to_hwirq(d); 250 251 chip->irq_trig &= ~MAX77759_GPIOx_TRIGGER_MASK(hwirq); 252 switch (type) { 253 case IRQ_TYPE_EDGE_RISING: 254 chip->irq_trig |= MAX77759_GPIOx_TRIGGER(hwirq, 255 MAX77759_GPIO_TRIGGER_RISING); 256 break; 257 258 case IRQ_TYPE_EDGE_FALLING: 259 chip->irq_trig |= MAX77759_GPIOx_TRIGGER(hwirq, 260 MAX77759_GPIO_TRIGGER_FALLING); 261 break; 262 263 default: 264 return -EINVAL; 265 } 266 267 chip->irq_trig_changed |= MAX77759_GPIOx_TRIGGER(hwirq, 1); 268 269 return 0; 270 } 271 272 static void max77759_gpio_bus_lock(struct irq_data *d) 273 { 274 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 275 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 276 277 mutex_lock(&chip->irq_lock); 278 } 279 280 static int max77759_gpio_bus_sync_unlock_helper(struct gpio_chip *gc, 281 struct max77759_gpio_chip *chip) 282 __must_hold(&chip->maxq_lock) 283 { 284 int ctrl, trigger, new_trigger, new_ctrl; 285 unsigned long irq_trig_changed; 286 int offset; 287 int ret; 288 289 lockdep_assert_held(&chip->maxq_lock); 290 291 ctrl = max77759_gpio_maxq_gpio_control_read(chip); 292 trigger = max77759_gpio_maxq_gpio_trigger_read(chip); 293 if (ctrl < 0 || trigger < 0) { 294 dev_err(gc->parent, "failed to read current state: %d / %d\n", 295 ctrl, trigger); 296 return (ctrl < 0) ? ctrl : trigger; 297 } 298 299 new_trigger = trigger & ~chip->irq_trig_changed; 300 new_trigger |= (chip->irq_trig & chip->irq_trig_changed); 301 302 /* change GPIO direction if required */ 303 new_ctrl = ctrl; 304 irq_trig_changed = chip->irq_trig_changed; 305 for_each_set_bit(offset, &irq_trig_changed, MAX77759_N_GPIOS) { 306 new_ctrl &= ~MAX77759_GPIOx_DIR_MASK(offset); 307 new_ctrl |= MAX77759_GPIOx_DIR(offset, MAX77759_GPIO_DIR_IN); 308 } 309 310 if (new_trigger != trigger) { 311 ret = max77759_gpio_maxq_gpio_trigger_write(chip, new_trigger); 312 if (ret) { 313 dev_err(gc->parent, 314 "failed to write new trigger: %d\n", ret); 315 return ret; 316 } 317 } 318 319 if (new_ctrl != ctrl) { 320 ret = max77759_gpio_maxq_gpio_control_write(chip, new_ctrl); 321 if (ret) { 322 dev_err(gc->parent, 323 "failed to write new control: %d\n", ret); 324 return ret; 325 } 326 } 327 328 chip->irq_trig_changed = 0; 329 330 return 0; 331 } 332 333 static void max77759_gpio_bus_sync_unlock(struct irq_data *d) 334 { 335 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 336 struct max77759_gpio_chip *chip = gpiochip_get_data(gc); 337 int ret; 338 339 scoped_guard(mutex, &chip->maxq_lock) { 340 ret = max77759_gpio_bus_sync_unlock_helper(gc, chip); 341 if (ret) 342 goto out_unlock; 343 } 344 345 ret = regmap_update_bits(chip->map, 346 MAX77759_MAXQ_REG_UIC_INT1_M, 347 chip->irq_mask_changed, chip->irq_mask); 348 if (ret) { 349 dev_err(gc->parent, 350 "failed to update UIC_INT1 irq mask: %d\n", ret); 351 goto out_unlock; 352 } 353 354 chip->irq_mask_changed = 0; 355 356 out_unlock: 357 mutex_unlock(&chip->irq_lock); 358 } 359 360 static void max77759_gpio_irq_print_chip(struct irq_data *d, struct seq_file *p) 361 { 362 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 363 364 seq_puts(p, dev_name(gc->parent)); 365 } 366 367 static const struct irq_chip max77759_gpio_irq_chip = { 368 .irq_mask = max77759_gpio_irq_mask, 369 .irq_unmask = max77759_gpio_irq_unmask, 370 .irq_set_type = max77759_gpio_set_irq_type, 371 .irq_bus_lock = max77759_gpio_bus_lock, 372 .irq_bus_sync_unlock = max77759_gpio_bus_sync_unlock, 373 .irq_print_chip = max77759_gpio_irq_print_chip, 374 .flags = IRQCHIP_IMMUTABLE, 375 GPIOCHIP_IRQ_RESOURCE_HELPERS, 376 }; 377 378 static irqreturn_t max77759_gpio_irqhandler(int irq, void *data) 379 { 380 struct max77759_gpio_chip *chip = data; 381 struct gpio_chip *gc = &chip->gc; 382 bool handled = false; 383 384 /* iterate until no interrupt is pending */ 385 while (true) { 386 unsigned int uic_int1; 387 int ret; 388 unsigned long pending; 389 int offset; 390 391 ret = regmap_read(chip->map, MAX77759_MAXQ_REG_UIC_INT1, 392 &uic_int1); 393 if (ret < 0) { 394 dev_err_ratelimited(gc->parent, 395 "failed to read IRQ status: %d\n", 396 ret); 397 /* 398 * If !handled, we have looped not even once, which 399 * means we should return IRQ_NONE in that case (and 400 * of course IRQ_HANDLED otherwise). 401 */ 402 return IRQ_RETVAL(handled); 403 } 404 405 pending = uic_int1; 406 pending &= (MAX77759_MAXQ_REG_UIC_INT1_GPIO6I 407 | MAX77759_MAXQ_REG_UIC_INT1_GPIO5I); 408 if (!pending) 409 break; 410 411 for_each_set_bit(offset, &pending, MAX77759_N_GPIOS) { 412 /* 413 * ACK interrupt by writing 1 to bit 'offset', all 414 * others need to be written as 0. This needs to be 415 * done unconditionally hence regmap_set_bits() is 416 * inappropriate here. 417 */ 418 regmap_write(chip->map, MAX77759_MAXQ_REG_UIC_INT1, 419 BIT(offset)); 420 421 handle_nested_irq(irq_find_mapping(gc->irq.domain, 422 offset)); 423 424 handled = true; 425 } 426 } 427 428 return IRQ_RETVAL(handled); 429 } 430 431 static int max77759_gpio_probe(struct platform_device *pdev) 432 { 433 struct max77759_gpio_chip *chip; 434 int irq; 435 struct gpio_irq_chip *girq; 436 int ret; 437 438 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 439 if (!chip) 440 return -ENOMEM; 441 442 chip->map = dev_get_regmap(pdev->dev.parent, "maxq"); 443 if (!chip->map) 444 return dev_err_probe(&pdev->dev, -ENODEV, "Missing regmap\n"); 445 446 irq = platform_get_irq_byname(pdev, "GPI"); 447 if (irq < 0) 448 return dev_err_probe(&pdev->dev, irq, "Failed to get IRQ\n"); 449 450 chip->max77759 = dev_get_drvdata(pdev->dev.parent); 451 ret = devm_mutex_init(&pdev->dev, &chip->maxq_lock); 452 if (ret) 453 return ret; 454 ret = devm_mutex_init(&pdev->dev, &chip->irq_lock); 455 if (ret) 456 return ret; 457 458 chip->gc.base = -1; 459 chip->gc.label = dev_name(&pdev->dev); 460 chip->gc.parent = &pdev->dev; 461 chip->gc.can_sleep = true; 462 463 chip->gc.names = max77759_gpio_line_names; 464 chip->gc.ngpio = MAX77759_N_GPIOS; 465 chip->gc.get_direction = max77759_gpio_get_direction; 466 chip->gc.direction_input = max77759_gpio_direction_input; 467 chip->gc.direction_output = max77759_gpio_direction_output; 468 chip->gc.get = max77759_gpio_get_value; 469 chip->gc.set = max77759_gpio_set_value; 470 471 girq = &chip->gc.irq; 472 gpio_irq_chip_set_chip(girq, &max77759_gpio_irq_chip); 473 /* This will let us handle the parent IRQ in the driver */ 474 girq->parent_handler = NULL; 475 girq->num_parents = 0; 476 girq->parents = NULL; 477 girq->default_type = IRQ_TYPE_NONE; 478 girq->handler = handle_simple_irq; 479 girq->threaded = true; 480 481 ret = devm_gpiochip_add_data(&pdev->dev, &chip->gc, chip); 482 if (ret < 0) 483 return dev_err_probe(&pdev->dev, ret, 484 "Failed to add GPIO chip\n"); 485 486 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 487 max77759_gpio_irqhandler, 488 IRQF_ONESHOT | IRQF_SHARED, 489 dev_name(&pdev->dev), chip); 490 if (ret < 0) 491 return dev_err_probe(&pdev->dev, ret, 492 "Failed to request IRQ\n"); 493 494 return ret; 495 } 496 497 static const struct of_device_id max77759_gpio_of_id[] = { 498 { .compatible = "maxim,max77759-gpio", }, 499 { } 500 }; 501 MODULE_DEVICE_TABLE(of, max77759_gpio_of_id); 502 503 static const struct platform_device_id max77759_gpio_platform_id[] = { 504 { .name = "max77759-gpio" }, 505 { } 506 }; 507 MODULE_DEVICE_TABLE(platform, max77759_gpio_platform_id); 508 509 static struct platform_driver max77759_gpio_driver = { 510 .driver = { 511 .name = "max77759-gpio", 512 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 513 .of_match_table = max77759_gpio_of_id, 514 }, 515 .probe = max77759_gpio_probe, 516 .id_table = max77759_gpio_platform_id, 517 }; 518 519 module_platform_driver(max77759_gpio_driver); 520 521 MODULE_AUTHOR("André Draszik <andre.draszik@linaro.org>"); 522 MODULE_DESCRIPTION("GPIO driver for Maxim MAX77759"); 523 MODULE_LICENSE("GPL"); 524