1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // IXP4 GPIO driver 4 // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org> 5 // 6 // based on previous work and know-how from: 7 // Deepak Saxena <dsaxena@plexity.net> 8 9 #include <linux/bitops.h> 10 #include <linux/gpio/driver.h> 11 #include <linux/gpio/generic.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqdomain.h> 15 #include <linux/irqchip.h> 16 #include <linux/of_irq.h> 17 #include <linux/platform_device.h> 18 #include <linux/property.h> 19 20 #define IXP4XX_REG_GPOUT 0x00 21 #define IXP4XX_REG_GPOE 0x04 22 #define IXP4XX_REG_GPIN 0x08 23 #define IXP4XX_REG_GPIS 0x0C 24 #define IXP4XX_REG_GPIT1 0x10 25 #define IXP4XX_REG_GPIT2 0x14 26 #define IXP4XX_REG_GPCLK 0x18 27 #define IXP4XX_REG_GPDBSEL 0x1C 28 29 /* 30 * The hardware uses 3 bits to indicate interrupt "style". 31 * we clear and set these three bits accordingly. The lower 24 32 * bits in two registers (GPIT1 and GPIT2) are used to set up 33 * the style for 8 lines each for a total of 16 GPIO lines. 34 */ 35 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0 36 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1 37 #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2 38 #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3 39 #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4 40 #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) 41 #define IXP4XX_GPIO_STYLE_SIZE 3 42 43 /* 44 * Clock output control register defines. 45 */ 46 #define IXP4XX_GPCLK_CLK0DC_SHIFT 0 47 #define IXP4XX_GPCLK_CLK0TC_SHIFT 4 48 #define IXP4XX_GPCLK_CLK0_MASK GENMASK(7, 0) 49 #define IXP4XX_GPCLK_MUX14 BIT(8) 50 #define IXP4XX_GPCLK_CLK1DC_SHIFT 16 51 #define IXP4XX_GPCLK_CLK1TC_SHIFT 20 52 #define IXP4XX_GPCLK_CLK1_MASK GENMASK(23, 16) 53 #define IXP4XX_GPCLK_MUX15 BIT(24) 54 55 /** 56 * struct ixp4xx_gpio - IXP4 GPIO state container 57 * @chip: generic GPIO chip for this instance 58 * @dev: containing device for this instance 59 * @base: remapped I/O-memory base 60 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, 61 * 0: level triggered 62 */ 63 struct ixp4xx_gpio { 64 struct gpio_generic_chip chip; 65 struct device *dev; 66 void __iomem *base; 67 unsigned long long irq_edge; 68 }; 69 70 static void ixp4xx_gpio_irq_ack(struct irq_data *d) 71 { 72 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 73 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 74 75 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); 76 } 77 78 static void ixp4xx_gpio_mask_irq(struct irq_data *d) 79 { 80 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 81 82 irq_chip_mask_parent(d); 83 gpiochip_disable_irq(gc, d->hwirq); 84 } 85 86 static void ixp4xx_gpio_irq_unmask(struct irq_data *d) 87 { 88 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 89 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 90 91 /* ACK when unmasking if not edge-triggered */ 92 if (!(g->irq_edge & BIT(d->hwirq))) 93 ixp4xx_gpio_irq_ack(d); 94 95 gpiochip_enable_irq(gc, d->hwirq); 96 irq_chip_unmask_parent(d); 97 } 98 99 static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type) 100 { 101 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 102 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 103 int line = d->hwirq; 104 u32 int_style; 105 u32 int_reg; 106 u32 val; 107 108 switch (type) { 109 case IRQ_TYPE_EDGE_BOTH: 110 irq_set_handler_locked(d, handle_edge_irq); 111 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; 112 g->irq_edge |= BIT(d->hwirq); 113 break; 114 case IRQ_TYPE_EDGE_RISING: 115 irq_set_handler_locked(d, handle_edge_irq); 116 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; 117 g->irq_edge |= BIT(d->hwirq); 118 break; 119 case IRQ_TYPE_EDGE_FALLING: 120 irq_set_handler_locked(d, handle_edge_irq); 121 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; 122 g->irq_edge |= BIT(d->hwirq); 123 break; 124 case IRQ_TYPE_LEVEL_HIGH: 125 irq_set_handler_locked(d, handle_level_irq); 126 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; 127 g->irq_edge &= ~BIT(d->hwirq); 128 break; 129 case IRQ_TYPE_LEVEL_LOW: 130 irq_set_handler_locked(d, handle_level_irq); 131 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; 132 g->irq_edge &= ~BIT(d->hwirq); 133 break; 134 default: 135 return -EINVAL; 136 } 137 138 if (line >= 8) { 139 /* pins 8-15 */ 140 line -= 8; 141 int_reg = IXP4XX_REG_GPIT2; 142 } else { 143 /* pins 0-7 */ 144 int_reg = IXP4XX_REG_GPIT1; 145 } 146 147 scoped_guard(gpio_generic_lock_irqsave, &g->chip) { 148 /* Clear the style for the appropriate pin */ 149 val = __raw_readl(g->base + int_reg); 150 val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); 151 __raw_writel(val, g->base + int_reg); 152 153 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); 154 155 /* Set the new style */ 156 val = __raw_readl(g->base + int_reg); 157 val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); 158 __raw_writel(val, g->base + int_reg); 159 160 /* Force-configure this line as an input */ 161 val = __raw_readl(g->base + IXP4XX_REG_GPOE); 162 val |= BIT(d->hwirq); 163 __raw_writel(val, g->base + IXP4XX_REG_GPOE); 164 } 165 166 /* This parent only accept level high (asserted) */ 167 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 168 } 169 170 static const struct irq_chip ixp4xx_gpio_irqchip = { 171 .name = "IXP4GPIO", 172 .irq_ack = ixp4xx_gpio_irq_ack, 173 .irq_mask = ixp4xx_gpio_mask_irq, 174 .irq_unmask = ixp4xx_gpio_irq_unmask, 175 .irq_set_type = ixp4xx_gpio_irq_set_type, 176 .flags = IRQCHIP_IMMUTABLE, 177 GPIOCHIP_IRQ_RESOURCE_HELPERS, 178 }; 179 180 static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 181 unsigned int child, 182 unsigned int child_type, 183 unsigned int *parent, 184 unsigned int *parent_type) 185 { 186 /* All these interrupts are level high in the CPU */ 187 *parent_type = IRQ_TYPE_LEVEL_HIGH; 188 189 /* GPIO lines 0..12 have dedicated IRQs */ 190 if (child == 0) { 191 *parent = 6; 192 return 0; 193 } 194 if (child == 1) { 195 *parent = 7; 196 return 0; 197 } 198 if (child >= 2 && child <= 12) { 199 *parent = child + 17; 200 return 0; 201 } 202 return -EINVAL; 203 } 204 205 static int ixp4xx_gpio_probe(struct platform_device *pdev) 206 { 207 struct gpio_generic_chip_config config; 208 unsigned long flags; 209 struct device *dev = &pdev->dev; 210 struct device_node *np = dev->of_node; 211 struct irq_domain *parent; 212 struct ixp4xx_gpio *g; 213 struct gpio_irq_chip *girq; 214 struct device_node *irq_parent; 215 bool clk_14, clk_15; 216 u32 val; 217 int ret; 218 219 g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); 220 if (!g) 221 return -ENOMEM; 222 g->dev = dev; 223 224 g->base = devm_platform_ioremap_resource(pdev, 0); 225 if (IS_ERR(g->base)) 226 return PTR_ERR(g->base); 227 228 irq_parent = of_irq_find_parent(np); 229 if (!irq_parent) { 230 dev_err(dev, "no IRQ parent node\n"); 231 return -ENODEV; 232 } 233 parent = irq_find_host(irq_parent); 234 if (!parent) { 235 dev_err(dev, "no IRQ parent domain\n"); 236 return -ENODEV; 237 } 238 239 /* 240 * If either clock output is enabled explicitly in the device tree 241 * we take full control of the clock by masking off all bits for 242 * the clock control and selectively enabling them. Otherwise 243 * we leave the hardware default settings. 244 * 245 * Enable clock outputs with default timings of requested clock. 246 * If you need control over TC and DC, add these to the device 247 * tree bindings and use them here. 248 */ 249 clk_14 = of_property_read_bool(np, "intel,ixp4xx-gpio14-clkout"); 250 clk_15 = of_property_read_bool(np, "intel,ixp4xx-gpio15-clkout"); 251 252 /* 253 * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on 254 * specific machines. 255 */ 256 if (of_machine_is_compatible("dlink,dsm-g600-a") || 257 of_machine_is_compatible("iom,nas-100d")) 258 val = 0; 259 else { 260 val = __raw_readl(g->base + IXP4XX_REG_GPCLK); 261 262 if (clk_14 || clk_15) { 263 val &= ~(IXP4XX_GPCLK_MUX14 | IXP4XX_GPCLK_MUX15); 264 val &= ~IXP4XX_GPCLK_CLK0_MASK; 265 val &= ~IXP4XX_GPCLK_CLK1_MASK; 266 if (clk_14) { 267 /* IXP4XX_GPCLK_CLK0DC implicit low */ 268 val |= (1 << IXP4XX_GPCLK_CLK0TC_SHIFT); 269 val |= IXP4XX_GPCLK_MUX14; 270 } 271 272 if (clk_15) { 273 /* IXP4XX_GPCLK_CLK1DC implicit low */ 274 val |= (1 << IXP4XX_GPCLK_CLK1TC_SHIFT); 275 val |= IXP4XX_GPCLK_MUX15; 276 } 277 } 278 } 279 280 __raw_writel(val, g->base + IXP4XX_REG_GPCLK); 281 282 /* 283 * This is a very special big-endian ARM issue: when the IXP4xx is 284 * run in big endian mode, all registers in the machine are switched 285 * around to the CPU-native endianness. As you see mostly in the 286 * driver we use __raw_readl()/__raw_writel() to access the registers 287 * in the appropriate order. With the GPIO library we need to specify 288 * byte order explicitly, so this flag needs to be set when compiling 289 * for big endian. 290 */ 291 #if defined(CONFIG_CPU_BIG_ENDIAN) 292 flags = GPIO_GENERIC_BIG_ENDIAN_BYTE_ORDER; 293 #else 294 flags = 0; 295 #endif 296 297 config = (struct gpio_generic_chip_config) { 298 .dev = dev, 299 .sz = 4, 300 .dat = g->base + IXP4XX_REG_GPIN, 301 .set = g->base + IXP4XX_REG_GPOUT, 302 .dirin = g->base + IXP4XX_REG_GPOE, 303 .flags = flags, 304 }; 305 306 /* Populate and register gpio chip */ 307 ret = gpio_generic_chip_init(&g->chip, &config); 308 if (ret) { 309 dev_err(dev, "unable to init generic GPIO\n"); 310 return ret; 311 } 312 g->chip.gc.ngpio = 16; 313 g->chip.gc.label = "IXP4XX_GPIO_CHIP"; 314 /* 315 * TODO: when we have migrated to device tree and all GPIOs 316 * are fetched using phandles, set this to -1 to get rid of 317 * the fixed gpiochip base. 318 */ 319 g->chip.gc.base = 0; 320 g->chip.gc.parent = &pdev->dev; 321 g->chip.gc.owner = THIS_MODULE; 322 323 girq = &g->chip.gc.irq; 324 gpio_irq_chip_set_chip(girq, &ixp4xx_gpio_irqchip); 325 girq->fwnode = dev_fwnode(dev); 326 girq->parent_domain = parent; 327 girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq; 328 girq->handler = handle_bad_irq; 329 girq->default_type = IRQ_TYPE_NONE; 330 331 ret = devm_gpiochip_add_data(dev, &g->chip.gc, g); 332 if (ret) { 333 dev_err(dev, "failed to add SoC gpiochip\n"); 334 return ret; 335 } 336 337 platform_set_drvdata(pdev, g); 338 dev_info(dev, "IXP4 GPIO registered\n"); 339 340 return 0; 341 } 342 343 static const struct of_device_id ixp4xx_gpio_of_match[] = { 344 { 345 .compatible = "intel,ixp4xx-gpio", 346 }, 347 {}, 348 }; 349 350 351 static struct platform_driver ixp4xx_gpio_driver = { 352 .driver = { 353 .name = "ixp4xx-gpio", 354 .of_match_table = ixp4xx_gpio_of_match, 355 }, 356 .probe = ixp4xx_gpio_probe, 357 }; 358 builtin_platform_driver(ixp4xx_gpio_driver); 359