1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // IXP4 GPIO driver 4 // Copyright (C) 2019 Linus Walleij <linus.walleij@linaro.org> 5 // 6 // based on previous work and know-how from: 7 // Deepak Saxena <dsaxena@plexity.net> 8 9 #include <linux/gpio/driver.h> 10 #include <linux/io.h> 11 #include <linux/irq.h> 12 #include <linux/irqdomain.h> 13 #include <linux/irqchip.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/bitops.h> 17 /* Include that go away with DT transition */ 18 #include <linux/irqchip/irq-ixp4xx.h> 19 20 #define IXP4XX_REG_GPOUT 0x00 21 #define IXP4XX_REG_GPOE 0x04 22 #define IXP4XX_REG_GPIN 0x08 23 #define IXP4XX_REG_GPIS 0x0C 24 #define IXP4XX_REG_GPIT1 0x10 25 #define IXP4XX_REG_GPIT2 0x14 26 #define IXP4XX_REG_GPCLK 0x18 27 #define IXP4XX_REG_GPDBSEL 0x1C 28 29 /* 30 * The hardware uses 3 bits to indicate interrupt "style". 31 * we clear and set these three bits accordingly. The lower 24 32 * bits in two registers (GPIT1 and GPIT2) are used to set up 33 * the style for 8 lines each for a total of 16 GPIO lines. 34 */ 35 #define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0 36 #define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1 37 #define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2 38 #define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3 39 #define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4 40 #define IXP4XX_GPIO_STYLE_MASK GENMASK(2, 0) 41 #define IXP4XX_GPIO_STYLE_SIZE 3 42 43 /** 44 * struct ixp4xx_gpio - IXP4 GPIO state container 45 * @dev: containing device for this instance 46 * @fwnode: the fwnode for this GPIO chip 47 * @gc: gpiochip for this instance 48 * @base: remapped I/O-memory base 49 * @irq_edge: Each bit represents an IRQ: 1: edge-triggered, 50 * 0: level triggered 51 */ 52 struct ixp4xx_gpio { 53 struct device *dev; 54 struct fwnode_handle *fwnode; 55 struct gpio_chip gc; 56 void __iomem *base; 57 unsigned long long irq_edge; 58 }; 59 60 static void ixp4xx_gpio_irq_ack(struct irq_data *d) 61 { 62 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 63 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 64 65 __raw_writel(BIT(d->hwirq), g->base + IXP4XX_REG_GPIS); 66 } 67 68 static void ixp4xx_gpio_irq_unmask(struct irq_data *d) 69 { 70 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 71 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 72 73 /* ACK when unmasking if not edge-triggered */ 74 if (!(g->irq_edge & BIT(d->hwirq))) 75 ixp4xx_gpio_irq_ack(d); 76 77 irq_chip_unmask_parent(d); 78 } 79 80 static int ixp4xx_gpio_irq_set_type(struct irq_data *d, unsigned int type) 81 { 82 struct gpio_chip *gc = irq_data_get_irq_chip_data(d); 83 struct ixp4xx_gpio *g = gpiochip_get_data(gc); 84 int line = d->hwirq; 85 unsigned long flags; 86 u32 int_style; 87 u32 int_reg; 88 u32 val; 89 90 switch (type) { 91 case IRQ_TYPE_EDGE_BOTH: 92 irq_set_handler_locked(d, handle_edge_irq); 93 int_style = IXP4XX_GPIO_STYLE_TRANSITIONAL; 94 g->irq_edge |= BIT(d->hwirq); 95 break; 96 case IRQ_TYPE_EDGE_RISING: 97 irq_set_handler_locked(d, handle_edge_irq); 98 int_style = IXP4XX_GPIO_STYLE_RISING_EDGE; 99 g->irq_edge |= BIT(d->hwirq); 100 break; 101 case IRQ_TYPE_EDGE_FALLING: 102 irq_set_handler_locked(d, handle_edge_irq); 103 int_style = IXP4XX_GPIO_STYLE_FALLING_EDGE; 104 g->irq_edge |= BIT(d->hwirq); 105 break; 106 case IRQ_TYPE_LEVEL_HIGH: 107 irq_set_handler_locked(d, handle_level_irq); 108 int_style = IXP4XX_GPIO_STYLE_ACTIVE_HIGH; 109 g->irq_edge &= ~BIT(d->hwirq); 110 break; 111 case IRQ_TYPE_LEVEL_LOW: 112 irq_set_handler_locked(d, handle_level_irq); 113 int_style = IXP4XX_GPIO_STYLE_ACTIVE_LOW; 114 g->irq_edge &= ~BIT(d->hwirq); 115 break; 116 default: 117 return -EINVAL; 118 } 119 120 if (line >= 8) { 121 /* pins 8-15 */ 122 line -= 8; 123 int_reg = IXP4XX_REG_GPIT2; 124 } else { 125 /* pins 0-7 */ 126 int_reg = IXP4XX_REG_GPIT1; 127 } 128 129 raw_spin_lock_irqsave(&g->gc.bgpio_lock, flags); 130 131 /* Clear the style for the appropriate pin */ 132 val = __raw_readl(g->base + int_reg); 133 val &= ~(IXP4XX_GPIO_STYLE_MASK << (line * IXP4XX_GPIO_STYLE_SIZE)); 134 __raw_writel(val, g->base + int_reg); 135 136 __raw_writel(BIT(line), g->base + IXP4XX_REG_GPIS); 137 138 /* Set the new style */ 139 val = __raw_readl(g->base + int_reg); 140 val |= (int_style << (line * IXP4XX_GPIO_STYLE_SIZE)); 141 __raw_writel(val, g->base + int_reg); 142 143 /* Force-configure this line as an input */ 144 val = __raw_readl(g->base + IXP4XX_REG_GPOE); 145 val |= BIT(d->hwirq); 146 __raw_writel(val, g->base + IXP4XX_REG_GPOE); 147 148 raw_spin_unlock_irqrestore(&g->gc.bgpio_lock, flags); 149 150 /* This parent only accept level high (asserted) */ 151 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 152 } 153 154 static struct irq_chip ixp4xx_gpio_irqchip = { 155 .name = "IXP4GPIO", 156 .irq_ack = ixp4xx_gpio_irq_ack, 157 .irq_mask = irq_chip_mask_parent, 158 .irq_unmask = ixp4xx_gpio_irq_unmask, 159 .irq_set_type = ixp4xx_gpio_irq_set_type, 160 }; 161 162 static int ixp4xx_gpio_child_to_parent_hwirq(struct gpio_chip *gc, 163 unsigned int child, 164 unsigned int child_type, 165 unsigned int *parent, 166 unsigned int *parent_type) 167 { 168 /* All these interrupts are level high in the CPU */ 169 *parent_type = IRQ_TYPE_LEVEL_HIGH; 170 171 /* GPIO lines 0..12 have dedicated IRQs */ 172 if (child == 0) { 173 *parent = 6; 174 return 0; 175 } 176 if (child == 1) { 177 *parent = 7; 178 return 0; 179 } 180 if (child >= 2 && child <= 12) { 181 *parent = child + 17; 182 return 0; 183 } 184 return -EINVAL; 185 } 186 187 static int ixp4xx_gpio_probe(struct platform_device *pdev) 188 { 189 unsigned long flags; 190 struct device *dev = &pdev->dev; 191 struct device_node *np = dev->of_node; 192 struct irq_domain *parent; 193 struct resource *res; 194 struct ixp4xx_gpio *g; 195 struct gpio_irq_chip *girq; 196 int ret; 197 198 g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL); 199 if (!g) 200 return -ENOMEM; 201 g->dev = dev; 202 203 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 204 g->base = devm_ioremap_resource(dev, res); 205 if (IS_ERR(g->base)) 206 return PTR_ERR(g->base); 207 208 /* 209 * When we convert to device tree we will simply look up the 210 * parent irqdomain using irq_find_host(parent) as parent comes 211 * from IRQCHIP_DECLARE(), then use of_node_to_fwnode() to get 212 * the fwnode. For now we need this boardfile style code. 213 */ 214 if (np) { 215 struct device_node *irq_parent; 216 217 irq_parent = of_irq_find_parent(np); 218 if (!irq_parent) { 219 dev_err(dev, "no IRQ parent node\n"); 220 return -ENODEV; 221 } 222 parent = irq_find_host(irq_parent); 223 if (!parent) { 224 dev_err(dev, "no IRQ parent domain\n"); 225 return -ENODEV; 226 } 227 g->fwnode = of_node_to_fwnode(np); 228 } else { 229 parent = ixp4xx_get_irq_domain(); 230 g->fwnode = irq_domain_alloc_fwnode(&res->start); 231 if (!g->fwnode) { 232 dev_err(dev, "no domain base\n"); 233 return -ENODEV; 234 } 235 } 236 237 /* 238 * Make sure GPIO 14 and 15 are NOT used as clocks but GPIO on 239 * specific machines. 240 */ 241 if (of_machine_is_compatible("dlink,dsm-g600-a") || 242 of_machine_is_compatible("iom,nas-100d")) 243 __raw_writel(0x0, g->base + IXP4XX_REG_GPCLK); 244 245 /* 246 * This is a very special big-endian ARM issue: when the IXP4xx is 247 * run in big endian mode, all registers in the machine are switched 248 * around to the CPU-native endianness. As you see mostly in the 249 * driver we use __raw_readl()/__raw_writel() to access the registers 250 * in the appropriate order. With the GPIO library we need to specify 251 * byte order explicitly, so this flag needs to be set when compiling 252 * for big endian. 253 */ 254 #if defined(CONFIG_CPU_BIG_ENDIAN) 255 flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER; 256 #else 257 flags = 0; 258 #endif 259 260 /* Populate and register gpio chip */ 261 ret = bgpio_init(&g->gc, dev, 4, 262 g->base + IXP4XX_REG_GPIN, 263 g->base + IXP4XX_REG_GPOUT, 264 NULL, 265 NULL, 266 g->base + IXP4XX_REG_GPOE, 267 flags); 268 if (ret) { 269 dev_err(dev, "unable to init generic GPIO\n"); 270 return ret; 271 } 272 g->gc.ngpio = 16; 273 g->gc.label = "IXP4XX_GPIO_CHIP"; 274 /* 275 * TODO: when we have migrated to device tree and all GPIOs 276 * are fetched using phandles, set this to -1 to get rid of 277 * the fixed gpiochip base. 278 */ 279 g->gc.base = 0; 280 g->gc.parent = &pdev->dev; 281 g->gc.owner = THIS_MODULE; 282 283 girq = &g->gc.irq; 284 girq->chip = &ixp4xx_gpio_irqchip; 285 girq->fwnode = g->fwnode; 286 girq->parent_domain = parent; 287 girq->child_to_parent_hwirq = ixp4xx_gpio_child_to_parent_hwirq; 288 girq->handler = handle_bad_irq; 289 girq->default_type = IRQ_TYPE_NONE; 290 291 ret = devm_gpiochip_add_data(dev, &g->gc, g); 292 if (ret) { 293 dev_err(dev, "failed to add SoC gpiochip\n"); 294 return ret; 295 } 296 297 platform_set_drvdata(pdev, g); 298 dev_info(dev, "IXP4 GPIO registered\n"); 299 300 return 0; 301 } 302 303 static const struct of_device_id ixp4xx_gpio_of_match[] = { 304 { 305 .compatible = "intel,ixp4xx-gpio", 306 }, 307 {}, 308 }; 309 310 311 static struct platform_driver ixp4xx_gpio_driver = { 312 .driver = { 313 .name = "ixp4xx-gpio", 314 .of_match_table = of_match_ptr(ixp4xx_gpio_of_match), 315 }, 316 .probe = ixp4xx_gpio_probe, 317 }; 318 builtin_platform_driver(ixp4xx_gpio_driver); 319