xref: /linux/drivers/gpio/gpio-grgpio.c (revision 7a9b709e7cc5ce1ffb84ce07bf6d157e1de758df) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Driver for Aeroflex Gaisler GRGPIO General Purpose I/O cores.
4  *
5  * 2013 (c) Aeroflex Gaisler AB
6  *
7  * This driver supports the GRGPIO GPIO core available in the GRLIB VHDL
8  * IP core library.
9  *
10  * Full documentation of the GRGPIO core can be found here:
11  * http://www.gaisler.com/products/grlib/grip.pdf
12  *
13  * See "Documentation/devicetree/bindings/gpio/gpio-grgpio.txt" for
14  * information on open firmware properties.
15  *
16  * Contributors: Andreas Larsson <andreas@gaisler.com>
17  */
18 
19 #include <linux/bitops.h>
20 #include <linux/err.h>
21 #include <linux/gpio/driver.h>
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/irq.h>
26 #include <linux/irqdomain.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/of.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
32 #include <linux/spinlock.h>
33 #include <linux/string_choices.h>
34 
35 #define GRGPIO_MAX_NGPIO 32
36 
37 #define GRGPIO_DATA		0x00
38 #define GRGPIO_OUTPUT		0x04
39 #define GRGPIO_DIR		0x08
40 #define GRGPIO_IMASK		0x0c
41 #define GRGPIO_IPOL		0x10
42 #define GRGPIO_IEDGE		0x14
43 #define GRGPIO_BYPASS		0x18
44 #define GRGPIO_IMAP_BASE	0x20
45 
46 /* Structure for an irq of the core - called an underlying irq */
47 struct grgpio_uirq {
48 	u8 refcnt; /* Reference counter to manage requesting/freeing of uirq */
49 	u8 uirq; /* Underlying irq of the gpio driver */
50 };
51 
52 /*
53  * Structure for an irq of a gpio line handed out by this driver. The index is
54  * used to map to the corresponding underlying irq.
55  */
56 struct grgpio_lirq {
57 	s8 index; /* Index into struct grgpio_priv's uirqs, or -1 */
58 	u8 irq; /* irq for the gpio line */
59 };
60 
61 struct grgpio_priv {
62 	struct gpio_chip gc;
63 	void __iomem *regs;
64 	struct device *dev;
65 
66 	u32 imask; /* irq mask shadow register */
67 
68 	/*
69 	 * The grgpio core can have multiple "underlying" irqs. The gpio lines
70 	 * can be mapped to any one or none of these underlying irqs
71 	 * independently of each other. This driver sets up an irq domain and
72 	 * hands out separate irqs to each gpio line
73 	 */
74 	struct irq_domain *domain;
75 
76 	/*
77 	 * This array contains information on each underlying irq, each
78 	 * irq of the grgpio core itself.
79 	 */
80 	struct grgpio_uirq uirqs[GRGPIO_MAX_NGPIO];
81 
82 	/*
83 	 * This array contains information for each gpio line on the irqs
84 	 * obtains from this driver. An index value of -1 for a certain gpio
85 	 * line indicates that the line has no irq. Otherwise the index connects
86 	 * the irq to the underlying irq by pointing into the uirqs array.
87 	 */
88 	struct grgpio_lirq lirqs[GRGPIO_MAX_NGPIO];
89 };
90 
91 static void grgpio_set_imask(struct grgpio_priv *priv, unsigned int offset,
92 			     int val)
93 {
94 	struct gpio_chip *gc = &priv->gc;
95 
96 	if (val)
97 		priv->imask |= BIT(offset);
98 	else
99 		priv->imask &= ~BIT(offset);
100 	gc->write_reg(priv->regs + GRGPIO_IMASK, priv->imask);
101 }
102 
103 static int grgpio_to_irq(struct gpio_chip *gc, unsigned offset)
104 {
105 	struct grgpio_priv *priv = gpiochip_get_data(gc);
106 
107 	if (offset >= gc->ngpio)
108 		return -ENXIO;
109 
110 	if (priv->lirqs[offset].index < 0)
111 		return -ENXIO;
112 
113 	return irq_create_mapping(priv->domain, offset);
114 }
115 
116 /* -------------------- IRQ chip functions -------------------- */
117 
118 static int grgpio_irq_set_type(struct irq_data *d, unsigned int type)
119 {
120 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
121 	unsigned long flags;
122 	u32 mask = BIT(d->hwirq);
123 	u32 ipol;
124 	u32 iedge;
125 	u32 pol;
126 	u32 edge;
127 
128 	switch (type) {
129 	case IRQ_TYPE_LEVEL_LOW:
130 		pol = 0;
131 		edge = 0;
132 		break;
133 	case IRQ_TYPE_LEVEL_HIGH:
134 		pol = mask;
135 		edge = 0;
136 		break;
137 	case IRQ_TYPE_EDGE_FALLING:
138 		pol = 0;
139 		edge = mask;
140 		break;
141 	case IRQ_TYPE_EDGE_RISING:
142 		pol = mask;
143 		edge = mask;
144 		break;
145 	default:
146 		return -EINVAL;
147 	}
148 
149 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
150 
151 	ipol = priv->gc.read_reg(priv->regs + GRGPIO_IPOL) & ~mask;
152 	iedge = priv->gc.read_reg(priv->regs + GRGPIO_IEDGE) & ~mask;
153 
154 	priv->gc.write_reg(priv->regs + GRGPIO_IPOL, ipol | pol);
155 	priv->gc.write_reg(priv->regs + GRGPIO_IEDGE, iedge | edge);
156 
157 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
158 
159 	return 0;
160 }
161 
162 static void grgpio_irq_mask(struct irq_data *d)
163 {
164 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
165 	int offset = d->hwirq;
166 	unsigned long flags;
167 
168 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
169 
170 	grgpio_set_imask(priv, offset, 0);
171 
172 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
173 }
174 
175 static void grgpio_irq_unmask(struct irq_data *d)
176 {
177 	struct grgpio_priv *priv = irq_data_get_irq_chip_data(d);
178 	int offset = d->hwirq;
179 	unsigned long flags;
180 
181 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
182 
183 	grgpio_set_imask(priv, offset, 1);
184 
185 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
186 }
187 
188 static struct irq_chip grgpio_irq_chip = {
189 	.name			= "grgpio",
190 	.irq_mask		= grgpio_irq_mask,
191 	.irq_unmask		= grgpio_irq_unmask,
192 	.irq_set_type		= grgpio_irq_set_type,
193 };
194 
195 static irqreturn_t grgpio_irq_handler(int irq, void *dev)
196 {
197 	struct grgpio_priv *priv = dev;
198 	int ngpio = priv->gc.ngpio;
199 	unsigned long flags;
200 	int i;
201 	int match = 0;
202 
203 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
204 
205 	/*
206 	 * For each gpio line, call its interrupt handler if it its underlying
207 	 * irq matches the current irq that is handled.
208 	 */
209 	for (i = 0; i < ngpio; i++) {
210 		struct grgpio_lirq *lirq = &priv->lirqs[i];
211 
212 		if (priv->imask & BIT(i) && lirq->index >= 0 &&
213 		    priv->uirqs[lirq->index].uirq == irq) {
214 			generic_handle_irq(lirq->irq);
215 			match = 1;
216 		}
217 	}
218 
219 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
220 
221 	if (!match)
222 		dev_warn(priv->dev, "No gpio line matched irq %d\n", irq);
223 
224 	return IRQ_HANDLED;
225 }
226 
227 /*
228  * This function will be called as a consequence of the call to
229  * irq_create_mapping in grgpio_to_irq
230  */
231 static int grgpio_irq_map(struct irq_domain *d, unsigned int irq,
232 			  irq_hw_number_t hwirq)
233 {
234 	struct grgpio_priv *priv = d->host_data;
235 	struct grgpio_lirq *lirq;
236 	struct grgpio_uirq *uirq;
237 	unsigned long flags;
238 	int offset = hwirq;
239 	int ret = 0;
240 
241 	if (!priv)
242 		return -EINVAL;
243 
244 	lirq = &priv->lirqs[offset];
245 	if (lirq->index < 0)
246 		return -EINVAL;
247 
248 	dev_dbg(priv->dev, "Mapping irq %d for gpio line %d\n",
249 		irq, offset);
250 
251 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
252 
253 	/* Request underlying irq if not already requested */
254 	lirq->irq = irq;
255 	uirq = &priv->uirqs[lirq->index];
256 	if (uirq->refcnt == 0) {
257 		raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
258 		ret = request_irq(uirq->uirq, grgpio_irq_handler, 0,
259 				  dev_name(priv->dev), priv);
260 		if (ret) {
261 			dev_err(priv->dev,
262 				"Could not request underlying irq %d\n",
263 				uirq->uirq);
264 			return ret;
265 		}
266 		raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
267 	}
268 	uirq->refcnt++;
269 
270 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
271 
272 	/* Setup irq  */
273 	irq_set_chip_data(irq, priv);
274 	irq_set_chip_and_handler(irq, &grgpio_irq_chip,
275 				 handle_simple_irq);
276 	irq_set_noprobe(irq);
277 
278 	return ret;
279 }
280 
281 static void grgpio_irq_unmap(struct irq_domain *d, unsigned int irq)
282 {
283 	struct grgpio_priv *priv = d->host_data;
284 	int index;
285 	struct grgpio_lirq *lirq;
286 	struct grgpio_uirq *uirq;
287 	unsigned long flags;
288 	int ngpio = priv->gc.ngpio;
289 	int i;
290 
291 	irq_set_chip_and_handler(irq, NULL, NULL);
292 	irq_set_chip_data(irq, NULL);
293 
294 	raw_spin_lock_irqsave(&priv->gc.bgpio_lock, flags);
295 
296 	/* Free underlying irq if last user unmapped */
297 	index = -1;
298 	for (i = 0; i < ngpio; i++) {
299 		lirq = &priv->lirqs[i];
300 		if (lirq->irq == irq) {
301 			grgpio_set_imask(priv, i, 0);
302 			lirq->irq = 0;
303 			index = lirq->index;
304 			break;
305 		}
306 	}
307 	WARN_ON(index < 0);
308 
309 	if (index >= 0) {
310 		uirq = &priv->uirqs[lirq->index];
311 		uirq->refcnt--;
312 		if (uirq->refcnt == 0) {
313 			raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
314 			free_irq(uirq->uirq, priv);
315 			return;
316 		}
317 	}
318 
319 	raw_spin_unlock_irqrestore(&priv->gc.bgpio_lock, flags);
320 }
321 
322 static void grgpio_irq_domain_remove(void *data)
323 {
324 	struct irq_domain *domain = data;
325 
326 	irq_domain_remove(domain);
327 }
328 
329 static const struct irq_domain_ops grgpio_irq_domain_ops = {
330 	.map	= grgpio_irq_map,
331 	.unmap	= grgpio_irq_unmap,
332 };
333 
334 /* ------------------------------------------------------------ */
335 
336 static int grgpio_probe(struct platform_device *ofdev)
337 {
338 	struct device_node *np = ofdev->dev.of_node;
339 	struct device *dev = &ofdev->dev;
340 	void  __iomem *regs;
341 	struct gpio_chip *gc;
342 	struct grgpio_priv *priv;
343 	int err;
344 	u32 prop;
345 	s32 *irqmap;
346 	int size;
347 	int i;
348 
349 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
350 	if (!priv)
351 		return -ENOMEM;
352 
353 	regs = devm_platform_ioremap_resource(ofdev, 0);
354 	if (IS_ERR(regs))
355 		return PTR_ERR(regs);
356 
357 	gc = &priv->gc;
358 	err = bgpio_init(gc, dev, 4, regs + GRGPIO_DATA,
359 			 regs + GRGPIO_OUTPUT, NULL, regs + GRGPIO_DIR, NULL,
360 			 BGPIOF_BIG_ENDIAN_BYTE_ORDER);
361 	if (err) {
362 		dev_err(dev, "bgpio_init() failed\n");
363 		return err;
364 	}
365 
366 	priv->regs = regs;
367 	priv->imask = gc->read_reg(regs + GRGPIO_IMASK);
368 	priv->dev = dev;
369 
370 	gc->owner = THIS_MODULE;
371 	gc->to_irq = grgpio_to_irq;
372 	gc->label = devm_kasprintf(dev, GFP_KERNEL, "%pOF", np);
373 	if (!gc->label)
374 		return -ENOMEM;
375 
376 	gc->base = -1;
377 
378 	err = of_property_read_u32(np, "nbits", &prop);
379 	if (err || prop <= 0 || prop > GRGPIO_MAX_NGPIO) {
380 		gc->ngpio = GRGPIO_MAX_NGPIO;
381 		dev_dbg(dev, "No or invalid nbits property: assume %d\n",
382 			gc->ngpio);
383 	} else {
384 		gc->ngpio = prop;
385 	}
386 
387 	/*
388 	 * The irqmap contains the index values indicating which underlying irq,
389 	 * if anyone, is connected to that line
390 	 */
391 	irqmap = (s32 *)of_get_property(np, "irqmap", &size);
392 	if (irqmap) {
393 		if (size < gc->ngpio) {
394 			dev_err(dev,
395 				"irqmap shorter than ngpio (%d < %d)\n",
396 				size, gc->ngpio);
397 			return -EINVAL;
398 		}
399 
400 		priv->domain = irq_domain_add_linear(np, gc->ngpio,
401 						     &grgpio_irq_domain_ops,
402 						     priv);
403 		if (!priv->domain) {
404 			dev_err(dev, "Could not add irq domain\n");
405 			return -EINVAL;
406 		}
407 
408 		err = devm_add_action_or_reset(dev, grgpio_irq_domain_remove,
409 					       priv->domain);
410 		if (err)
411 			return err;
412 
413 		for (i = 0; i < gc->ngpio; i++) {
414 			struct grgpio_lirq *lirq;
415 			int ret;
416 
417 			lirq = &priv->lirqs[i];
418 			lirq->index = irqmap[i];
419 
420 			if (lirq->index < 0)
421 				continue;
422 
423 			ret = platform_get_irq(ofdev, lirq->index);
424 			if (ret <= 0) {
425 				/*
426 				 * Continue without irq functionality for that
427 				 * gpio line
428 				 */
429 				continue;
430 			}
431 			priv->uirqs[lirq->index].uirq = ret;
432 		}
433 	}
434 
435 	err = devm_gpiochip_add_data(dev, gc, priv);
436 	if (err) {
437 		dev_err(dev, "Could not add gpiochip\n");
438 		return err;
439 	}
440 
441 	dev_info(dev, "regs=0x%p, base=%d, ngpio=%d, irqs=%s\n",
442 		 priv->regs, gc->base, gc->ngpio, str_on_off(priv->domain));
443 
444 	return 0;
445 }
446 
447 static const struct of_device_id grgpio_match[] = {
448 	{.name = "GAISLER_GPIO"},
449 	{.name = "01_01a"},
450 	{},
451 };
452 
453 MODULE_DEVICE_TABLE(of, grgpio_match);
454 
455 static struct platform_driver grgpio_driver = {
456 	.driver = {
457 		.name = "grgpio",
458 		.of_match_table = grgpio_match,
459 	},
460 	.probe = grgpio_probe,
461 };
462 module_platform_driver(grgpio_driver);
463 
464 MODULE_AUTHOR("Aeroflex Gaisler AB.");
465 MODULE_DESCRIPTION("Driver for Aeroflex Gaisler GRGPIO");
466 MODULE_LICENSE("GPL");
467